4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
d565b44a98
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
...
llvm-svn: 116368
2010-10-12 23:19:28 +00:00
604e142844
Combine these together - should probably have some text associated
...
that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
...
llvm-svn: 116323
2010-10-12 18:18:03 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
...
llvm-svn: 116319
2010-10-12 18:00:49 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
...
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
35e6ce479c
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
626656a562
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
8f21f9c1fb
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
5b2a411c77
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
e2245542ce
Use the new TB_NOT_REVERSABLE flag instead of special
...
casing FsMOVAPDrr/FsMOVAPSrr.
llvm-svn: 116016
2010-10-08 00:03:02 +00:00
0921bfdf36
simplify some map operations.
...
llvm-svn: 116014
2010-10-07 23:57:02 +00:00
4fb38d3cd3
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
1c090c00bc
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
70a7b54f97
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
f5c60d8156
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
a8c0bbb869
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
9fece2bea2
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
752b60bc01
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
c6a6e9ba7c
Fix obvious mistake pointed out by Michael Spencer.
...
llvm-svn: 115952
2010-10-07 18:47:10 +00:00
67677515ac
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
4fc52f6fa0
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
...
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
94eff91dc0
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
...
register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
...
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
...
convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
...
and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
...
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
...
not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
...
llvm-svn: 115692
2010-10-05 22:01:02 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
8f4f1d1136
move SETB pseudos into the same place in InstrCompiler.td
...
llvm-svn: 115686
2010-10-05 21:18:04 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
ab85ef9e55
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
27c763d342
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
...
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
c2f5e5764f
continue moving 64-bit stuff into X86InstrArithmetic.td
...
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
7552d15d19
move 64-bit add and adc to InstrArithmetic.
...
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
182e87caaf
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
...
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
39c70f4833
split the 32-bit integer arithmetic instructions out to their own file.
...
llvm-svn: 115627
2010-10-05 16:39:12 +00:00
1818dd510e
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
...
llvm-svn: 115608
2010-10-05 07:13:35 +00:00
1b3aa8678e
move 32-bit shift and rotates out to their own file.
...
llvm-svn: 115607
2010-10-05 07:00:12 +00:00
89497a990e
add new file
...
llvm-svn: 115606
2010-10-05 06:52:35 +00:00
a68466c202
move sign and zero extensions out to their own file.
...
llvm-svn: 115605
2010-10-05 06:52:26 +00:00
84571a1581
move some instructions from Instr64Bit -> InstrInfo.
...
bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
da8c94ef44
move CMOV_FR32 and friends to InstrCompiler, since they are
...
pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
44a5a2b569
move various pattern matching support goop out of X86Instr64Bit, to live
...
with the 32-bit stuff.
llvm-svn: 115602
2010-10-05 06:37:31 +00:00
fa9b058eef
split conditional moves and setcc's out to their own file.
...
llvm-svn: 115601
2010-10-05 06:33:16 +00:00
f9594ba4e7
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
...
llvm-svn: 115600
2010-10-05 06:27:48 +00:00
c184a57e98
move the atomic pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115599
2010-10-05 06:22:35 +00:00
c793f8bca6
move more pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115598
2010-10-05 06:10:16 +00:00
52d3935dfe
move VMX instructions out to their own file.
...
llvm-svn: 115597
2010-10-05 06:06:53 +00:00
ae33f5d93b
continue moving stuff out to X86InstrSystem.td. Move
...
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
llvm-svn: 115596
2010-10-05 06:04:14 +00:00
dec85b8c64
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
...
llvm-svn: 115591
2010-10-05 05:32:15 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
d77a443631
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
ae1a9de083
stub out a header to put 3dNow! instructions into.
...
llvm-svn: 115429
2010-10-02 23:06:23 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
14e909a942
Delete token *after* reading from it.
...
llvm-svn: 115311
2010-10-01 12:25:27 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
c6e13f7383
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
0574cc556a
Noticed by inspection when looking for other cmov bits.
...
llvm-svn: 115100
2010-09-29 23:00:29 +00:00
23ebf4b319
Add parens to fix GCC warning:
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lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
llvm-svn: 115064
2010-09-29 18:56:57 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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llvm-svn: 115061
2010-09-29 18:39:16 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
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llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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llvm-svn: 115027
2010-09-29 04:55:40 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
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order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
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are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
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operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
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Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
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llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
786874de82
MMX parameters aren't handled here yet.
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llvm-svn: 114844
2010-09-27 17:29:47 +00:00
b6a7f97c88
yet more aliases.
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llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
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llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
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llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
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My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
b5b71e07af
improve indentation
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llvm-svn: 114815
2010-09-27 06:34:01 +00:00
422e463be7
This code should never fire on non-darwin subtargets.
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llvm-svn: 114811
2010-09-27 06:01:51 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
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but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
75d65b9a03
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
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symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
6a4cd59b08
We can't return SSE/MMX vectors if SSE is disabled.
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llvm-svn: 114745
2010-09-24 19:05:48 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
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llvm-svn: 114703
2010-09-23 22:57:01 +00:00
bbb9287080
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
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llvm-svn: 114597
2010-09-22 22:35:21 +00:00
c1b3e072f4
Temporarily work around new address lowering while I figure out what
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needs to happen for darwin.
llvm-svn: 114577
2010-09-22 20:42:08 +00:00
e1223fb583
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
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ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
llvm-svn: 114554
2010-09-22 17:35:14 +00:00
415624cf3f
fix rdar://8456371 - Handle commutable instructions written backward.
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llvm-svn: 114536
2010-09-22 06:26:39 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
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x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
37fc469f88
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
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Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
9dfd2e354e
add the missing aliases for fp stack cmovs, rdar://8456391
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llvm-svn: 114531
2010-09-22 04:56:20 +00:00
8a236b63d8
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
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llvm-svn: 114529
2010-09-22 04:39:11 +00:00
1261b81e82
Fix rdar://8456364 - llvm-mc rejects '%CS'
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llvm-svn: 114528
2010-09-22 04:11:10 +00:00
39cf8deded
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
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-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
a91e510f94
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
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llvm-svn: 114526
2010-09-22 03:50:32 +00:00
a5156c30ed
convert the last 4 X86ISD nodes that should have memoperands to have them.
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llvm-svn: 114523
2010-09-22 01:28:21 +00:00
ed85da5600
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
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can access the stack due to how it is generated though.
llvm-svn: 114522
2010-09-22 01:11:26 +00:00
78f518b79b
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
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used with stack slots, but hey, lets be safe.
llvm-svn: 114521
2010-09-22 01:05:16 +00:00
54e5329545
give VZEXT_LOAD a memory operand, it now works with segment registers.
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llvm-svn: 114515
2010-09-22 00:34:38 +00:00
07827ba978
revert r114386 now that address modes work correctly, we get a nice
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call through gs-relative memory now.
llvm-svn: 114510
2010-09-22 00:11:31 +00:00
e479e9643b
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
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llvm-svn: 114508
2010-09-21 23:59:42 +00:00
Rafael Espindola