Commit Graph

114639 Commits

Author SHA1 Message Date
Justin Bogner f19da3c33a Now that r231902's test is executed, make it actually pass
As of r231908, the test I added in r231902 actually gets run - but I'd
checked in a stale version of the input so it didn't pass. Fix the
input and un-xfail the test.

llvm-svn: 231911
2015-03-11 08:17:25 +00:00
Owen Anderson a3c68fdf82 Fix another verifier crash where a GC intrinsic would look at the internals of another intrinsic in order to verify itself.
This causes a crash if the referenced intrinsic was malformed.  In this case, we
would already have reported an error on the referenced intrinsic, but then
crashed on the second one when it tried to introspect the first without
error checking.

llvm-svn: 231910
2015-03-11 06:57:30 +00:00
Daniel Jasper 92e701b16f Make test added in r231902 actually be executed.
There were also errors in the CHECK line which I fixed and the test
doesn't actually pass as the "100" is in the wrong line. Not sure
whether this is a test failure or a coverage failure so making the test
XFAIL for now.

llvm-svn: 231908
2015-03-11 06:44:51 +00:00
Rafael Espindola 23562fcfe9 Don't print labels that on ELF are never used.
llvm-svn: 231904
2015-03-11 04:20:31 +00:00
Justin Bogner 4379535e3f InstrProf: Teach llvm-cov to handle universal binaries when given -arch
llvm-svn: 231902
2015-03-11 02:30:51 +00:00
Rafael Espindola d9f6e5daaa Relax label CHECK to mach COFF syntax.
Should fix the cygwin bots.

I added a cygwin specific test that would have caught this on Linux.

llvm-svn: 231899
2015-03-11 01:08:32 +00:00
Rafael Espindola f1a13f5ad5 Print section start labels when first switching to the section.
This is less brittle and avoids polluting the start of the file with every
debug section.

llvm-svn: 231898
2015-03-11 00:51:37 +00:00
Lang Hames b11860362d [Orc][MCJIT][RuntimeDyld] Re-apply r231726 and r231724 with fix suggested by
Dave Blaikie. Thanks Dave!

llvm-svn: 231896
2015-03-11 00:43:26 +00:00
Chandler Carruth 04b997e517 Fix a grammar issue I introduced.
llvm-svn: 231894
2015-03-11 00:19:01 +00:00
Chandler Carruth dfcd3dcf81 Inspired by r231891, use gender neutral pronouns in the places I've
found in LLVM.

llvm-svn: 231893
2015-03-11 00:15:44 +00:00
Andrew Kaylor b93fb82b3f Fix Value dangling reference debug output
llvm-svn: 231889
2015-03-10 23:55:38 +00:00
Eric Christopher 433c432b7e Have TargetRegisterInfo::getLargestLegalSuperClass take a
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

llvm-svn: 231888
2015-03-10 23:46:01 +00:00
Eric Christopher c4d3140524 Remove subtarget dependence from HexagonRegisterInfo.
llvm-svn: 231887
2015-03-10 23:45:55 +00:00
Rafael Espindola 9b8a4e301a Split test in two to handle building without x86.
llvm-svn: 231886
2015-03-10 23:44:12 +00:00
Eric Christopher 49338e9fa6 Remove dead code.
llvm-svn: 231883
2015-03-10 23:22:04 +00:00
Rafael Espindola b03bc79bed Add missing section symbol to COFF's .debug_types.dwo.
Should bring the cygwin bots back.

I added a triple to the test that was failing so that it would have failed
on Linux.

llvm-svn: 231882
2015-03-10 23:06:32 +00:00
Philip Reames 71c4035c18 If a conditional branch jumps to the same target, remove the condition
Given that large parts of inst combine is restricted to instructions which have one use, getting rid of a use on the condition can help the effectiveness of the optimizer. Also, it allows the condition to potentially be deleted by instcombine rather than waiting for another pass.

I noticed this completely by accident in another test case. It's not anything that actually came from a real workload.

p.s. We should probably do the same thing for switch instructions.

Differential Revision: http://reviews.llvm.org/D8220

llvm-svn: 231881
2015-03-10 22:52:37 +00:00
Paul Robinson 857b4434df Emit correct linkage-name attribute based on DWARF version.
There are still 4 tests that check for DW_AT_MIPS_linkage_name,
because they specify DWARF 2 or 3 in the module metadata. So, I didn't
create an explicit version-based test for the attribute.

Differential Revision: http://reviews.llvm.org/D8227

llvm-svn: 231880
2015-03-10 22:44:45 +00:00
Philip Reames 1c29227144 Infer known bits from dominating conditions
This patch adds limited support in ValueTracking for inferring known bits of a value from conditional expressions which must be true to reach the instruction we're trying to optimize. At this time, the feature is off by default. Once landed, I'm hoping for feedback from others on both profitability and compile time impact.

Forms of conditional value propagation have been tried in LLVM before and have failed due to compile time problems.  In an attempt to side step that, this patch only considers conditions where the edge leaving the branch dominates the context instruction. It does not attempt full dataflow.  Even with that restriction, it handles many interesting cases:
 * Early exits from functions
 * Early exits from loops (for context instructions in the loop and after the check)
 * Conditions which control entry into loops, including multi-version loops (such as those produced during vectorization, IRCE, loop unswitch, etc..)

Possible applications include optimizing using information provided by constructs such as: preconditions, assumptions, null checks, & range checks.

This patch implements two approaches to the problem that need further benchmarking.  Approach 1 is to directly walk the dominator tree looking for interesting conditions.  Approach 2 is to inspect other uses of the value being queried for interesting comparisons.  From initial benchmarking, it appears that Approach 2 is faster than Approach 1, but this needs to be further validated.  

Differential Revision: http://reviews.llvm.org/D7708

llvm-svn: 231879
2015-03-10 22:43:20 +00:00
Eric Christopher 0169e42c3b Remove the use of the subtarget in MCCodeEmitter creation and
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

llvm-svn: 231861
2015-03-10 22:03:14 +00:00
Rafael Espindola 6b9998b3eb Create symbols marking the start of a section earlier.
This lets us pass the symbol to the constructor and avoid the mutable field.

This also opens the way for outputting the symbol only when needed, instead
of outputting them at the start of the file.

llvm-svn: 231859
2015-03-10 22:00:25 +00:00
Eric Christopher 501d5e9f66 Remove createAMDGPUMCCodeEmitter and instead just register the correct
MCCodeEmitter creation routine based on TargetMachine since the only
64-bit R600 gpus are part of the GCN target.

llvm-svn: 231856
2015-03-10 21:57:34 +00:00
Quentin Colombet 1b274f99ad [CodeGenPrepare] Refine the cost model provided by the promotion helper.
- Use TargetLowering to check for the actual cost of each extension.
- Provide a factorized method to check for the cost of an extension:
  TargetLowering::isExtFree.
- Provide a virtual method TargetLowering::isExtFreeImpl for targets to be able
  to tune the cost of non-free extensions.

This refactoring offers a better granularity to model what really happens on
different targets.

No performance changes and very few code differences.

Part of <rdar://problem/19267165> 

llvm-svn: 231855
2015-03-10 21:48:15 +00:00
Adam Nemet 4bb90a71de [LoopAccesses] Add debug message to indicate the result of the analysis
The debug message was pretty confusing here.  It only reported the
situation with memchecks without the result of the dependence analysis.

Now it prints whether the loop is safe from the POV of the dependence
analysis and if yes, whether we need memchecks.

llvm-svn: 231854
2015-03-10 21:47:39 +00:00
Rafael Espindola ceb96a4cb8 Move a non-trivial virtual function out of line.
llvm-svn: 231853
2015-03-10 21:35:16 +00:00
Colin LeMahieu bdc6c83d24 [Hexagon] Adding frame index + add load/store patterns.
llvm-svn: 231850
2015-03-10 21:24:13 +00:00
Rafael Espindola 6ed58a2d91 clang-format code that is about to change.
llvm-svn: 231848
2015-03-10 21:16:18 +00:00
Colin LeMahieu 3901c066e0 [Hexagon] Simplifying deallocret definitions.
llvm-svn: 231847
2015-03-10 21:12:32 +00:00
Rafael Espindola 0be4c2b0d4 clang-format these declarations. NFC.
llvm-svn: 231846
2015-03-10 21:05:09 +00:00
Rafael Espindola aecf6a874b Don't repeat names in comments. NFC.
llvm-svn: 231845
2015-03-10 21:01:50 +00:00
Colin LeMahieu 4e90d2136f [Hexagon] Separating InstHexagon from OpcodeHexagon.
llvm-svn: 231844
2015-03-10 20:56:22 +00:00
Nemanja Ivanovic 0adf26b9b0 Add support for part-word atomics for PPC
http://reviews.llvm.org/D8090#inline-67337

llvm-svn: 231843
2015-03-10 20:51:07 +00:00
Chris Bieneman da91ceb860 Add new LLVM_OPTIMIZED_TABLEGEN build setting which configures, builds and uses a release tablegen build when LLVM is configured with assertions enabled.
Summary: This change leverages the cross-compiling functionality in the build system to build a release tablegen executable for use during the build.

Reviewers: resistor, rnk

Reviewed By: rnk

Subscribers: rnk, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D7349

llvm-svn: 231842
2015-03-10 20:48:02 +00:00
Ahmed Bougacha fab5892f8b [AArch64] Avoid going through GPRs for across-vector instructions.
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
  (v4i32 (uaddv ...))
is the same as
  (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
  (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
           (i32 (int_aarch64_neon_uaddv ...)), ssub)

In a combine, we transform all such across-vector-lanes intrinsics to:

  (i32 (extract_vector_elt (uaddv ...), 0))

This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs.  Consider:

    uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
        return vmulq_n_u32(a, vaddvq_u32(b));
    }

We now generate:
    addv.4s  s1, v1
    mul.4s   v0, v0, v1[0]
instead of the previous:
    addv.4s  s1, v1
    fmov     w8, s1
    dup.4s   v1, w8
    mul.4s   v0, v1, v0

rdar://20044838

llvm-svn: 231840
2015-03-10 20:45:38 +00:00
Ahmed Bougacha 8f6a115de9 [AArch64] Remove integer INSvi*lane patterns. NFCI.
Most are redundant, and they never seem to fire.

The V128 integer patterns already exist in the INS multiclass.
The duplicates only fire when the vector index type isn't i64,
because they accept "imm" instead of an explicit "i64", as the
instruction definition patterns do.

TLI::getVectorIdxTy is i64 on AArch64, so this should never happen.
Also, one of them had a typo: for i64, INSvi32lane was used.
I noticed because I mistakenly used an explicit i32 as the idx type,
and got ins.s for an i64 vector_insert.

The V64 patterns also don't seem to ever fire, as V64 vector
extract/insert are legalized to V128.

The equivalent float patterns are unique and useful, so keep them.

No functional change intended;  none exhibited on the LIT and LNT tests.

llvm-svn: 231838
2015-03-10 20:37:19 +00:00
Chad Rosier 99fb8d17ec Don't evaluate rend() on every iteration of the loop.
llvm-svn: 231837
2015-03-10 20:29:59 +00:00
David Majnemer d388e930ce LoopAccessAnalysis: Silence -Wreturn-type diagnostic from GCC
llvm-svn: 231836
2015-03-10 20:23:29 +00:00
Benjamin Kramer d58792f38b Don't use LLVM_LIBRARY_VISIBILITY in cpp files.
llvm-svn: 231831
2015-03-10 20:07:44 +00:00
Bruno Cardoso Lopes b3a58b4c3c [AsmPrinter][TLOF] Reintroduce AArch64 test
Follow up from r231505.

Fix the non-determinism by using a MapVector and reintroduce the AArch64
testcase. Defer deleting the got candidates up to the end and remove
them in a bulk, avoiding linear time removal of each element.

Thanks to Renato Golin for trying it out on other platforms.

llvm-svn: 231830
2015-03-10 20:05:23 +00:00
Colin LeMahieu 60a99e66a0 [Hexagon] Adding nodes for PIC support.
llvm-svn: 231829
2015-03-10 20:04:44 +00:00
Colin LeMahieu 092d9c18a8 [Hexagon] Adding DuplexInst instruction format and duplex class defs.
llvm-svn: 231828
2015-03-10 19:53:14 +00:00
Kit Barton 20d3981e15 Change the generation of the vmuluwm instruction to be based on the MUL opcode.
Phabricator review: http://reviews.llvm.org/D8185

llvm-svn: 231827
2015-03-10 19:49:38 +00:00
Sanjay Patel 0fdb437b25 remove function names from comments; NFC
llvm-svn: 231826
2015-03-10 19:42:57 +00:00
Colin LeMahieu 3b6747df13 [Hexagon] Adding nodes for vector insert/extract lowering.
llvm-svn: 231825
2015-03-10 19:40:03 +00:00
Colin LeMahieu ee776452f9 [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
llvm-svn: 231824
2015-03-10 19:29:53 +00:00
Adrian Prantl 51233680ae Change the datatype of DwarfExpression::Emit(Un)Signed to (u)int64_t
so it matches the one used by ByteStreamer::Emit(U|S)LEB128.

llvm-svn: 231823
2015-03-10 19:23:37 +00:00
Benjamin Kramer 414c0964c3 NVPTX: move NVPTXAllocaHoisting into the cpp file
Also initialize without using static initialization.

llvm-svn: 231822
2015-03-10 19:20:52 +00:00
Adam Nemet 949e91a6fa [LAA-memchecks] Comment improvement
I forgot to roll this into r231816.  It was requested by Hal in D8122.

llvm-svn: 231821
2015-03-10 19:12:41 +00:00
Michael Zolotukhin 267e12f714 Enable loop-rotate before loop-vectorize by default
llvm-svn: 231820
2015-03-10 19:07:41 +00:00
Adam Nemet ec1e2bb6a4 [LAA-memchecks 3/3] Introduce pointer partitions for memchecks
This is the final patch that actually introduces the new parameter of
partition mapping to RuntimePointerCheck::needsChecking.

Another API (LAI::getInstructionsForAccess) is also exposed that helps
to map pointers to instructions because ultimately we partition
instructions.

The WIP version of the Loop Distribution pass in D6930 has been adapted
to use all this.  See for example, how
InstrPartitionContainer::computePartitionSetForPointers sets up the
partitions using the above API and then calls to LAI::addRuntimeCheck
with the pointer partitions.

llvm-svn: 231818
2015-03-10 18:54:26 +00:00