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Author SHA1 Message Date
Evan Cheng ef0b7cc2d5 On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead. 
llvm-svn: 66776
 2009-03-12 05:59:15 +00:00
Chris Lattner 1d5cf4bcdd add nounwinds 
llvm-svn: 66773
 2009-03-12 05:35:33 +00:00
Dan Gohman 5637df37cd Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the 
assembly text output uses an indirect call ("call *") instead of a direct call.

llvm-svn: 66735
 2009-03-11 23:01:47 +00:00
Rafael Espindola 294943c99b optimize i8 and i16 tls values. 
llvm-svn: 66725
 2009-03-11 22:40:04 +00:00
Evan Cheng 6cba561648 My last coalescer fix introduced a subtler one. It's aborting a commuting optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. 
llvm-svn: 66715
 2009-03-11 22:18:44 +00:00
Mon P Wang 25c6a46a81 For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits. 
llvm-svn: 66684
 2009-03-11 18:47:57 +00:00
Mon P Wang ce6a26cb1a Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw. 
llvm-svn: 66645
 2009-03-11 06:35:11 +00:00
Chris Lattner 43d6377f89 reapply my previous patch (r66358) with a tweak to set the 
alignment of the generated constant pool entry to the
desired alignment of a type.  If we don't do this, we end up
trying to do movsd from 4-byte alignment memory.  This fixes
450.soplex and 456.hmmer.

llvm-svn: 66641
 2009-03-11 05:08:08 +00:00
Evan Cheng 64b3f9d7a7 Two coalescer fixes in one. 
1. Use the same value# to represent unknown values being merged into sub-registers.
2. When coalescer commute an instruction and the destination is a physical register, update its sub-registers by merging in the extended ranges.

llvm-svn: 66610
 2009-03-11 00:03:21 +00:00
Bill Wendling 63144deea9 Readd test, but XFAIL it. 
llvm-svn: 66581
 2009-03-10 21:31:00 +00:00
Evan Cheng aa887653f4 Revert 66358 for now. It's breaking povray, 450.soplex, and 456.hmmer on x86 / Darwin. 
llvm-svn: 66574
 2009-03-10 20:47:18 +00:00
Bill Wendling a042a82408 Add radar number. 
llvm-svn: 66534
 2009-03-10 06:53:54 +00:00
Chris Lattner 4249b9a698 Fix PR3763 by using proper APInt methods instead of uint64_t's. 
llvm-svn: 66434
 2009-03-09 20:22:18 +00:00
Evan Cheng fb8ded911e Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706. 
llvm-svn: 66428
 2009-03-09 19:00:05 +00:00
Chris Lattner ab5a443144 implement an optimization to codegen c ? 1.0 : 2.0 as load { 2.0, 1.0 } + c*4. 
For 2009-03-07-FPConstSelect.ll we now produce:

_f:
	xorl	%eax, %eax
	testl	%edi, %edi
	movl	$4, %ecx
	cmovne	%rax, %rcx
	leaq	LCPI1_0(%rip), %rax
	movss	(%rcx,%rax), %xmm0
	ret

previously we produced:

_f:
	subl	$4, %esp
	cmpl	$0, 8(%esp)
	movss	LCPI1_0, %xmm0
	je	LBB1_2	## entry
LBB1_1:	## entry
	movss	LCPI1_1, %xmm0
LBB1_2:	## entry
	movss	%xmm0, (%esp)
	flds	(%esp)
	addl	$4, %esp
	ret

on PPC the code also improves to:

_f:
	cntlzw r2, r3
	srwi r2, r2, 5
	li r3, lo16(LCPI1_0)
	slwi r2, r2, 2
	addis r3, r3, ha16(LCPI1_0)
	lfsx f1, r3, r2
	blr 

from:

_f:
	li r2, lo16(LCPI1_1)
	cmplwi cr0, r3, 0
	addis r2, r2, ha16(LCPI1_1)
	beq cr0, LBB1_2	; entry
LBB1_1:	; entry
	li r2, lo16(LCPI1_0)
	addis r2, r2, ha16(LCPI1_0)
LBB1_2:	; entry
	lfs f1, 0(r2)
	blr 

This also improves the existing pic-cpool case from:

foo:
	subl	$12, %esp
	call	.Lllvm$1.$piclabel
.Lllvm$1.$piclabel:
	popl	%eax
	addl	$_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$1.$piclabel], %eax
	cmpl	$0, 16(%esp)
	movsd	.LCPI1_0@GOTOFF(%eax), %xmm0
	je	.LBB1_2	# entry
.LBB1_1:	# entry
	movsd	.LCPI1_1@GOTOFF(%eax), %xmm0
.LBB1_2:	# entry
	movsd	%xmm0, (%esp)
	fldl	(%esp)
	addl	$12, %esp
	ret

to:

foo:
	call	.Lllvm$1.$piclabel
.Lllvm$1.$piclabel:
	popl	%eax
	addl	$_GLOBAL_OFFSET_TABLE_ + [.-.Lllvm$1.$piclabel], %eax
	xorl	%ecx, %ecx
	cmpl	$0, 4(%esp)
	movl	$8, %edx
	cmovne	%ecx, %edx
	fldl	.LCPI1_0@GOTOFF(%eax,%edx)
	ret

This triggers a few dozen times in spec FP 2000.

llvm-svn: 66358
 2009-03-08 01:51:30 +00:00
Dan Gohman ff659b5b86 Arithmetic instructions don't set EFLAGS bits OF and CF bits 
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.

llvm-svn: 66318
 2009-03-07 01:58:32 +00:00
Dan Gohman 15af5524a4 Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodes 
with multiple chain operands. This can occur when the scheduler
has added chain operands to a node that already has a chain
operand, in order to handle physical register dependencies.

This fixes an llvm-gcc bootstrap failure on x86-64 introduced
in r66058.

llvm-svn: 66240
 2009-03-06 02:23:01 +00:00
Dan Gohman 2c2f192c74 Fix the "test" optimization to recognize "dec" as an add of 
negative one, as subtracts of immediates are canonicalized
to adds.

llvm-svn: 66180
 2009-03-05 19:32:48 +00:00
Dan Gohman 14cc4a458e Make this test more thorough. Not only should there be no %esi, 
there should be no spilling of anything.

llvm-svn: 66179
 2009-03-05 19:31:32 +00:00
Evan Cheng b7922dee15 Do not split edges to EH landing pads. It will cause code size explosion. 
llvm-svn: 66140
 2009-03-05 06:31:26 +00:00
Dan Gohman 55d7b2ac4f Re-apply 66008, now that the unfoldMemoryOperand bug is fixed. 
llvm-svn: 66058
 2009-03-04 19:44:21 +00:00
Owen Anderson 0dedc114de Add a restore folder, which shaves a dozen or so machineinstrs off oggenc. Update a testcase to check this. 
llvm-svn: 66029
 2009-03-04 08:52:31 +00:00
Evan Cheng 9edd616b59 Fix PR3666: isel calls to constant addresses. 
llvm-svn: 66024
 2009-03-04 06:48:53 +00:00
Eli Friedman 7604d37723 PR3686: make the legalizer handle bitcast from i80 to x86 long double. 
llvm-svn: 66021
 2009-03-04 06:23:34 +00:00
Dan Gohman 6728f892be Revert r66004 for now; it's causing a variety of test failures. 
llvm-svn: 66008
 2009-03-04 03:54:19 +00:00
Evan Cheng e08f4cb9a1 Rename test. 
llvm-svn: 66006
 2009-03-04 02:47:25 +00:00
Dan Gohman fe8d71f42a Teach the x86 backend to eliminate "test" instructions by using the EFLAGS 
result from add, sub, inc, and dec instructions in simple cases.

llvm-svn: 66004
 2009-03-04 02:33:24 +00:00
Evan Cheng b8905c4e2c Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. 
llvm-svn: 65996
 2009-03-04 01:41:49 +00:00
Bill Wendling 6d2714738f The DAG combiner was performing a BT combine. The BT combine had a value of -1, 
so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it
would go through the DAG combiner again. This time it had a value of 31, which
was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong
forever.

Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded
value is an XOR of all ones.

llvm-svn: 65985
 2009-03-04 00:18:06 +00:00
Nate Begeman a9e981225e Fix a problem with DAGCombine on 64b targets where folding 
extracts + build_vector into a shuffle would fail, because the
type of the new build_vector would not be legal.  Try harder to
create a legal build_vector type.  Note: this will be totally 
irrelevant once vector_shuffle no longer takes a build_vector for
shuffle mask.

New:
_foo:
	xorps	%xmm0, %xmm0
	xorps	%xmm1, %xmm1
	subps	%xmm1, %xmm1
	mulps	%xmm0, %xmm1
	addps	%xmm0, %xmm1
	movaps	%xmm1, 0

Old:
_foo:
	xorps	%xmm0, %xmm0
	movss	%xmm0, %xmm1
	xorps	%xmm2, %xmm2
	unpcklps	%xmm1, %xmm2
	pshufd	$80, %xmm1, %xmm1
	unpcklps	%xmm1, %xmm2
	pslldq	$16, %xmm2
	pshufd	$57, %xmm2, %xmm1
	subps	%xmm0, %xmm1
	mulps	%xmm0, %xmm1
	addps	%xmm0, %xmm1
	movaps	%xmm1, 0

llvm-svn: 65791
 2009-03-01 23:44:07 +00:00
Evan Cheng c2f95b56db Minor optimization: 
Look for situations like this:                                                                                                                                                              
%reg1024<def> = MOV r1                                                                                                                                                                      
%reg1025<def> = MOV r0                                                                                                                                                                      
%reg1026<def> = ADD %reg1024, %reg1025                                                                                                                                                      
r0            = MOV %reg1026                                                                                                                                                                
Commute the ADD to hopefully eliminate an otherwise unavoidable copy.

llvm-svn: 65752
 2009-03-01 02:03:43 +00:00
Rafael Espindola 000421eade Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.

llvm-svn: 65632
 2009-02-27 13:37:18 +00:00
Evan Cheng 2ad43a97cc Make sure this test passes on linux-ppc. 
llvm-svn: 65600
 2009-02-27 00:51:50 +00:00
Evan Cheng 8d0b4d4fd6 MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. 
llvm-svn: 65592
 2009-02-27 00:02:22 +00:00
Evan Cheng 40abb7b5d0 ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. 
llvm-svn: 65499
 2009-02-26 03:12:02 +00:00
Evan Cheng a49de9de2e Revert BuildVectorSDNode related patches: 65426, 65427, and 65296. 
llvm-svn: 65482
 2009-02-25 22:49:59 +00:00
Dan Gohman 318d7376ba Fast-isel can't do TLS yet, so it should fall back to SDISel 
if it sees TLS addresses.

llvm-svn: 65341
 2009-02-23 22:03:08 +00:00
Dan Gohman 0fd45016c2 Use the -stack-alignment option instead of using a target triple 
for avoiding dynamic stack realignment.

llvm-svn: 65319
 2009-02-23 16:34:46 +00:00
Evan Cheng 9f8fddeed8 Only v1i16 (i.e. _m64) is returned via RAX / RDX. 
llvm-svn: 65313
 2009-02-23 09:03:22 +00:00
Nate Begeman 9af0d0c97e Make this test use darwin targe triple, to avoid stack traffic on linux. 
llvm-svn: 65312
 2009-02-23 09:03:06 +00:00
Nate Begeman e684da3e5d Generate better code for v8i16 shuffles on SSE2 
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
  cleanups.
New tests that test the above.

Examples:

New:
_shuf2:
	pextrw	$7, %xmm0, %eax
	punpcklqdq	%xmm1, %xmm0
	pshuflw	$128, %xmm0, %xmm0
	pinsrw	$2, %eax, %xmm0

Old:
_shuf2:
	pextrw	$2, %xmm0, %eax
	pextrw	$7, %xmm0, %ecx
	pinsrw	$2, %ecx, %xmm0
	pinsrw	$3, %eax, %xmm0
	movd	%xmm1, %eax
	pinsrw	$4, %eax, %xmm0
	ret

=========

New:
_shuf4:
	punpcklqdq	%xmm1, %xmm0
	pshufb	LCPI1_0, %xmm0

Old:
_shuf4:
	pextrw	$3, %xmm0, %eax
	movsd	%xmm1, %xmm0
	pextrw	$3, %xmm1, %ecx
	pinsrw	$4, %ecx, %xmm0
	pinsrw	$5, %eax, %xmm0

========

New:
_shuf1:
	pushl	%ebx
	pushl	%edi
	pushl	%esi
	pextrw	$1, %xmm0, %eax
	rolw	$8, %ax
	movd	%xmm0, %ecx
	rolw	$8, %cx
	pextrw	$5, %xmm0, %edx
	pextrw	$4, %xmm0, %esi
	pextrw	$3, %xmm0, %edi
	pextrw	$2, %xmm0, %ebx
	movaps	%xmm0, %xmm1
	pinsrw	$0, %ecx, %xmm1
	pinsrw	$1, %eax, %xmm1
	rolw	$8, %bx
	pinsrw	$2, %ebx, %xmm1
	rolw	$8, %di
	pinsrw	$3, %edi, %xmm1
	rolw	$8, %si
	pinsrw	$4, %esi, %xmm1
	rolw	$8, %dx
	pinsrw	$5, %edx, %xmm1
	pextrw	$7, %xmm0, %eax
	rolw	$8, %ax
	movaps	%xmm1, %xmm0
	pinsrw	$7, %eax, %xmm0
	popl	%esi
	popl	%edi
	popl	%ebx
	ret

Old:
_shuf1:
	subl	$252, %esp
	movaps	%xmm0, (%esp)
	movaps	%xmm0, 16(%esp)
	movaps	%xmm0, 32(%esp)
	movaps	%xmm0, 48(%esp)
	movaps	%xmm0, 64(%esp)
	movaps	%xmm0, 80(%esp)
	movaps	%xmm0, 96(%esp)
	movaps	%xmm0, 224(%esp)
	movaps	%xmm0, 208(%esp)
	movaps	%xmm0, 192(%esp)
	movaps	%xmm0, 176(%esp)
	movaps	%xmm0, 160(%esp)
	movaps	%xmm0, 144(%esp)
	movaps	%xmm0, 128(%esp)
	movaps	%xmm0, 112(%esp)
	movzbl	14(%esp), %eax
	movd	%eax, %xmm1
	movzbl	22(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	42(%esp), %eax
	movd	%eax, %xmm1
	movzbl	50(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm1, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	77(%esp), %eax
	movd	%eax, %xmm1
	movzbl	84(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm1, %xmm2
	movzbl	104(%esp), %eax
	movd	%eax, %xmm1
	punpcklbw	%xmm1, %xmm0
	punpcklbw	%xmm2, %xmm0
	movaps	%xmm0, %xmm1
	punpcklbw	%xmm3, %xmm1
	movzbl	127(%esp), %eax
	movd	%eax, %xmm0
	movzbl	135(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	155(%esp), %eax
	movd	%eax, %xmm0
	movzbl	163(%esp), %eax
	movd	%eax, %xmm3
	punpcklbw	%xmm0, %xmm3
	punpcklbw	%xmm2, %xmm3
	movzbl	188(%esp), %eax
	movd	%eax, %xmm0
	movzbl	197(%esp), %eax
	movd	%eax, %xmm2
	punpcklbw	%xmm0, %xmm2
	movzbl	217(%esp), %eax
	movd	%eax, %xmm4
	movzbl	225(%esp), %eax
	movd	%eax, %xmm0
	punpcklbw	%xmm4, %xmm0
	punpcklbw	%xmm2, %xmm0
	punpcklbw	%xmm3, %xmm0
	punpcklbw	%xmm1, %xmm0
	addl	$252, %esp
	ret

llvm-svn: 65311
 2009-02-23 08:49:38 +00:00
Scott Michel 9d31aca679 Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR 
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.

llvm-svn: 65296
 2009-02-22 23:36:09 +00:00
Evan Cheng e4ffc030e2 Be bug compatible with gcc by returning MMX values in RAX. 
llvm-svn: 65274
 2009-02-22 08:05:12 +00:00
Anton Korobeynikov 42aae86590 Drop bunch of half-working stuff in the ext_weak linkage support. 
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).

The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)

llvm-svn: 65230
 2009-02-21 11:53:32 +00:00
Evan Cheng 34806b1fa4 If two-address def is dead and the instruction does not define other registers, and it doesn't produce side effects, just delete the instruction. 
llvm-svn: 65218
 2009-02-21 03:14:25 +00:00
Evan Cheng 107b06c4b9 Teach LSR sink to sink the immediate portion of the common expression back into uses if they fit in address modes of all the uses. 
llvm-svn: 65215
 2009-02-21 02:06:47 +00:00
Evan Cheng 8a9481d50d Fix strange logic in CollectIVUsers used to determine whether all uses are 
addresses, part 1. This fixes an obvious logic bug. Previously if the only
in-loop use is a PHI, it would return AllUsesAreAddresses as true.

llvm-svn: 65178
 2009-02-20 22:16:49 +00:00
Evan Cheng 2a9bad5ac1 Support return of MMX values in 64-bit mode. 
llvm-svn: 65152
 2009-02-20 20:43:02 +00:00
Owen Anderson f13820148b Fix a crash in the pre-alloc splitter exposed by recent codegen changes. 
llvm-svn: 65121
 2009-02-20 10:02:23 +00:00
Chris Lattner 52e8d4cc5d make these tests pass when run on a G5. 
llvm-svn: 65117
 2009-02-20 07:10:11 +00:00