Commit Graph

313126 Commits

Author SHA1 Message Date
Matt Arsenault 4d47ac3b30 AMDGPU: Add additional MIR tests for exec mask optimizations
Also includes one example of how this transform is unsound. This isn't
verifying the copies are used in the control flow intrinisic patterns.

Also add option to disable exec mask opt pass. Since this pass is
unsound, it may be useful to turn it off until it is fixed.

llvm-svn: 357091
2019-03-27 16:58:30 +00:00
Matt Arsenault 4ab28b64b4 AMDGPU: Skip debug_instr when collapsing end_cf
Based on how these are inserted, I doubt this was causing a problem in
practice.

llvm-svn: 357090
2019-03-27 16:58:27 +00:00
Matt Arsenault a42b7247d3 AMDGPU: Fix missing scc implicit def on s_andn2_b64_term
Introduce new helper class to copy properties directly from the base
instruction.

llvm-svn: 357089
2019-03-27 16:58:22 +00:00
Mikhail R. Gadelha f5f8d27d39 New methods to check for under-/overflow in the SMT API
Summary: Added methods to check for under-/overflow in additions, subtractions, signed divisions/modulus, negations, and multiplications.

Reviewers: ddcc, gou4shi1

Reviewed By: ddcc, gou4shi1

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59796

llvm-svn: 357088
2019-03-27 16:54:12 +00:00
Matt Arsenault b19361243b PEI: Delay checking requiresFrameIndexReplacementScavenging
Currently this is called before the frame size is set on the
function. For AMDGPU, the scavenger is used for large frames where
part of the offset needs to be materialized in a register, so
estimating the frame size is useful for knowing whether the scavenger
is useful.

llvm-svn: 357087
2019-03-27 16:37:31 +00:00
Jonas Devlieghere f8819bd510 [Platform] Remove Kalimba Platform
This patch removes the Kalimba platform. For more information please
refer to the corresponding thread on the mailing list.

http://lists.llvm.org/pipermail/lldb-dev/2019-March/014921.html

llvm-svn: 357086
2019-03-27 16:23:50 +00:00
Andrea Di Biagio a194656fa2 [MCA] Fix -Wparentheses warning breaking the -Werror build.
Waring was introduced at r357074.

llvm-svn: 357085
2019-03-27 16:22:36 +00:00
Matt Arsenault 28f97f1dbc AMDGPU: Don't hardcode num defs for MUBUF instructions
This shouldn't change anything since the no-ret atomics are selected
later.

llvm-svn: 357084
2019-03-27 16:12:29 +00:00
Matt Arsenault 733b8571b4 MIR: Freeze reserved regs after parsing everything
The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.

Some tests were relying on the default reserved set for the assumed
default calling convention.

llvm-svn: 357083
2019-03-27 16:12:26 +00:00
Haojian Wu 566fba03de [clangd] Bump vscode-clangd v0.0.12.
CHANGELOG:
- add an explicit command to activate the extension.
- support .cu files (the extension is not activated for .cu files by default,
  you need to manually activate the extension).

llvm-svn: 357082
2019-03-27 16:01:25 +00:00
Matt Arsenault e9ad7e9a71 AMDGPU: wave_barrier is not isBarrier
This is not a control flow instruction, so should not be marked as
isBarrier. This fixes a verifier error if followed by unreachable.

llvm-svn: 357081
2019-03-27 15:54:45 +00:00
Pavel Labath 9f1a7e559c Rename some variables in the std-module tests
They cause failures on some systems due to an unrelated bug (pr35043).
This works around that.

llvm-svn: 357080
2019-03-27 15:52:11 +00:00
Louis Dionne daf43ed800 [libc++] Add proper XFAILs for shared_mutex tests
Dylib support for shared_mutex was added in macOS 10.12, so the tests
should be XFAILed accordingly instead of being completely disabled
whenever availability is enabled.

rdar://problem/48769104

llvm-svn: 357079
2019-03-27 15:50:34 +00:00
Haojian Wu 55beb2f549 [clangd] Fix the inconsistent code indent in vscode extension, NFC.
llvm-svn: 357078
2019-03-27 15:50:33 +00:00
Yonghong Song 6c56edfe42 [BPF] use std::map to ensure consistent output
The .BTF.ext FuncInfoTable and LineInfoTable contain
information organized per ELF section. Current definition
of FuncInfoTable/LineInfoTable is:
  std::unordered_map<uint32_t, std::vector<BTFFuncInfo>> FuncInfoTable
  std::unordered_map<uint32_t, std::vector<BTFLineInfo>> LineInfoTable
where the key is the section name off in the string table.
The unordered_map may cause the order of section output
different for different platforms.

The same for unordered map definition of
  std::unordered_map<std::string, std::unique_ptr<BTFKindDataSec>>
    DataSecEntries
where BTF_KIND_DATASEC entries may have different ordering
for different platforms.

This patch fixed the issue by using std::map.
Test static-var-derived-type.ll is modified to generate two
DataSec's which will ensure the ordering is the same for all
supported platforms.

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 357077
2019-03-27 15:45:27 +00:00
Clement Courbet 678d128b5a [X86MacroFusion][NFC] Improve macrofusion testing.
Add negative tests.
Add arithmetic/inc/cmp/and macrofusion tests.

llvm-svn: 357076
2019-03-27 15:43:03 +00:00
Haojian Wu d44e201376 [clangd] Add activate command to the vscode extension.
Summary:
This would help minizime the annoying part of not activating the extension
for .cu file.

Reviewers: ilya-biryukov

Subscribers: ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D59817

llvm-svn: 357075
2019-03-27 15:41:59 +00:00
Andrea Di Biagio 333a3264f4 [MCA][Pipeline] Don't visit stages in reverse order when calling method cycleEnd(). NFCI
There is no reason why stages should be visited in reverse order.
This patch allows the definition of stages that push instructions forward from
their cycleEnd() routine.

llvm-svn: 357074
2019-03-27 15:41:53 +00:00
Matt Arsenault bbc59d8d0d AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics
The offset operand index is different for atomics.

llvm-svn: 357073
2019-03-27 15:41:00 +00:00
Andrew Ng e6b6ab2c66 [LLD] Restore tests that use "-" as output
No longer require workarounds for output to "-" (stdout) for
Windows. These workarounds were just hiding the actual problem which has
been fixed in r357058.

Differential Revision: https://reviews.llvm.org/D59824

llvm-svn: 357072
2019-03-27 15:30:52 +00:00
Nico Weber 88efba8170 gn build: Merge r357047
llvm-svn: 357071
2019-03-27 15:10:47 +00:00
Nirav Dave b5630a2ab1 [DAGCombiner] Unify Lifetime and memory Op aliasing.
Rework BaseIndexOffset and isAlias to fully work with lifetime nodes
and fold in lifetime alias analysis.

This is mostly NFC.

Reviewers: courbet

Reviewed By: courbet

Subscribers: hiraditya, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59794

llvm-svn: 357070
2019-03-27 14:14:46 +00:00
Nirav Dave 96a264e053 [DAGCombine] Refactor GatherAllAliases. NFCI.
llvm-svn: 357069
2019-03-27 14:14:35 +00:00
Alexey Bataev e04483ee35 [OPENMP]Initial support for 'allocate' clause.
Added parsing/sema analysis of the allocate clause.

llvm-svn: 357068
2019-03-27 14:14:31 +00:00
Hans Wennborg 5c0d7a24e8 Re-commit r355490 "[CodeGen] Omit range checks from jump tables when lowering switches with unreachable default"
Original commit by Ayonam Ray.

This commit adds a regression test for the issue discovered in the
previous commit: that the range check for the jump table can only be
omitted if the fall-through destination of the jump table is
unreachable, which isn't necessarily true just because the default of
the switch is unreachable.

This addresses the missing optimization in PR41242.

> During the lowering of a switch that would result in the generation of a
> jump table, a range check is performed before indexing into the jump
> table, for the switch value being outside the jump table range and a
> conditional branch is inserted to jump to the default block. In case the
> default block is unreachable, this conditional jump can be omitted. This
> patch implements omitting this conditional branch for unreachable
> defaults.
>
> Differential Revision: https://reviews.llvm.org/D52002
> Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev

llvm-svn: 357067
2019-03-27 14:10:11 +00:00
Dmitry Preobrazhensky 40f0162a9a Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes
Reason: the change was mistakenly committed before review
llvm-svn: 357066
2019-03-27 13:49:52 +00:00
Kevin P. Neal 4f3cdc6555 The IR verifier currently supports the constrained floating point intrinsics,
but the implementation is hard to extend. It doesn't currently have an
easy way to support intrinsics that, for example, lack a rounding mode.
This will be needed for impending new constrained intrinsics.

This code is split out of D55897 <https://reviews.llvm.org/D55897>, which
itself was split out of D43515 <https://reviews.llvm.org/D43515>.

Reviewed by:	arsenm
Differential Revision:	http://reviews.llvm.org/D59830

llvm-svn: 357065
2019-03-27 13:30:57 +00:00
Sander de Smalen 90d1b551e1 [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal
Cleanup isAArch64FrameOffsetLegal by:
- Merging the large switch statement to reuse AArch64InstrInfo::getMemOpInfo().
- Using AArch64InstrInfo::getUnscaledLdSt() to determine whether an instruction
  has an unscaled variant.
- Simplifying the logic that calculates the offset to fit the immediate.

Reviewers: paquette, evandro, eli.friedman, efriedma

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D59636

llvm-svn: 357064
2019-03-27 13:16:19 +00:00
Dmitry Preobrazhensky bcc4d53835 [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes
See bug 40917: https://bugs.llvm.org/show_bug.cgi?id=40917

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D59305

llvm-svn: 357063
2019-03-27 13:07:41 +00:00
Simon Pilgrim d6f9baf74f [X86][SSE] Add shuffle test case for PR41249
llvm-svn: 357062
2019-03-27 11:21:09 +00:00
George Rimar 36d71da694 Revert the r348352 "[clang] - Simplify tools::SplitDebugName."
This partially reverts the r348352 (https://reviews.llvm.org/D55006)
because of https://bugs.llvm.org/show_bug.cgi?id=41161.

I did not revert the test case file because it passes fine now.

llvm-svn: 357061
2019-03-27 11:00:03 +00:00
Pavel Labath ee7ceacaca minidump: Add ability to attach (breakpad) symbol files to placeholder modules
This re-commits r354263, which was because it uncovered with handling of
modules with empty (zero) UUIDs. This would cause us to treat two
modules as intentical even though they were not. This caused an assert
in PlaceholderObjectFile::SetLoadAddress to fire, because we were trying
to load the module twice even though it was designed to be only loaded
at a specific address. (The same problem also existed with the previous
implementation, but it had no asserts to warn us about this.) These
issues have now been fixed in r356896.

windows bot. The issue there was that ObjectFilePECOFF vended its base
address through the incorrect interface. SymbolFilePDB depended on that,
which lead to assertion failures when SymbolFilePDB was attempting to
use the placeholder object files as a base. This has been fixed in
r354258

The original commit message was:

The reason this wasn't working was that ProcessMinidump was creating odd
object-file-less modules, and SymbolFileBreakpad required the module to
have an associated object file because it needed to get its base
address.

This fixes that by introducing a PlaceholderObjectFile to serve as a
dummy object file. The general idea for this is taken from D55142, but
I've reworked it a bit to avoid the need for the PlaceholderModule
class. Now that we have an object file, our modules are sufficiently
similar to regular modules that we can use the regular Module class
almost out of the box -- the only thing I needed to tweak was the
Module::CreateModuleFromObjectFile functon to set the module's FileSpec
in addition to it's architecture. This wasn't needed for ObjectFileJIT
(the other user of CreateModuleFromObjectFile), but it shouldn't hurt it
either, and the change seems like a straightforward extension of this
function.

Reviewers: clayborg, lemo, amccarth

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D57751

llvm-svn: 357060
2019-03-27 10:54:10 +00:00
Sander de Smalen 46edefe3c4 [AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfo
This patch also adds cases PRFUMi and PRFMui.
This change was discussed in https://reviews.llvm.org/D59635.

llvm-svn: 357059
2019-03-27 10:39:03 +00:00
Andrew Ng 2fc69abf5b [Support] MemoryBlock size should reflect the requested size
This patch mirrors the change made to the Unix equivalent in
r351916. This in turn fixes bugs related to the use of FileOutputBuffer
to output to "-", i.e. stdout, on Windows.

Differential Revision: https://reviews.llvm.org/D59663

llvm-svn: 357058
2019-03-27 10:26:21 +00:00
Simon Pilgrim ccb71b2985 Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure.

This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.
........
Causes PR41249

llvm-svn: 357057
2019-03-27 10:25:02 +00:00
Pavel Labath ab0f18076b Fix a "memset clearing an object of non-trivial type" warning in DWARFFormValue
This is diagnosed by gcc-8. The ValueType struct already has a default
constructor which performs zero-initialization, so we can just call that
instead of using memset.

llvm-svn: 357056
2019-03-27 10:02:36 +00:00
Pavel Labath cf6c19c2d3 Fix an out-of-bounds error in RegisterContextDarwin_arm64
Summary:
gcc diagnoses this as "array subscript 63 is above array bounds of
'RegisterContextDarwin_arm64::VReg [32]'".

The correct fix seems to be subtracting the fpu register base index, but
I have no way of verifying that this actually works.

Reviewers: jasonmolenda

Subscribers: javed.absar, kristof.beyls, lldb-commits

Differential Revision: https://reviews.llvm.org/D59495

llvm-svn: 357055
2019-03-27 09:39:46 +00:00
Fangrui Song 3f2e29b013 [DWARF] Add D to Seen early to avoid duplicate elements in Worklist
llvm-svn: 357054
2019-03-27 09:38:05 +00:00
Fangrui Song 38a4c619eb [DWARF] Simplify DWARFVerifier::handleDebugAbbrev. NFC
llvm-svn: 357053
2019-03-27 08:43:21 +00:00
Jonas Paulsson 38342a5185 [DAGCombiner] Don't allow addcarry if the carry producer is illegal.
getAsCarry() checks that the input argument is a carry-producing node before
allowing a transformation to addcarry. This patch adds a check to make sure
that the carry-producing node is legal. If it is not, it may not remain in a
form that is manageable by the target backend. The test case caused a
compilation failure during instruction selection for this reason on SystemZ.

Patch by Ulrich Weigand.

Review: Sanjay Patel
https://reviews.llvm.org/D59822

llvm-svn: 357052
2019-03-27 08:41:46 +00:00
Fangrui Song 95db95729c [llvm-dwarfdump] Simplify -o handling
ToolOutputFile handles '-' so no need to specialize here.
Also, we neither reassign the variable nor pass it around, thus no need
to use std::unique_ptr<ToolOutputFile>.

exit(1) -> return 1;  to call the destructor of raw_fd_stream

llvm-svn: 357051
2019-03-27 08:19:36 +00:00
Craig Topper feadc2a1de [X86] Add test cases for missed opportunities in (x << C1) op C2 to (x op (C2>>C1)) << C1 transform.
We handle the case where the C2 does not fit in a signed 32-bit immediate, but
(C2>>C1) does. But there's also some 64-bit opportunities when C2 is not an unsigned
32-bit immediate, but (C2>>C1) is. For OR/XOR this allows us to load the
immediate with with MOV32ri instead of a movabsq. For AND it allows us to use a
32-bit AND and fold the immediate.

llvm-svn: 357050
2019-03-27 06:07:05 +00:00
Craig Topper 7da7b97487 [X86] When iselling (x << C1) and/or/xor C2 as (x and/or/xor (C2>>C1)) << C1, go through the isel table instead of manually selecting.
Previously we manually selected the AND/OR/XOR with immediate and the SHL(or ADD if the shift is 1). But this was missing out on the opportunity to use a 64 bit AND with a 32-bit immediate and possibly other isel tricks we have built into the tables.

Instead, insert the new nodes into the DAG using insertDAGNode and allow them each to be selected through the normal table.

llvm-svn: 357049
2019-03-27 04:45:58 +00:00
Yi Kong e204d244ba Revert "[builtins] Rounding mode support for addxf3/subxf3"
This reverts commit 2cabea054e.

Test failure on buildbots.

llvm-svn: 357048
2019-03-27 04:18:37 +00:00
QingShan Zhang 5321dcd608 [NFC][PowerPC] Custom PowerPC specific machine-scheduler
This patch lays the groundwork for extending the generic machine scheduler by providing a PPC-specific implementation.
There are no functional changes as this is an incremental patch that simply provides the necessary overrides which just
encapsulate the behavior of the generic scheduler. Subsequent patches will add specific behavior.

Differential Revision: https://reviews.llvm.org/D59284

llvm-svn: 357047
2019-03-27 03:50:16 +00:00
Craig Topper 06cdd7e488 [X86] Autogenerate complete checks. NFC
llvm-svn: 357046
2019-03-27 02:18:41 +00:00
Craig Topper 22387a56fe [X86] Simplify some code in matchBitExtract by using ANY_EXTEND.
We were manually outputting the code we would get from selecting ANY_EXTEND. We
can save some code by just letting an ANY_EXTEND go through isel on its own.

llvm-svn: 357045
2019-03-27 02:08:03 +00:00
Nathan Lanza d0050d1b8b Get the lang from the CompileUnit for ParseCompileUnitFunctionForPDBFunc
Summary:
Instead of assuming that the language is C++ instead check the compunit
for the language it received from the debug info.

Subscribers: aprantl, jdoerfert

Differential Revision: https://reviews.llvm.org/D59805

llvm-svn: 357044
2019-03-27 01:24:03 +00:00
Francis Visoiu Mistrih ee1a6e70fa [Remarks] Emit a section containing remark diagnostics metadata
A section containing metadata on remark diagnostics will be emitted if
the flag (-mllvm) -remarks-section is present.

For now, the metadata is:

* a magic number for remarks: "REMARKS\0"
* the version number: a little-endian uint64_t
* the absolute file path to the serialized remark diagnostics: a
  null-terminated string.

Differential Revision: https://reviews.llvm.org/D59571

llvm-svn: 357043
2019-03-27 01:13:59 +00:00
Nico Weber 8b106be2c7 gn build: Add build files for clang-include-fixer and find-all-symbols
Differential Revision: https://reviews.llvm.org/D59838

llvm-svn: 357042
2019-03-27 00:17:05 +00:00