f2d589fe24
Remove a completed optimization. Add a potential optimization I ran
...
into.
llvm-svn: 71352
2009-05-09 08:40:15 +00:00
af9eaa830a
Rename PaddedSize to AllocSize, in the hope that this
...
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
llvm-svn: 71349
2009-05-09 07:06:46 +00:00
3033816c80
Use 16 bit arithmetic while retrieving the address of callee's frame during indirect function calls, and set pclath before every call to retrieve the frame address.
...
llvm-svn: 71323
2009-05-09 05:11:19 +00:00
8f43afd3bb
PPC::B and PPC::BCC's target operand may be an immediate.
...
llvm-svn: 71282
2009-05-08 23:09:25 +00:00
65a58168cc
Factor out cycle-finder code and make it generic.
...
llvm-svn: 71241
2009-05-08 18:51:58 +00:00
ea618dd0ba
Allow 8 bit select in custom inserter
...
llvm-svn: 71239
2009-05-08 18:51:21 +00:00
1484cfe945
Expand UREM / SREM into libcalls
...
llvm-svn: 71236
2009-05-08 18:50:41 +00:00
c3e1b392ae
Add 8 bit select
...
llvm-svn: 71235
2009-05-08 18:50:26 +00:00
f1d9b91434
Fix PR4152: asm constraint validation happens before dag combine, so we
...
need to work a bit to combine things like (x+c1+c2) into x+c3.
llvm-svn: 71232
2009-05-08 18:23:14 +00:00
2fa281106a
Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
...
/// A:
/// ...
/// <fallthrough to B>
///
/// B: --> loop header
/// ...
/// jcc <cond> C, [exit]
///
/// C:
/// ...
/// jmp B
///
/// ==>
///
/// A:
/// ...
/// jmp B
///
/// C: --> new loop header
/// ...
/// <fallthough to B>
///
/// B:
/// ...
/// jcc <cond> C, [exit]
llvm-svn: 71209
2009-05-08 06:34:09 +00:00
2f6bddd2b1
Add missing #include for "strlen" which is used inline in this header. Fixes
...
build under gcc 4.3.
llvm-svn: 71208
2009-05-08 06:22:25 +00:00
89e72b9c4a
Moved pic16 naming functions to correct place.
...
No functionality change.
llvm-svn: 71207
2009-05-08 04:50:14 +00:00
a55d46100e
Eliminate compiler warnings.
...
llvm-svn: 71149
2009-05-07 05:31:56 +00:00
364f3efa53
CMake: Updated lib/Target/PIC16/CMakeLists.txt.
...
llvm-svn: 71115
2009-05-06 20:40:05 +00:00
72b6582c0f
Use X86AddrNumOperands instead of magic constant one
...
more place. This fixes a bunch of x86-64 JIT regressions.
(Introduced when the value of the magic constant changed
in 68645. At the time apparently nobody noticed; failures
were hidden in 70343-70439 by an unrelated bug, so showed
up again as "new" failures in 70440.)
llvm-svn: 71106
2009-05-06 19:04:30 +00:00
960ae0660b
Emit banksel and movlp instructions.
...
Split large global data (both initialized and un-initialized) into multiple sections of <= 80 bytes.
Provide routines to manage PIC16 ABI naming conventions.
llvm-svn: 71073
2009-05-06 08:02:01 +00:00
be9fa506ad
Add basic support for code generation of
...
addrspace(257) -> FS relative on x86. Patch by Zoltan Varga!
llvm-svn: 70992
2009-05-05 18:52:19 +00:00
a35aed567a
Revert part of 70929 that has to do with determining whether a SIB byte is needed. It causes a lot of x86_64 JIT failures.
...
llvm-svn: 70986
2009-05-05 18:18:57 +00:00
1ff2727c95
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
...
llvm-svn: 70950
2009-05-05 00:30:09 +00:00
c298ccb998
- Avoid the longer SIB encoding on x86_64 when it's not needed.
...
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.
llvm-svn: 70929
2009-05-04 22:49:16 +00:00
bb525f7e02
X86FastISel doesn't support the -tailcallopt ABI.
...
llvm-svn: 70902
2009-05-04 19:50:33 +00:00
2d1e7321f6
Fix code emission for conditional branches.
...
Patch by Collin Winter!
llvm-svn: 70898
2009-05-04 19:10:38 +00:00
630f4e1eb3
Trim unnecessary #includes.
...
llvm-svn: 70880
2009-05-04 17:11:06 +00:00
4ff60e0cc2
Handle implicit zext in a better way. Shamelessly stolen from x86 backend.
...
Thanks for Dan Gohman for suggestion!
llvm-svn: 70782
2009-05-03 15:50:18 +00:00
1324f810d7
Update due to mainline API change
...
llvm-svn: 70769
2009-05-03 13:19:42 +00:00
d089ef1003
Add TODO list :)
...
llvm-svn: 70768
2009-05-03 13:19:24 +00:00
47fcd72e24
Make handling of conditional stuff much more straightforward
...
llvm-svn: 70767
2009-05-03 13:19:09 +00:00
dedfa00ba1
Temporary disable imm patterns for cmp. Actually, all cmp-related stuff (select_cc, setcc, br_cc). needs to be rethought
...
llvm-svn: 70766
2009-05-03 13:18:50 +00:00
eb2152f753
Expand divisions into libcalls
...
llvm-svn: 70765
2009-05-03 13:18:33 +00:00
29747e9c26
Custom lower SIGN_EXTEND
...
llvm-svn: 70763
2009-05-03 13:17:49 +00:00
3c48ea7dbe
Some eye-candy
...
llvm-svn: 70762
2009-05-03 13:17:31 +00:00
48e21c57f1
Print function header / footer
...
llvm-svn: 70761
2009-05-03 13:17:11 +00:00
8847e3e554
Fix printing: je => jeq
...
llvm-svn: 70760
2009-05-03 13:16:54 +00:00
f3a6bc8562
Add 8bit shifts
...
llvm-svn: 70759
2009-05-03 13:16:37 +00:00
61763b532a
Handle logical shift right (at least I hope so :) )
...
llvm-svn: 70758
2009-05-03 13:16:17 +00:00
20a91130ce
Handle anyext
...
llvm-svn: 70757
2009-05-03 13:15:57 +00:00
e31559576f
Expand all sorts of indirect branches
...
llvm-svn: 70755
2009-05-03 13:15:40 +00:00
41917df643
Add InsertBranch() hook for tail mergeing
...
llvm-svn: 70754
2009-05-03 13:15:22 +00:00
4b0a0f18fb
Implement bswap
...
llvm-svn: 70753
2009-05-03 13:15:03 +00:00
ba0e81d4b2
Properly handle ExternalSymbol's
...
llvm-svn: 70752
2009-05-03 13:14:46 +00:00
de60d1caef
Expand muls (all mulls!) to libcalls for now
...
llvm-svn: 70751
2009-05-03 13:14:25 +00:00
0da755ee3e
Provide addc and subc
...
llvm-svn: 70748
2009-05-03 13:13:34 +00:00
a3f7a83ad8
Add left shift
...
llvm-svn: 70747
2009-05-03 13:13:17 +00:00
aa43d0b182
Add direct branch
...
llvm-svn: 70746
2009-05-03 13:12:58 +00:00
24bfb51416
It's error-prone to maintain two separate variants of asmprinting stuff, one of which is even used. Drop second (aka 'intel') variant of operands. It can be added later, if needed.
...
llvm-svn: 70745
2009-05-03 13:12:37 +00:00
b6321e15f7
Lower select with custom inserted and make condjumps generic
...
llvm-svn: 70744
2009-05-03 13:12:23 +00:00
962720129d
Add first draft for conditions, conditional branches, etc
...
llvm-svn: 70743
2009-05-03 13:12:06 +00:00
aa51bff808
Hanle i8 returns
...
llvm-svn: 70742
2009-05-03 13:11:48 +00:00
7212c15e70
Small tweaking
...
llvm-svn: 70741
2009-05-03 13:11:35 +00:00
f2b50994ca
Add prologue/epilogue emission. Fix frame pointer handling.
...
llvm-svn: 70740
2009-05-03 13:11:20 +00:00
1af0b61e7c
Add code for save/restore of callee-saved registers
...
llvm-svn: 70739
2009-05-03 13:11:04 +00:00
b85f4ec819
Two more hooks for RA and FP registers
...
llvm-svn: 70738
2009-05-03 13:10:40 +00:00
7784ae9a6f
Proper handle loading of effective address of stack slot stuff
...
llvm-svn: 70737
2009-05-03 13:10:26 +00:00
0d1234fd69
Match frame indexes
...
llvm-svn: 70736
2009-05-03 13:10:11 +00:00
f6af822c76
First draft of stack slot loads / stores lowering
...
llvm-svn: 70735
2009-05-03 13:09:57 +00:00
ed65671768
Reverse order of memory arguments
...
llvm-svn: 70734
2009-05-03 13:09:40 +00:00
04888305f6
Remove bogus pattern
...
llvm-svn: 70733
2009-05-03 13:09:24 +00:00
6399a3d628
Correct asmprinting of memory operands
...
llvm-svn: 70732
2009-05-03 13:09:10 +00:00
a3bce28ae0
Match wrapper node for address
...
llvm-svn: 70731
2009-05-03 13:08:51 +00:00
cfc97056e7
Add lowering for global address nodes. Not pretty efficient though.
...
llvm-svn: 70730
2009-05-03 13:08:33 +00:00
b5613928f5
Some early full call lowering draft for direct calls
...
llvm-svn: 70729
2009-05-03 13:08:13 +00:00
ec3f0b3f9d
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
...
llvm-svn: 70728
2009-05-03 13:07:54 +00:00
5613510c81
Add CALL lowering.
...
llvm-svn: 70727
2009-05-03 13:07:31 +00:00
c995ddd017
Add bunch of mem-whatever patterns
...
llvm-svn: 70726
2009-05-03 13:07:10 +00:00
f702a0085c
Add bunch of reg-mem inst patterns
...
llvm-svn: 70725
2009-05-03 13:06:46 +00:00
ed1c3dfa0f
Add normal and trunc stores
...
llvm-svn: 70724
2009-05-03 13:06:26 +00:00
31ecd23a9e
Basic support for mem=>reg moves
...
llvm-svn: 70723
2009-05-03 13:06:03 +00:00
80a73e7d8b
Add 8-bit insts. zext behaviour is not modelled yet
...
llvm-svn: 70722
2009-05-03 13:05:42 +00:00
b900245e13
Add 8-bit regclass and pattern for sext_inreg
...
llvm-svn: 70721
2009-05-03 13:05:22 +00:00
b638fb10f5
Add pattern for OR
...
llvm-svn: 70720
2009-05-03 13:05:00 +00:00
654cb0a761
Add reg-imm variants
...
llvm-svn: 70719
2009-05-03 13:04:41 +00:00
37709c3584
Add hint to nop
...
llvm-svn: 70718
2009-05-03 13:04:23 +00:00
6339db830e
Add more instructions
...
llvm-svn: 70717
2009-05-03 13:04:06 +00:00
e32c817d2c
Cleanup
...
llvm-svn: 70716
2009-05-03 13:03:50 +00:00
15a515b1af
Add dummy lowering for shifts
...
llvm-svn: 70715
2009-05-03 13:03:33 +00:00
55a085b539
We don't have any div at all - thus mark it as expensive
...
llvm-svn: 70714
2009-05-03 13:03:14 +00:00
abb51755c8
We're not going to spend 100% of time in interrupts, do we? :)
...
llvm-svn: 70713
2009-05-03 13:02:57 +00:00
8a17dff7d0
Add simple reg-reg add.
...
llvm-svn: 70712
2009-05-03 13:02:39 +00:00
6ff6fc95a0
gas uses lower letter for register names
...
llvm-svn: 70711
2009-05-03 13:02:22 +00:00
d7afd69e3b
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
...
llvm-svn: 70710
2009-05-03 13:02:04 +00:00
c942782b3b
Add function body printing routine
...
llvm-svn: 70709
2009-05-03 13:01:41 +00:00
ef811d8e05
Add 'msp430' target triple recognizer
...
llvm-svn: 70708
2009-05-03 13:01:23 +00:00
a9b7df98e6
Make emit{Prologue,Epilogue}() noop for now
...
llvm-svn: 70707
2009-05-03 13:01:04 +00:00
69f51f0b41
Add callee-saved regs & reg classes getter hooks
...
llvm-svn: 70706
2009-05-03 13:00:46 +00:00
efcd5aa381
Add simple FP indicator for given function hook
...
llvm-svn: 70705
2009-05-03 13:00:28 +00:00
c10f98ace3
Provide set of reserved registers
...
llvm-svn: 70704
2009-05-03 13:00:11 +00:00
7bfc3ea2ee
Add proper ISD::RET lowering
...
llvm-svn: 70703
2009-05-03 12:59:50 +00:00
3849be6ca1
Add first draft of MSP430 calling convention stuff and draft of ISD::FORMAL_ARGUMENTS node lowering.
...
llvm-svn: 70702
2009-05-03 12:59:33 +00:00
77e5a11ec2
Fix register names, fix register allocation order, handle frame pointer.
...
llvm-svn: 70701
2009-05-03 12:59:16 +00:00
64717bbc14
Clearify the usage and add some debug stuff
...
llvm-svn: 70700
2009-05-03 12:58:58 +00:00
e10f69a8a7
Cleanup
...
llvm-svn: 70699
2009-05-03 12:58:40 +00:00
128e8a188f
Add cmake script. No idea whether it works or not :)
...
llvm-svn: 70698
2009-05-03 12:58:22 +00:00
4130a7c1e7
Add a note
...
llvm-svn: 70697
2009-05-03 12:58:05 +00:00
7c4db99df3
Typo
...
llvm-svn: 70695
2009-05-03 12:57:47 +00:00
101380015c
Dummy MSP430 backend
...
llvm-svn: 70694
2009-05-03 12:57:15 +00:00
e01821edbd
'The attached patch fixes an issue where llc -march=cpp fails with
...
"Invalid primitive type" on input containing the x86_fp80 type.'
Patch by Collin Winter!
llvm-svn: 70610
2009-05-01 23:54:26 +00:00
31af617924
Fix compilation for some targets other than x86.
...
llvm-svn: 70522
2009-04-30 23:50:26 +00:00
a5037484a4
Make DebugLoc independent of DwarfWriter.
...
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)
llvm-svn: 70520
2009-04-30 23:22:31 +00:00
e651f25a7b
getCommonSubClass() - Calculate the largest common sub-class of two register
...
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
llvm-svn: 70512
2009-04-30 21:23:32 +00:00
db3a57ec5c
Set mayLoad on MOVZX32_NOREXrm8 too.
...
llvm-svn: 70466
2009-04-30 03:11:48 +00:00
99578674fd
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
...
llvm-svn: 70461
2009-04-30 00:58:57 +00:00
1fba01bbcd
remove progname which is never set. PR4085
...
llvm-svn: 70453
2009-04-30 00:24:33 +00:00
026e5d7667
Instead of passing in an unsigned value for the optimization level, use an enum,
...
which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
7e6e352735
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
...
llvm-svn: 70425
2009-04-29 22:47:44 +00:00
5f829d896d
Implement review feedback for vector shuffle work.
...
llvm-svn: 70372
2009-04-29 05:20:52 +00:00
ccd30945f9
Add a public method called getAddressSpace() to the GlobalAddressSDNode.
...
llvm-svn: 70366
2009-04-29 04:43:24 +00:00
084669a1c9
Second attempt:
...
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
dac88bae4f
Properly print 'P' modifier on inline asm memory operands.
...
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!
llvm-svn: 70328
2009-04-28 21:49:33 +00:00
7bfed8a9f4
GlobalValue is always pointer type, so an assert isn't required.
...
llvm-svn: 70300
2009-04-28 16:39:45 +00:00
56f2987a87
r70270 isn't ready yet. Back this out. Sorry for the noise.
...
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
d0ae15946c
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
...
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
llvm-svn: 70270
2009-04-28 00:21:31 +00:00
8d6d4b9289
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
...
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
llvm-svn: 70225
2009-04-27 18:41:29 +00:00
2986972118
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
...
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
llvm-svn: 70211
2009-04-27 16:41:36 +00:00
ec542ca65e
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
...
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
llvm-svn: 70210
2009-04-27 16:33:14 +00:00
ba99bddf1f
Break up long multi-mnemonic strings into separate lines for readability.
...
llvm-svn: 70209
2009-04-27 15:13:28 +00:00
e15bf109be
Revised 68749 to allow matching of load/stores for address spaces < 256.
...
llvm-svn: 70197
2009-04-27 07:22:10 +00:00
3ad60b18cb
add support for detecting process features on win64, patch by
...
Nicolas Capens!
llvm-svn: 70057
2009-04-25 18:27:23 +00:00
0041bd3523
Change LowerCallResult method so that CCValAssign::BCvt can be used with
...
f64 types. This is not used for anything yet.
llvm-svn: 70006
2009-04-25 00:33:20 +00:00
40e784ce69
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
...
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
llvm-svn: 69978
2009-04-24 17:05:01 +00:00
f134b2d212
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
...
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
llvm-svn: 69977
2009-04-24 17:00:36 +00:00
62d47d2361
Remove unnecessary references to f32 types. After specifying that f32
...
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
llvm-svn: 69973
2009-04-24 16:55:25 +00:00
c1396a2313
Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
...
very elegant, but neither is the tls specification :-(
llvm-svn: 69968
2009-04-24 12:59:40 +00:00
b93db668b3
Revert 69952. Causes testsuite failures on linux x86-64.
...
llvm-svn: 69967
2009-04-24 12:40:33 +00:00
bb881d66f4
PR2957
...
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
2009-04-24 03:42:54 +00:00
870c33f14b
Fix spurious indentation in a comment.
...
llvm-svn: 69934
2009-04-23 22:41:05 +00:00
5058f240d9
Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand.
...
llvm-svn: 69883
2009-04-23 10:34:58 +00:00
14efb90fcf
Add support for printing MO_ExternalSymbol operands in
...
memory operand tuples. This doesn't ever come up in normal
code however.
llvm-svn: 69848
2009-04-23 00:57:37 +00:00
107b2818ce
Make the function begin label start after ther data pointer.
...
The address of data frame for function can be obtained by subtracting 2 from the function begin label.
llvm-svn: 69801
2009-04-22 12:02:36 +00:00
7ce5cc6bd1
Get rid of what looks like a copy-and-pasted typo.
...
Spotted by gcc-4.5.
llvm-svn: 69673
2009-04-21 09:44:39 +00:00
47ed1f5293
TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.
...
This fixes PR4002.
llvm-svn: 69672
2009-04-21 08:22:09 +00:00
3e3ef7c4d9
Handle direct aggregate type arguments.
...
llvm-svn: 69665
2009-04-21 05:54:51 +00:00
1addf64735
Make X86's copyRegToReg able to handle copies to and from subclasses.
...
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.
llvm-svn: 69635
2009-04-20 22:54:34 +00:00
2c441c6afe
Remove unused variable.
...
llvm-svn: 69624
2009-04-20 20:34:38 +00:00
f8b85477ae
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
...
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
2009-04-20 18:36:57 +00:00
958d5eb032
Match C backend only if it explicitly requested.
...
llvm-svn: 69613
2009-04-20 18:07:22 +00:00
0fcc019d36
Emit the auto variables of a function into a different section than parameters.
...
llvm-svn: 69605
2009-04-20 16:59:35 +00:00
6c8bcf9da1
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction
...
llvm-svn: 69417
2009-04-18 05:16:01 +00:00
06684350c4
Recommit r69335 and r69336. These were not causing problems.
...
llvm-svn: 69394
2009-04-17 22:40:38 +00:00
b0b10f8bf6
Move the AddLiveIn function definition closer to its uses.
...
llvm-svn: 69382
2009-04-17 20:42:34 +00:00
deeaf70dad
Rearrange code to reduce indentation.
...
llvm-svn: 69381
2009-04-17 20:40:45 +00:00
ea09d4aca8
Clean up formatting, remove trailing whitespace, fix comment typos and
...
punctuation. No functional changes.
llvm-svn: 69378
2009-04-17 20:35:10 +00:00
a4c2290e5f
Use CallConvLower.h and TableGen descriptions of the calling conventions
...
for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
355fe12c82
For general dynamic TLS access we must use
...
leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
llvm-svn: 69350
2009-04-17 14:35:58 +00:00
30527b1114
Revert r69335 and r69336. They were causing build failures.
...
llvm-svn: 69347
2009-04-17 04:19:22 +00:00
09dbb0b5e0
MOV8rr_NOREX is a "Move" instruction. This doesn't currently
...
matter, because this instruction isn't generated until after
things that care.
llvm-svn: 69336
2009-04-17 00:45:17 +00:00
74835ce1cb
Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
...
present, but it's inconsistent.
llvm-svn: 69335
2009-04-17 00:43:09 +00:00
a8919d0a35
Fix some failures in targets on available_externally functions,
...
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
llvm-svn: 69333
2009-04-17 00:26:12 +00:00
5e42177a0f
fix PR3995. A scale must be 1, 2, 4 or 8.
...
llvm-svn: 69284
2009-04-16 12:34:53 +00:00
de7b3e74be
Fix 80-column violations.
...
llvm-svn: 69204
2009-04-15 19:48:57 +00:00
6711216e84
Add a folding table entry for MOV8rr_NOREX.
...
llvm-svn: 69203
2009-04-15 19:48:28 +00:00
6f873b446a
Fix X86MachineFunctionInfo's doxygen comment.
...
llvm-svn: 69127
2009-04-15 01:20:18 +00:00
dd07f638f5
Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
...
the local register allocator.
llvm-svn: 69115
2009-04-15 00:10:16 +00:00
7913ea5e4a
Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it when
...
either the source or destination is a physical h register.
This fixes sqlite3 with the post-RA scheduler enabled.
llvm-svn: 69111
2009-04-15 00:04:23 +00:00
821e13a8f4
GR8_NOREX can contain the H registers, since they don't require
...
REX prefixes.
llvm-svn: 69108
2009-04-15 00:00:48 +00:00
62f4498646
For the h-register addressing-mode trick, use the correct value for
...
any non-address uses of the address value. This fixes 186.crafty.
llvm-svn: 69094
2009-04-14 22:45:05 +00:00
dfbbf5c043
Some of GR8_NOREX registers are only available in 64-bit mode.
...
llvm-svn: 69049
2009-04-14 16:57:43 +00:00
92bb846e2b
Handle aggregate type arguments to direct and indirect calls.
...
llvm-svn: 69022
2009-04-14 02:49:52 +00:00
6c1426308c
Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
...
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
llvm-svn: 68986
2009-04-13 21:06:25 +00:00
80be3511ed
Reapply 68847.
...
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.
llvm-svn: 68964
2009-04-13 17:02:03 +00:00
57d6bd36b2
Implement x86 h-register extract support.
...
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
2009-04-13 16:09:41 +00:00
f20462c217
Remove x86's special-case handling for ISD::TRUNCATE and
...
ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.
llvm-svn: 68959
2009-04-13 15:29:31 +00:00
e9432dcc0d
Fix copy+pastos in comments.
...
llvm-svn: 68958
2009-04-13 15:28:29 +00:00
9e3eb7bcd9
List the l registers before h registers, for consistency.
...
llvm-svn: 68954
2009-04-13 15:18:42 +00:00
092b8b6fdb
Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.
...
llvm-svn: 68951
2009-04-13 15:14:03 +00:00
c5c2fc45ae
Add a comment about MOVSX64rr8.
...
llvm-svn: 68950
2009-04-13 15:13:28 +00:00
39aa13a401
Fix another hard-coded constant to use X86AddrNumOperands.
...
This unbreaks the JIT on x86-64.
llvm-svn: 68948
2009-04-13 15:04:25 +00:00
6d6c6043ea
X86-64 TLS support for local exec and initial exec.
...
llvm-svn: 68947
2009-04-13 13:02:49 +00:00
0368bc4703
While passing arg of types larger than char only one byte at lower end was getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.
...
llvm-svn: 68946
2009-04-13 09:38:38 +00:00
184f1be4a8
Add a new "available_externally" linkage type. This is intended
...
to support C99 inline, GNU extern inline, etc. Related bugzilla's
include PR3517, PR3100, & PR2933. Nothing uses this yet, but it
appears to work.
llvm-svn: 68940
2009-04-13 05:44:34 +00:00
7186f20a1b
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
...
only if symbolic addresses are RIP relatives.
llvm-svn: 68924
2009-04-12 23:00:38 +00:00
6688b0a5da
refactor some code into X86DAGToDAGISel::MatchWrapper
...
llvm-svn: 68915
2009-04-12 21:55:03 +00:00
ce6bcf0847
fix a cross-block fastisel crash handling overflow intrinsics.
...
See comment for details. This fixes rdar://6772169
llvm-svn: 68890
2009-04-12 07:51:14 +00:00
99a8cb627d
simplify code by using IntrinsicInst.
...
llvm-svn: 68887
2009-04-12 07:36:01 +00:00
24ac95abc1
Add new TargetInstrDesc::hasImplicitUseOfPhysReg and
...
hasImplicitDefOfPhysReg methods. Use them to remove a
look in X86 fast isel.
llvm-svn: 68886
2009-04-12 07:26:51 +00:00
825236b116
Revert r68847. It breaks the build on non-Darwin targets, with this message
...
from the assembler:
Error: unknown pseudo-op: `.debug_inlined'
llvm-svn: 68863
2009-04-11 15:57:04 +00:00
790e60999e
Keep track of inlined functions and their locations. This information is collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.)
...
Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section.
llvm-svn: 68847
2009-04-11 00:16:47 +00:00
638f400a3c
Added code to handle spilling and reloading of FSRs.
...
llvm-svn: 68783
2009-04-10 15:10:14 +00:00
bb834f0929
Don't fold a load if the other operand is a TLS address.
...
With this we generate
movl %gs:0, %eax
leal i@NTPOFF(%eax), %eax
instead of
movl $i@NTPOFF, %eax
addl %gs:0, %eax
llvm-svn: 68778
2009-04-10 10:09:34 +00:00
428f71623b
a few fixes to "addrspace(256) is reference offset of GS segment register".
...
It turns out that there are still several problems with this, will file a bugzilla.
llvm-svn: 68749
2009-04-10 00:16:23 +00:00
992f846dc7
Pass in the std::string parameter instead of returning it by value.
...
llvm-svn: 68747
2009-04-10 00:12:49 +00:00
de912e2475
Remove the obsolete SelectionDAG::getNodeValueTypes and simplify
...
code that uses it by using SelectionDAG::getVTList instead.
llvm-svn: 68744
2009-04-09 23:54:40 +00:00
5eb8d26f19
Give register alias checking the hash table treatment too.
...
llvm-svn: 68730
2009-04-09 22:19:30 +00:00
51856173c8
Fix pr3954. The register scavenger asserts for inline assembly with
...
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
2009-04-09 17:16:43 +00:00
38533d48dd
The way we are trying to figure out banksel immediate operand may yield different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand.
...
llvm-svn: 68713
2009-04-09 17:06:24 +00:00
60fd2cd503
Arguments to indirect calls were being passed incorrectly. They are not fixed to start after return value.
...
llvm-svn: 68705
2009-04-09 10:29:32 +00:00
bcd2632638
Fix code size computation on x86-64, patch by Zoltan Varga!
...
llvm-svn: 68690
2009-04-09 06:10:51 +00:00
cdfdc79b70
r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were custom lowering an ADD to ADDC.
...
llvm-svn: 68671
2009-04-09 04:03:43 +00:00
3a888f639e
Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.
...
llvm-svn: 68669
2009-04-09 03:50:16 +00:00
f15454866c
Fix grammaros in comments.
...
llvm-svn: 68666
2009-04-09 02:06:09 +00:00
3b2df10c9e
Re-apply 68552.
...
Tested by bootstrapping llvm-gcc and using that to build llvm.
llvm-svn: 68645
2009-04-08 21:14:34 +00:00
866c174f79
Fix PR3795: Apply Dan's suggested fix for
...
ARMTargetLowering::isLegalAddressingMode.
llvm-svn: 68619
2009-04-08 17:55:28 +00:00
d173f4237d
Avoid a hard coded constant.
...
llvm-svn: 68603
2009-04-08 08:09:33 +00:00
44ea053a49
Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.
...
llvm-svn: 68602
2009-04-08 06:24:04 +00:00
4b489c75c2
Handle indirect function calls.
...
Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.
llvm-svn: 68597
2009-04-08 05:38:48 +00:00
ad3e549a53
Implement support for using modeling implicit-zero-extension on x86-64
...
with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.
This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.
Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.
Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.
Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.
Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.
llvm-svn: 68576
2009-04-08 00:15:30 +00:00
4aa25b79f9
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
...
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
llvm-svn: 68560
2009-04-07 22:35:25 +00:00
1edda06792
Reduce code duplication on the TLS implementation.
...
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
llvm-svn: 68552
2009-04-07 21:37:46 +00:00
fde2110aa9
PR2985 / <rdar://problem/6584986>
...
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.
llvm-svn: 68545
2009-04-07 20:34:09 +00:00
0669f6d295
Handle 'a' modifier in ARM inline assembly.
...
Patch by Richard Pennington.
llvm-svn: 68464
2009-04-06 21:46:51 +00:00
0b08df8c09
Map stack based frameindices for spills to zero based indices that can be accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc.
...
llvm-svn: 68442
2009-04-06 10:54:50 +00:00
6bedd59894
Wrap some lines to fix indentation problems.
...
llvm-svn: 68405
2009-04-03 21:08:42 +00:00
d24b794f31
Fix some comments.
...
llvm-svn: 68404
2009-04-03 20:53:25 +00:00
f4de47b91e
CMake: removed IA64AsmPrinter.cpp from lib/Target/IA64/CMakeLists.txt
...
llvm-svn: 68384
2009-04-03 12:11:43 +00:00
06d2d8ba72
Separate MIPS asmprinter
...
llvm-svn: 68383
2009-04-03 10:41:41 +00:00
354171f060
Fix target library name
...
llvm-svn: 68382
2009-04-03 10:41:17 +00:00
b1cce77929
Fix comment
...
llvm-svn: 68381
2009-04-03 10:41:00 +00:00
547b43a809
Move IA64 asmprinter to separate library
...
llvm-svn: 68380
2009-04-03 10:38:51 +00:00
9c186c5d27
Added a x86 dag combine to increase the chances to use a
...
movq for v2i64 on x86-32.
llvm-svn: 68368
2009-04-03 02:43:30 +00:00
e9cff3328f
Fixed build warnings.
...
llvm-svn: 68333
2009-04-02 18:33:12 +00:00
cc841a3810
To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize.
...
llvm-svn: 68329
2009-04-02 18:03:10 +00:00
1e8860a8f5
Params are not being generated as static globals now. The caller passes them onto the callee's stack directly and the callee loads the argvals from its own stack. Clang generated frameindexes validatd by recalculating the stack as if all frameindexes represent 1-byte slots.
...
llvm-svn: 68327
2009-04-02 17:42:00 +00:00
d2eb0a63a1
silence warning in release-asserts build.
...
llvm-svn: 68253
2009-04-01 22:14:45 +00:00
cff6953c45
Use CHAR_BIT instead of hard-coding 8 in several places where it
...
is appropriate. This helps visually differentiate host-oriented
calculations from target-oriented calculations.
llvm-svn: 68227
2009-04-01 18:45:54 +00:00
0170402fe8
Use LLVM type names instead of C type names in comments, to be
...
less ambiguous and less C-specific.
llvm-svn: 68219
2009-04-01 18:10:16 +00:00
cf1ec2cc68
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
...
assembly.
llvm-svn: 68218
2009-04-01 17:58:54 +00:00
d9d6e427d6
i128 shift libcalls are not available on x86.
...
llvm-svn: 68133
2009-03-31 19:38:51 +00:00
6b42dfddf4
Reapply 68073, with fixes. EH Landing-pad basic blocks are not
...
entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.
llvm-svn: 68129
2009-03-31 18:39:13 +00:00
9277379fc0
remove unused arguments.
...
llvm-svn: 68109
2009-03-31 16:16:57 +00:00
6afae239c2
Really temporarily revert r68073.
...
llvm-svn: 68100
2009-03-31 08:42:40 +00:00
b8017e02ca
Oy! When reverting r68073, I added in experimental code. Sorry...
...
llvm-svn: 68099
2009-03-31 08:41:31 +00:00
c4b08e5eb0
Revert r68073. It's causing a failure in the Apple-style builds.
...
llvm-svn: 68092
2009-03-31 08:26:26 +00:00
885bc6de52
X86 address mode isel tweak. If the base of the address is also used by a CopyToReg (i.e. it's likely live-out), do not fold the sub-expressions into the addressing mode to avoid computing the address twice. The CopyToReg use will be isel'ed to a LEA, re-use it for address instead.
...
This is not yet enabled.
llvm-svn: 68082
2009-03-31 01:13:53 +00:00
adccd30533
Except in asm-verbose mode, avoid printing labels for blocks that are
...
only reachable via fall-through edges. This dramatically reduces the
number of labels printed, and thus also the number of labels the
assembler must parse and remember.
llvm-svn: 68073
2009-03-30 22:55:17 +00:00
a84a318873
When optimzing a mul by immediate into two, the resulting mul's should get a x86 specific node to avoid dag combiner from hacking on them further.
...
llvm-svn: 68066
2009-03-30 21:36:47 +00:00
57178e8822
Fix comment to match function name.
...
llvm-svn: 68050
2009-03-30 18:49:37 +00:00
56709fdffe
Fix thinko: put stuff with both global and local relocations into data.rel{.ro}, not .local
...
llvm-svn: 68036
2009-03-30 17:37:43 +00:00
7c5f3c40ca
Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness.
...
llvm-svn: 68032
2009-03-30 15:27:43 +00:00
c247fd396c
Add data.rel stuff
...
llvm-svn: 68031
2009-03-30 15:27:03 +00:00
bea241a5f5
IA64 is as weird as Alpha wrt r/o relocs :)
...
llvm-svn: 68007
2009-03-29 17:14:35 +00:00
014a86f216
Alpha always requires global relocations to be r/w regardless of PIC.
...
llvm-svn: 68006
2009-03-29 17:14:14 +00:00
088ebede53
Honour relocation behaviour stuff for ro objects
...
llvm-svn: 68005
2009-03-29 17:13:49 +00:00
356d974a93
add a note
...
llvm-svn: 67953
2009-03-28 19:26:55 +00:00
1f11c3c36f
Use array_lengthof
...
llvm-svn: 67950
2009-03-28 19:02:18 +00:00
6ff3dabbb4
Have only one definition of X86AddrNumOperands.
...
llvm-svn: 67949
2009-03-28 18:55:31 +00:00
c2a17d3022
Make code a bit less brittle by no hardcoding the number
...
of operands in an address in so many places.
llvm-svn: 67945
2009-03-28 17:03:24 +00:00
fd81c73cde
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
...
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
llvm-svn: 67917
2009-03-28 05:57:29 +00:00
669f1d0b0b
remove trailing whitespace
...
llvm-svn: 67874
2009-03-27 23:06:27 +00:00
705f2a6cd2
Avoid hardcoding that X86 addresses have 4 operands.
...
llvm-svn: 67848
2009-03-27 15:57:50 +00:00
227815437a
Use less hard coded constants to make the code less brittle.
...
llvm-svn: 67846
2009-03-27 15:45:05 +00:00
e728019392
I am trying to add a segment to the X86 addresses matching to
...
improve TLS support (see http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090309/075220.html ), but that code is VERY brittle.
This patch just makes it a bit more resistant.
llvm-svn: 67843
2009-03-27 15:26:30 +00:00
d88ebc352c
-no-implicit-float means explicit fp operations are legal.
...
llvm-svn: 67784
2009-03-26 23:06:32 +00:00
904f14663d
tADDhirr is a thumb instruction. Do not allow this code to be reached in non-thumb mode.
...
llvm-svn: 67765
2009-03-26 19:09:01 +00:00
aa28be652c
Pull transform from target-dependent code into target-independent code.
...
llvm-svn: 67742
2009-03-26 06:14:09 +00:00
78b7cbe668
fix warning in -asserts mode.
...
llvm-svn: 67739
2009-03-26 05:29:34 +00:00
f38fd11a26
fix some warnings in release-asserts mode.
...
llvm-svn: 67738
2009-03-26 05:28:26 +00:00
3c04970f31
fix an apparently real bug exposed by a warning in -asserts mode.
...
llvm-svn: 67737
2009-03-26 05:28:14 +00:00
3871781c7b
fix warning in -asserts build.
...
llvm-svn: 67736
2009-03-26 05:25:59 +00:00
94f299f2c5
Match this pattern so that we can generate simpler code:
...
%a = ...
%b = and i32 %a, 2
%c = srl i32 %b, 1
%d = br i32 %c,
into
%a = ...
%b = and %a, 2
%c = X86ISD::CMP %b, 0
%d = X86ISD::BRCOND %c ...
This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.
llvm-svn: 67728
2009-03-26 01:47:50 +00:00
189d67181c
Doxygen-ify comments.
...
llvm-svn: 67727
2009-03-26 01:46:56 +00:00
2755edf4c4
do not rely on callee being operand 0
...
llvm-svn: 67681
2009-03-25 06:32:59 +00:00
5e5a63cf8f
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
...
llvm-svn: 67668
2009-03-25 01:47:28 +00:00
9966403e90
Don't print global names twice with -asm-verbose.
...
llvm-svn: 67667
2009-03-25 01:08:42 +00:00
efd2d44aa5
I was convinced that it's ok to allow a second i8 return value
...
to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.
llvm-svn: 67588
2009-03-24 01:04:34 +00:00
a774a99245
Do not emit comments unless -asm-verbose.
...
llvm-svn: 67580
2009-03-24 00:17:40 +00:00
93eefa0043
Fix internal representation of fp80 to be the
...
same as a normal i80 {low64, high16} rather
than its own {high64, low16}. A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.
llvm-svn: 67562
2009-03-23 21:16:53 +00:00
4f2fea1a21
Now that errs() is properly non-buffered, there's no need to
...
explicitly flush it.
llvm-svn: 67526
2009-03-23 15:57:19 +00:00
4a683478d5
Correct some comments. Operand numbers start at 0.
...
llvm-svn: 67518
2009-03-23 15:40:10 +00:00
968c3b0d6e
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
...
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
772de0ae2d
Fix a grammaro in a comment that Bill noticed.
...
llvm-svn: 67507
2009-03-23 05:02:44 +00:00
70d9929def
Add comments explaining why there's only one register for
...
i8 return values.
llvm-svn: 67502
2009-03-23 04:28:24 +00:00
9b9586a5ae
Removed AFGR32 register class
...
Handle odd registers allocation in FGR32.
llvm-svn: 67422
2009-03-21 00:05:07 +00:00
dc40d5ae2c
Fix a few more indentation problems and an 80-column violation.
...
llvm-svn: 67416
2009-03-20 23:16:43 +00:00
7117a916f5
No functional changes. Fix indentation and whitespace only.
...
llvm-svn: 67412
2009-03-20 22:42:55 +00:00
4655d731e1
Fixed comment for libcalls.
...
llvm-svn: 67373
2009-03-20 14:10:20 +00:00
c035b7e879
Reformatting. Inserted code comments. Cleaned interfaces.
...
Removed unncessary code. No functionality change.
llvm-svn: 67371
2009-03-20 13:42:20 +00:00
f67448adf8
Added option to enable generating less precise mad (multiply addition)
...
for those architectures that support the instruction.
llvm-svn: 67363
2009-03-20 05:06:58 +00:00
bfd4ad67c7
Remove strange extra semicolons.
...
llvm-svn: 67287
2009-03-19 05:51:39 +00:00
dbe3f77f5b
Add support to tablegen for naming the nodes themselves, not just the operands,
...
in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.
llvm-svn: 67286
2009-03-19 05:21:56 +00:00
3b7b301a24
Added support for Mips O32 Calling Convention
...
llvm-svn: 67280
2009-03-19 02:12:28 +00:00
a6bed3e950
Disable the "call to immediate" optimization on x86-64. It is
...
not safe in general because the immediate could be an arbitrary
value that does not fit in a 32-bit pcrel displacement.
Conservatively fall back to loading the value into a register
and calling through it.
We still do the optzn on X86-32.
llvm-svn: 67142
2009-03-18 00:43:52 +00:00
df52d3d477
CellSPU:
...
Revert inadvertent mis-fix of fneg.
llvm-svn: 67084
2009-03-17 16:45:16 +00:00
d6e571b202
Recognize bswapl as bswap too.
...
llvm-svn: 67072
2009-03-17 02:45:40 +00:00
77a9279d80
Recognize "bswapq" as an alternate spelling for the bswap instruction.
...
llvm-svn: 67071
2009-03-17 02:17:27 +00:00
839ad0a5f3
CellSPU:
...
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
to the constant pool when they correspond to SPU's shufb instruction's
special mask values. This avoids the overhead of performing a shuffle on a
zero-filled vector just to get the special constant when the memory load
suffices.
llvm-svn: 67067
2009-03-17 01:15:45 +00:00
d1db1aba66
CellSPU:
...
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.
llvm-svn: 67048
2009-03-16 18:47:25 +00:00
aa7db25235
This causes incorrect stack frame allocation when the last object is an array allocated on the stack which would lead
...
the compiled program to run over its stack. Thanks to Gil Dogon
llvm-svn: 67034
2009-03-15 23:28:07 +00:00
f98cd1b48a
Use %rip-relative addressing on x86-64 whenever practical, as
...
it has a smaller encoding than absolute addressing.
llvm-svn: 67002
2009-03-14 02:33:41 +00:00
2293eb6037
Don't forego folding of loads into 64-bit adds when the other
...
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.
llvm-svn: 67001
2009-03-14 02:07:16 +00:00
a62e4ab690
Improve FastISel's handling of truncates to i1, and implement
...
ptrtoint and inttoptr in X86FastISel. These casts aren't always
handled in the generic FastISel code because X86 sometimes needs
custom code to do truncation and zero-extension.
llvm-svn: 66988
2009-03-13 23:53:06 +00:00
c0bb959591
Fix FastISel's assumption that i1 values are always zero-extended
...
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.
llvm-svn: 66941
2009-03-13 20:42:20 +00:00
997b74ac61
add 8 and 16 bit TLS moves.
...
add a fixme note on how to remove code duplication.
llvm-svn: 66932
2009-03-13 19:39:55 +00:00
71144973f3
Improve sext and zext of TLS variables.
...
llvm-svn: 66922
2009-03-13 18:37:06 +00:00
3fb71c8f49
generalize this code so that fast isel handles integer truncates to i1, which
...
codegen to the same thing as integer truncates to i8 (the top bits are
just undefined). This implements rdar://6667338
llvm-svn: 66902
2009-03-13 16:36:42 +00:00
798fd56d0f
These instructions have special lowering that may lower them to SSE
...
instructions. Prevent that if we don't want implicit uses of SSE.
llvm-svn: 66877
2009-03-13 08:41:47 +00:00
1fb8aedd1e
Fix some significant problems with constant pools that resulted in unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues.
...
1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants.
2. MachineConstantPool alignment field is also a log2 value.
3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values.
4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries.
5. Asm printer uses expensive data structure multimap to track constant pool entries by sections.
6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic.
Solutions:
1. ConstantPoolSDNode alignment field is changed to keep non-log2 value.
2. MachineConstantPool alignment field is also changed to keep non-log2 value.
3. Functions that create ConstantPool nodes are passing in non-log2 alignments.
4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT.
5. Asm printer uses cheaper data structure to group constant pool entries.
6. Asm printer compute entry offsets after grouping is done.
7. Change JIT code to compute entry offsets on the fly.
llvm-svn: 66875
2009-03-13 07:51:59 +00:00
99cc133710
generalize the previous code to use the full generality of LEA
...
for i32/i64 expressions (we could also do i16 on cpus where
i16 lea is fast, but I didn't add this). On the example, we now
generate:
_test:
movl 4(%esp), %eax
cmpl $42, (%eax)
setl %al
movzbl %al, %eax
leal 4(%eax,%eax,8), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
cmpl $41, (%eax)
movl $4, %ecx
movl $13, %eax
cmovg %ecx, %eax
ret
llvm-svn: 66869
2009-03-13 05:53:31 +00:00
4be6df5d86
optimize the case of cond ? 42 : 41 and friends. This compiles the
...
example to:
_test:
movl 4(%esp), %eax
cmpl $41, (%eax)
setg %al
movzbl %al, %eax
orl $4294967294, %eax
ret
instead of:
movl 4(%esp), %eax
cmpl $41, (%eax)
movl $4294967294, %ecx
movl $4294967295, %eax
cmova %ecx, %eax
ret
which is smaller in code size and faster. rdar://6668608
llvm-svn: 66868
2009-03-13 05:22:11 +00:00
a1d92423cf
Enhance address-mode folding of ISD::ADD to handle cases where the
...
operands can't both be fully folded at the same time. For example,
in the included testcase, a global variable is being added with
an add of two values. The global variable wants RIP-relative
addressing, so it can't share the address with another base
register, but it's still possible to fold the initial add.
llvm-svn: 66865
2009-03-13 02:25:09 +00:00
2a332aa866
Re-apply 66024 with fixes: 1. Fixed indirect call to immediate address assembly. 2. Fixed JIT encoding by making the address pc-relative.
...
llvm-svn: 66803
2009-03-12 18:15:39 +00:00
4147f08e44
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
...
related transformations out of target-specific dag combine into the
ARM backend. These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).
Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently
with the recently added cp constant select optimization, but is a
very general xform. For example, we now compile the second example
in const-select.ll to:
_test:
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
seta %al
movzbl %al, %eax
movl 4(%esp), %ecx
movsbl (%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal 4(%eax), %ecx
movsd LCPI2_0, %xmm0
ucomisd 8(%esp), %xmm0
cmovbe %eax, %ecx
movsbl (%ecx), %eax
ret
This passes multisource and dejagnu.
llvm-svn: 66779
2009-03-12 06:52:53 +00:00
a492d29c23
improve comment.
...
llvm-svn: 66778
2009-03-12 06:46:02 +00:00
ef0b7cc2d5
On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
...
llvm-svn: 66776
2009-03-12 05:59:15 +00:00
8bb50e2344
Forgot to check-in this as part of 7761.
...
llvm-svn: 66763
2009-03-12 03:20:07 +00:00
f883419b2f
Banksel optimization is now based on the section names of symbols, since the symbols in one section will always be put into one bank.
...
llvm-svn: 66761
2009-03-12 02:10:45 +00:00
5637df37cd
Revert r66024. The JIT encoding for CALLpcrel32 is wrong -- see PR3773, and the
...
assembly text output uses an indirect call ("call *") instead of a direct call.
llvm-svn: 66735
2009-03-11 23:01:47 +00:00
294943c99b
optimize i8 and i16 tls values.
...
llvm-svn: 66725
2009-03-11 22:40:04 +00:00
42adc73a2b
Add a -no-implicit-float flag. This acts like -soft-float, but may generate
...
floating point instructions that are explicitly specified by the user.
llvm-svn: 66719
2009-03-11 22:30:01 +00:00
4581bebf2a
It makes no sense to have a ODR version of common
...
linkage, so remove it.
llvm-svn: 66690
2009-03-11 20:14:15 +00:00
25c6a46a81
For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
...
llvm-svn: 66684
2009-03-11 18:47:57 +00:00
93e87652f2
fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.ll
...
llvm-svn: 66660
2009-03-11 16:14:25 +00:00
e2881053c9
Remove the one-definition-rule version of extern_weak
...
linkage: this linkage type only applies to declarations,
but ODR is only relevant to globals with definitions.
llvm-svn: 66650
2009-03-11 08:08:06 +00:00
ce6a26cb1a
Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
...
llvm-svn: 66645
2009-03-11 06:35:11 +00:00
248ad00afd
formatting change, reduce indentation. No functionality change.
...
llvm-svn: 66642
2009-03-11 05:48:52 +00:00
afb355f281
Mark the Defs and Uses of STATUS register correctly, plus some reformatting.
...
llvm-svn: 66540
2009-03-10 10:35:34 +00:00
b0d4009ec8
Add more information to the EFLAGS note.
...
llvm-svn: 66515
2009-03-10 00:26:23 +00:00
d5b35ee215
Add a note about EFLAGS optimization.
...
llvm-svn: 66508
2009-03-09 23:47:02 +00:00
0ee0da841d
ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.
...
llvm-svn: 66435
2009-03-09 20:25:39 +00:00
ce5dfb692a
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
...
llvm-svn: 66429
2009-03-09 19:15:00 +00:00
d5ac9d87b4
do not export all the X86FastISel symbols, ever.
...
llvm-svn: 66382
2009-03-08 18:44:31 +00:00
ec415efb44
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
...
llvm-svn: 66365
2009-03-08 04:02:49 +00:00
393ac62837
add a note.
...
llvm-svn: 66360
2009-03-08 03:04:26 +00:00
cfd1f7aa9f
add a note.
...
llvm-svn: 66359
2009-03-08 01:54:43 +00:00
12da8ce3d2
Introduce new linkage types linkonce_odr, weak_odr, common_odr
...
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
llvm-svn: 66339
2009-03-07 15:45:40 +00:00
ff659b5b86
Arithmetic instructions don't set EFLAGS bits OF and CF bits
...
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.
llvm-svn: 66318
2009-03-07 01:58:32 +00:00
c719d73eec
Don't use plain INC32 and DEC32 on x86-64; it needs
...
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.
llvm-svn: 66207
2009-03-05 21:32:23 +00:00
e014b193c9
When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
...
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.
llvm-svn: 66206
2009-03-05 21:29:28 +00:00
2c2f192c74
Fix the "test" optimization to recognize "dec" as an add of
...
negative one, as subtracts of immediates are canonicalized
to adds.
llvm-svn: 66180
2009-03-05 19:32:48 +00:00
55d7b2ac4f
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
...
llvm-svn: 66058
2009-03-04 19:44:21 +00:00
f8920d0c75
Correct this comment.
...
llvm-svn: 66057
2009-03-04 19:24:25 +00:00
cc329b567d
When using MachineInstr operand indices on SDNodes, the number
...
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.
llvm-svn: 66056
2009-03-04 19:23:38 +00:00
9edd616b59
Fix PR3666: isel calls to constant addresses.
...
llvm-svn: 66024
2009-03-04 06:48:53 +00:00
6728f892be
Revert r66004 for now; it's causing a variety of test failures.
...
llvm-svn: 66008
2009-03-04 03:54:19 +00:00
fe8d71f42a
Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
...
result from add, sub, inc, and dec instructions in simple cases.
llvm-svn: 66004
2009-03-04 02:33:24 +00:00
b8905c4e2c
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
...
llvm-svn: 65996
2009-03-04 01:41:49 +00:00
3a72265d41
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC
...
instructions. These aren't used yet.
llvm-svn: 65965
2009-03-03 19:53:46 +00:00
530e038940
Use early exit to reduce indentation. No functional change.
...
llvm-svn: 65962
2009-03-03 19:26:27 +00:00
92b551bc2b
Fix a bunch of Doxygen syntax issues. Escape special characters,
...
and put @file directives on their own comment line.
llvm-svn: 65920
2009-03-03 02:55:14 +00:00
85cefe8567
Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
...
arbitrary vector sizes. Add an optional MinSplatBits parameter to specify
a minimum for the splat element size. Update the PPC target to use the
revised interface.
llvm-svn: 65899
2009-03-02 23:24:16 +00:00
d8ea0e144e
Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
...
method in a BuildVectorSDNode "pseudo-class".
llvm-svn: 65747
2009-03-01 01:13:55 +00:00
d844dc305e
Added another darwin subtarget
...
llvm-svn: 65662
2009-02-28 00:25:30 +00:00
000421eade
Refactor TLS code and add some tests. The tests and expected results are:
...
pic | declaration | linkage | visibility |
!pic | declaration | external | default | tls1.ll tls2.ll | local exec
pic | declaration | external | default | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default | tls3.ll tls4.ll | initial exec
pic | !declaration | external | default | tls3-pic.ll tls4-pic.ll | general dynamic
!pic | declaration | external | hidden | tls7.ll tls8.ll | local exec
pic | declaration | external | hidden | X | local dynamic
!pic | !declaration | external | hidden | tls9.ll tls10.ll | local exec
pic | !declaration | external | hidden | X | local dynamic
!pic | declaration | internal | default | tls5.ll tls6.ll | local exec
pic | declaration | internal | default | X | local dynamic
The ones marked with an X have not been implemented since local dynamic is not implemented.
llvm-svn: 65632
2009-02-27 13:37:18 +00:00
4609dbe222
Alignment values for i64 and f64 on ppc64 were wrong,
...
possibly for the reason suggested by the comment.
No wonder it didn't work very well. This unblocks
bootstrap with assertions on ppc.
llvm-svn: 65601
2009-02-27 00:56:35 +00:00
40abb7b5d0
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.
...
llvm-svn: 65499
2009-02-26 03:12:02 +00:00
a49de9de2e
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
...
llvm-svn: 65482
2009-02-25 22:49:59 +00:00
5c10a3aa7f
Add a totally synthetic situation I came up with while looking at a bug in
...
related code.
llvm-svn: 65437
2009-02-25 06:52:48 +00:00
bb878288cb
Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
...
results via reference parameters.
This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.
llvm-svn: 65426
2009-02-25 03:12:50 +00:00
c5437ea429
Overhaul my earlier submission due to feedback. It's a large patch, but most of
...
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
llvm-svn: 65379
2009-02-24 08:30:20 +00:00
318d7376ba
Fast-isel can't do TLS yet, so it should fall back to SDISel
...
if it sees TLS addresses.
llvm-svn: 65341
2009-02-23 22:03:08 +00:00
9f8fddeed8
Only v1i16 (i.e. _m64) is returned via RAX / RDX.
...
llvm-svn: 65313
2009-02-23 09:03:22 +00:00
e684da3e5d
Generate better code for v8i16 shuffles on SSE2
...
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
llvm-svn: 65311
2009-02-23 08:49:38 +00:00
9ee052bcdc
Propagate debug loc info through prologue/epilogue.
...
llvm-svn: 65298
2009-02-23 00:42:30 +00:00
9d31aca679
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
...
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
llvm-svn: 65296
2009-02-22 23:36:09 +00:00
2448aa1d8d
Add a note.
...
llvm-svn: 65275
2009-02-22 08:13:45 +00:00
e4ffc030e2
Be bug compatible with gcc by returning MMX values in RAX.
...
llvm-svn: 65274
2009-02-22 08:05:12 +00:00
91193c0094
Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.
...
llvm-svn: 65273
2009-02-22 08:04:23 +00:00
42aae86590
Drop bunch of half-working stuff in the ext_weak linkage support.
...
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).
The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)
llvm-svn: 65230
2009-02-21 11:53:32 +00:00
82aa14fae8
Make sure this doesn't access .end() too.
...
llvm-svn: 65213
2009-02-21 01:11:36 +00:00
81ebf9a578
Make sure we don't dereference the .end() of the container.
...
llvm-svn: 65211
2009-02-21 01:07:26 +00:00
56759ee658
Propagate more debug loc infos. This also includes some code cleaning.
...
llvm-svn: 65207
2009-02-21 00:43:56 +00:00
5191934371
We need to propagate the debug location information even when dealing with the
...
prologue/epilogue.
llvm-svn: 65206
2009-02-21 00:32:08 +00:00
Eli Friedman