25bbcc67fa
Make the buildbot see green (to make it easier to spot the next person
...
that puts a new warning in).
llvm-svn: 72797
2009-06-03 19:07:46 +00:00
11231d0c75
Remove unnecessary #includes.
...
llvm-svn: 72782
2009-06-03 16:47:12 +00:00
215921ef94
Emit file directives correctly in case of a .bc is generated by llvm-ld after linking in several .bc files.
...
llvm-svn: 72781
2009-06-03 16:27:49 +00:00
b011aa3a5e
FrameIndex could be used as a value (addressof (arg)) or as an address.
...
Expand it exactly like GlobalAddress.
Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.
llvm-svn: 72776
2009-06-03 15:31:12 +00:00
a53241a880
Fixed a bug in which signed comparisons were being used instead of unsigned comparisons.
...
llvm-svn: 72771
2009-06-03 13:36:44 +00:00
c66ad73e35
Avoid a warning "'U' might be used uninitialized in
...
this function" when using a not-too-smart compiler.
llvm-svn: 72768
2009-06-03 12:05:18 +00:00
ab0c710fae
Temporarily revert 72756 for now.
...
llvm-svn: 72757
2009-06-03 07:40:47 +00:00
dfe6e689fd
Fold preceding / trailing base inc / dec into the single load / store as well.
...
llvm-svn: 72756
2009-06-03 06:14:58 +00:00
fc262babc3
Revert r72734. The Darwin assembler doesn't support the static
...
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.
llvm-svn: 72746
2009-06-03 00:37:20 +00:00
448641d87c
On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
...
llvm-svn: 72734
2009-06-02 20:09:31 +00:00
5234d3795f
Revert 72707 and 72709, for the moment.
...
llvm-svn: 72712
2009-06-02 03:12:52 +00:00
7fde88cce8
Add missing file.
...
llvm-svn: 72709
2009-06-01 23:48:58 +00:00
0b8ca79253
Make the implicit inputs and outputs of target-independent
...
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.
Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.
The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.
llvm-svn: 72707
2009-06-01 23:27:20 +00:00
ff10450680
Comment grammaro/clarification.
...
llvm-svn: 72706
2009-06-01 23:13:42 +00:00
67f472feed
Trailing whitespace.
...
llvm-svn: 72705
2009-06-01 23:12:52 +00:00
12694bd8ac
Implement review feedback. Make thumb2 'normal' subtarget feature
...
llvm-svn: 72698
2009-06-01 20:00:48 +00:00
9fd794bebf
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
...
llvm-svn: 72697
2009-06-01 19:57:37 +00:00
2afc641e04
Do not emit "generic" CPU string. This fixes PR4291.
...
llvm-svn: 72696
2009-06-01 19:03:17 +00:00
c1c2c68945
Fix a grammaro and clarify a comment.
...
llvm-svn: 72668
2009-05-31 17:52:18 +00:00
a194c3a69e
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
...
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
2009-05-30 20:51:52 +00:00
7142ad75a1
(i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
...
llvm-svn: 72618
2009-05-30 08:43:27 +00:00
09f17a8479
Untabification.
...
llvm-svn: 72604
2009-05-30 01:09:53 +00:00
b6f4538683
Add placeholder for thumb2 stuff
...
llvm-svn: 72593
2009-05-29 23:41:08 +00:00
716e688fca
More h-registers tricks: folding zext nodes.
...
llvm-svn: 72558
2009-05-29 01:44:43 +00:00
2e09bd3d34
The MONITOR and MWAIT instructions have insufficient information for
...
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.
Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.
llvm-svn: 72556
2009-05-28 23:40:46 +00:00
cc3ae1f2ff
Fix MOVMSKPDrr encoding.
...
llvm-svn: 72535
2009-05-28 18:55:28 +00:00
60618fe4ac
Fix PSIGND encoding bug. Patch by Sean Callanan.
...
llvm-svn: 72534
2009-05-28 18:48:53 +00:00
ae028d48be
Emit debug info for locals with proper scope.
...
llvm-svn: 72531
2009-05-28 18:24:11 +00:00
fc4707a331
Mark the branch insns correctly.
...
llvm-svn: 72529
2009-05-28 17:32:56 +00:00
335311c67a
Fixing problems that got exposed after the refactoring of LegalizeDAG done in 72447.
...
llvm-svn: 72521
2009-05-28 06:59:57 +00:00
5806e18ce1
Return the operand rather than a null SDValue when the given SELECT_CC
...
is actually legal. Part of LegalizeDAG cleanups.
llvm-svn: 72513
2009-05-28 04:31:08 +00:00
97021ae319
This patch brings the list of attributes in CPPBackend.cpp up to date with the
...
list in Attributes.h. It also reorders the CPPBackend list to match so that
it's easier to see that it's complete.
llvm-svn: 72510
2009-05-28 03:16:17 +00:00
0feb0e6071
"The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but
...
the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."
Patch by Sean Callanan!
llvm-svn: 72508
2009-05-28 02:04:00 +00:00
a9cda8abf2
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
...
e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
llvm-svn: 72507
2009-05-28 00:35:15 +00:00
a56159b7e9
Ger rid of some dead code.
...
llvm-svn: 72494
2009-05-27 20:39:00 +00:00
4db1631a43
Fix sfence jit encoding. Patch by Sean Callanan.
...
llvm-svn: 72488
2009-05-27 18:38:01 +00:00
a72a505a80
Added support for fround, fextend and FP_TO_SINT
...
llvm-svn: 72483
2009-05-27 17:23:44 +00:00
acb851a8c0
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
...
FP_TO_XINT. Necessary for some cleanups I'm working on. Updated
from the previous version (r72431) to fix a bug and make some things a
bit clearer.
llvm-svn: 72445
2009-05-27 00:47:34 +00:00
d96b117872
Back out r72431, it is causing a number of compilation crashes with clang.
...
llvm-svn: 72436
2009-05-26 21:27:02 +00:00
96180b5387
Update CPU capabilities for AMD machines
...
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
8c7bff96ed
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
...
FP_TO_XINT. Necessary for some cleanups I'm working on.
llvm-svn: 72431
2009-05-26 19:18:56 +00:00
9b65031add
add some late optimizations that GCC does. It thinks these are a win
...
even on Core2, not just AMD processors which was a surprise to me.
llvm-svn: 72396
2009-05-25 20:28:19 +00:00
9a3f3a5c3d
fix typo
...
llvm-svn: 72395
2009-05-25 19:51:07 +00:00
be31b7b534
we should eventually add -march=atom and the new atom movbe instruction.
...
llvm-svn: 72387
2009-05-25 16:34:44 +00:00
9c6ab1a34d
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
...
nodes it generates.
llvm-svn: 72356
2009-05-24 02:03:36 +00:00
2199ed399f
Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
...
moment.
llvm-svn: 72350
2009-05-23 22:44:52 +00:00
0b91cc4260
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
...
llvm-svn: 72337
2009-05-23 19:51:43 +00:00
fa6f1eea36
Emit ARM Build Attributes
...
llvm-svn: 72336
2009-05-23 19:51:20 +00:00
08bf4c0f5a
Propagate CPU string out of SubtargetFeatures
...
llvm-svn: 72335
2009-05-23 19:50:50 +00:00
dfe4f25355
Make the x86 backend custom-lower UINT_TO_FP and FP_TO_UINT on 32-bit
...
systems instead of attempting to promote them to a 64-bit SINT_TO_FP or
FP_TO_SINT. This is in preparation for removing the type legalization
code from LegalizeDAG: once type legalization is gone from LegalizeDAG,
it won't be able to handle the i64 operand/result correctly.
This isn't quite ideal, but I don't think any other operation for any
target ends up in this situation, so treating this case specially seems
reasonable.
llvm-svn: 72324
2009-05-23 09:59:16 +00:00
770c8e7927
CMake: Use libpthread in tblgen when needed. Updated list of source
...
files for PIC16 target.
llvm-svn: 72277
2009-05-22 20:55:15 +00:00
ccbc17b3a3
Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls
...
for ARM. This fixes rdar://6908807.
llvm-svn: 72269
2009-05-22 17:38:41 +00:00
43becc23c2
Emit debug information for globals (which include automatic variables as well because on PIC16 they are emitted as globals by the frontend).
...
llvm-svn: 72262
2009-05-22 13:58:45 +00:00
dd0e23610a
Minor formatting fixes.
...
llvm-svn: 72172
2009-05-20 16:30:25 +00:00
960983371c
Try again. Allow call to immediate address for ELF or when in static relocation mode.
...
llvm-svn: 72160
2009-05-20 04:53:57 +00:00
61da18645b
Cannot use immediate as call absolute target in PIC mode.
...
llvm-svn: 72154
2009-05-20 01:11:00 +00:00
335fa435dd
Fix pr4227: Handle large immediate values in inline assembly.
...
llvm-svn: 72138
2009-05-19 21:27:57 +00:00
840e3281ff
Follow up on new support for memory operands in ARM inline assembly.
...
This fixes pr4233.
llvm-svn: 72115
2009-05-19 18:33:02 +00:00
e666cc5206
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
...
the stack. Patch by Sandeep Patel.
llvm-svn: 72106
2009-05-19 10:02:36 +00:00
a2c462bbe9
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
...
llvm-svn: 72105
2009-05-19 05:53:42 +00:00
5668077271
Spacing fix.
...
llvm-svn: 72083
2009-05-19 00:46:42 +00:00
74503f0b31
Add OpSize to 16-bit ADC and SBB.
...
llvm-svn: 72045
2009-05-18 21:41:59 +00:00
320d54a2d8
Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has
...
to run last because it needs to know the exact size and position of every
basic block. Currently CodePlacementOpt is set up to run last. It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.
llvm-svn: 72037
2009-05-18 20:55:32 +00:00
1df0e80380
Fill in the missing patterns for ADC and SBB.
...
Some comment cleanup.
llvm-svn: 72022
2009-05-18 17:44:15 +00:00
6de08cd093
Mark rotl/rotr as expand. This generates pretty ugly code, but this is better than nothing.
...
llvm-svn: 71976
2009-05-17 10:16:28 +00:00
6b5523aec2
Typo
...
llvm-svn: 71975
2009-05-17 10:15:22 +00:00
af917d8f85
Fix a missing def-flag on a Mips epilogue load.
...
llvm-svn: 71935
2009-05-16 07:26:06 +00:00
99abac8996
Remember to set def-flag on register loaded from stack slot in CellSPU.
...
llvm-svn: 71934
2009-05-16 07:25:44 +00:00
35ea2c9aa6
Reflow to fit 80-col.
...
llvm-svn: 71813
2009-05-14 23:23:37 +00:00
13e4f10c53
Reflow to fit 80-col.
...
llvm-svn: 71812
2009-05-14 23:22:47 +00:00
06928192ae
Update the names of the exception handling sjlj instrinsics to
...
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).
llvm-svn: 71758
2009-05-14 00:46:35 +00:00
91fa781df3
Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places
...
llvm-svn: 71735
2009-05-13 22:32:43 +00:00
ab0d23396a
Run code placement optimization for targets that want it (arm and x86 for now).
...
llvm-svn: 71726
2009-05-13 21:42:09 +00:00
f7b83c7ae7
Change MachineInstrBuilder::addReg() to take a flag instead of a list of
...
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.
I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).
llvm-svn: 71722
2009-05-13 21:33:08 +00:00
4a71ae268b
Run through the list of globals once and sectionize all types of globlas includeing declarations. Later emit them from their section lists.
...
llvm-svn: 71661
2009-05-13 15:13:17 +00:00
536de01bcf
Add an int64_t variant of abs, for host environments
...
without one. Use it where we were using abs on
int64_t objects.
(I strongly suspect the casts to unsigned in the
fragments in LoopStrengthReduce are not doing whatever
the original intent was, but the obvious change to
uint64_t doesn't work. Maybe later.)
llvm-svn: 71612
2009-05-13 00:24:22 +00:00
aeca45dd6f
Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is
...
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.
llvm-svn: 71610
2009-05-12 23:59:14 +00:00
46632d89bb
correct register class for tADDspi to GPR since the register will always be SP
...
llvm-svn: 71602
2009-05-12 22:30:18 +00:00
6b167d684a
More MSVC fixes -- class/struct conflicts.
...
llvm-svn: 71601
2009-05-12 21:55:29 +00:00
b41de47856
80 col violations.
...
llvm-svn: 71582
2009-05-12 20:17:52 +00:00
ce8cfb41e8
Fix up a few minor typos in comments.
...
llvm-svn: 71563
2009-05-12 17:35:29 +00:00
2f4e56fd2e
Fix 80-col violations and remove trailing whitespace. No functional changes.
...
llvm-svn: 71562
2009-05-12 17:09:30 +00:00
83adfb4a9f
Iterate over globals once and sectionize them into appropriate sections.
...
Later in asmprinter, go over thsese sections and print them.
Do not print empty sections.
llvm-svn: 71560
2009-05-12 17:07:27 +00:00
679e578c65
We do not need to create a label for external defs and decls,
...
just emit a comment for readability.
llvm-svn: 71544
2009-05-12 06:52:41 +00:00
63f5f68024
Mark mayLoad, mayStore for insns correctly and use them
...
to check if an insn is accessing memory during mem sel optimization.
llvm-svn: 71537
2009-05-12 04:30:38 +00:00
d76d71a291
Factor the code for collecting IV users out of LSR into an IVUsers class,
...
and generalize it so that it can be used by IndVarSimplify. Implement the
base IndVarSimplify transformation code using IVUsers. This removes
TestOrigIVForWrap and associated code, as ScalarEvolution now has enough
builtin overflow detection and folding logic to handle all the same cases,
and more. Run "opt -iv-users -analyze -disable-output" on your favorite
loop for an example of what IVUsers does.
This lets IndVarSimplify eliminate IV casts and compute trip counts in
more cases. Also, this happens to finally fix the remaining testcases
in PR1301.
Now that IndVarSimplify is being more aggressive, it occasionally runs
into the problem where ScalarEvolutionExpander's code for avoiding
duplicate expansions makes it difficult to ensure that all expanded
instructions dominate all the instructions that will use them. As a
temporary measure, IndVarSimplify now uses a FixUsesBeforeDefs function
to fix up instructions inserted by SCEVExpander. Fortunately, this code
is contained, and can be easily removed once a more comprehensive
solution is available.
llvm-svn: 71535
2009-05-12 02:17:14 +00:00
55173b7646
Avoid unneeded SIB byte encoding. Patch by Zoltan Varga.
...
llvm-svn: 71520
2009-05-12 00:07:35 +00:00
ec63c85505
Don't #include DerivedTypes.h from TargetData.h.
...
llvm-svn: 71468
2009-05-11 19:38:09 +00:00
1dbb40f481
Fix two wording errors that Duncan spotted.
...
llvm-svn: 71459
2009-05-11 18:51:16 +00:00
b0ddbbe7c4
LLVM has unaligned loads and stores now.
...
llvm-svn: 71449
2009-05-11 18:06:05 +00:00
7ee3a4371f
Upgrade this example to new-style syntax.
...
llvm-svn: 71447
2009-05-11 18:04:52 +00:00
faf75c8c9a
Convert a subtract into a negate and an add when it helps x86
...
address folding.
llvm-svn: 71446
2009-05-11 18:02:53 +00:00
17a999efac
remove some done things: we have nocapture and SROA is smarter.
...
llvm-svn: 71443
2009-05-11 17:41:40 +00:00
183a7ec027
add a note
...
llvm-svn: 71442
2009-05-11 17:36:33 +00:00
ada3549ae1
Change TargetData::getIntPtrType() to return an IntegerType instead of
...
just a Type.
llvm-svn: 71426
2009-05-11 11:13:47 +00:00
ea5a8d8808
Fix more naming issues.
...
compiler libcalls start with .lib. now.
fixed section names.
llvm-svn: 71424
2009-05-11 08:52:04 +00:00
9d175c15e7
Detect calls to compiler intrinsics and emit an extern declarations
...
only for those. These extern declarations to intrinsics are currently
being emitted at the bottom of generated .s file, which works fine with
gpasm(not sure about MPSAM though).
PIC16 linker generates errors for few cases (function-args/struct_args_5) if you do not include any
extern declarations (even if no intrinsics are being used), but that
needs to be fixed in the linker itself.
llvm-svn: 71423
2009-05-11 06:01:38 +00:00
004192bde3
Module iterator contains list of filescope functions as well, we don't need to emit and global declarations for them. This was working earlier and was broken during one of the recent commit for PIC16 naming.
...
llvm-svn: 71394
2009-05-10 16:18:39 +00:00
3c8e0c52d7
Add imm-reg and imm-mem patters for cmp on msp430
...
(imm is allowed to be source operand, not dest...)
llvm-svn: 71393
2009-05-10 14:49:00 +00:00
258f851629
Changed lowering and asmprinter to use ABI Names class called PAN.
...
llvm-svn: 71386
2009-05-10 05:23:47 +00:00
f2d589fe24
Remove a completed optimization. Add a potential optimization I ran
...
into.
llvm-svn: 71352
2009-05-09 08:40:15 +00:00
af9eaa830a
Rename PaddedSize to AllocSize, in the hope that this
...
will make it more obvious what it represents, and stop
it being confused with the StoreSize.
llvm-svn: 71349
2009-05-09 07:06:46 +00:00
3033816c80
Use 16 bit arithmetic while retrieving the address of callee's frame during indirect function calls, and set pclath before every call to retrieve the frame address.
...
llvm-svn: 71323
2009-05-09 05:11:19 +00:00
8f43afd3bb
PPC::B and PPC::BCC's target operand may be an immediate.
...
llvm-svn: 71282
2009-05-08 23:09:25 +00:00
65a58168cc
Factor out cycle-finder code and make it generic.
...
llvm-svn: 71241
2009-05-08 18:51:58 +00:00
ea618dd0ba
Allow 8 bit select in custom inserter
...
llvm-svn: 71239
2009-05-08 18:51:21 +00:00
1484cfe945
Expand UREM / SREM into libcalls
...
llvm-svn: 71236
2009-05-08 18:50:41 +00:00
c3e1b392ae
Add 8 bit select
...
llvm-svn: 71235
2009-05-08 18:50:26 +00:00
f1d9b91434
Fix PR4152: asm constraint validation happens before dag combine, so we
...
need to work a bit to combine things like (x+c1+c2) into x+c3.
llvm-svn: 71232
2009-05-08 18:23:14 +00:00
2fa281106a
Optimize code placement in loop to eliminate unconditional branches or move unconditional branch to the outside of the loop. e.g.
...
/// A:
/// ...
/// <fallthrough to B>
///
/// B: --> loop header
/// ...
/// jcc <cond> C, [exit]
///
/// C:
/// ...
/// jmp B
///
/// ==>
///
/// A:
/// ...
/// jmp B
///
/// C: --> new loop header
/// ...
/// <fallthough to B>
///
/// B:
/// ...
/// jcc <cond> C, [exit]
llvm-svn: 71209
2009-05-08 06:34:09 +00:00
2f6bddd2b1
Add missing #include for "strlen" which is used inline in this header. Fixes
...
build under gcc 4.3.
llvm-svn: 71208
2009-05-08 06:22:25 +00:00
89e72b9c4a
Moved pic16 naming functions to correct place.
...
No functionality change.
llvm-svn: 71207
2009-05-08 04:50:14 +00:00
a55d46100e
Eliminate compiler warnings.
...
llvm-svn: 71149
2009-05-07 05:31:56 +00:00
364f3efa53
CMake: Updated lib/Target/PIC16/CMakeLists.txt.
...
llvm-svn: 71115
2009-05-06 20:40:05 +00:00
72b6582c0f
Use X86AddrNumOperands instead of magic constant one
...
more place. This fixes a bunch of x86-64 JIT regressions.
(Introduced when the value of the magic constant changed
in 68645. At the time apparently nobody noticed; failures
were hidden in 70343-70439 by an unrelated bug, so showed
up again as "new" failures in 70440.)
llvm-svn: 71106
2009-05-06 19:04:30 +00:00
960ae0660b
Emit banksel and movlp instructions.
...
Split large global data (both initialized and un-initialized) into multiple sections of <= 80 bytes.
Provide routines to manage PIC16 ABI naming conventions.
llvm-svn: 71073
2009-05-06 08:02:01 +00:00
be9fa506ad
Add basic support for code generation of
...
addrspace(257) -> FS relative on x86. Patch by Zoltan Varga!
llvm-svn: 70992
2009-05-05 18:52:19 +00:00
a35aed567a
Revert part of 70929 that has to do with determining whether a SIB byte is needed. It causes a lot of x86_64 JIT failures.
...
llvm-svn: 70986
2009-05-05 18:18:57 +00:00
1ff2727c95
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
...
llvm-svn: 70950
2009-05-05 00:30:09 +00:00
c298ccb998
- Avoid the longer SIB encoding on x86_64 when it's not needed.
...
- Synchronize instruction length computation code in X86InstrInfo with code in X86CodeEmitter.cpp
Patch by Zoltan Varga.
llvm-svn: 70929
2009-05-04 22:49:16 +00:00
bb525f7e02
X86FastISel doesn't support the -tailcallopt ABI.
...
llvm-svn: 70902
2009-05-04 19:50:33 +00:00
2d1e7321f6
Fix code emission for conditional branches.
...
Patch by Collin Winter!
llvm-svn: 70898
2009-05-04 19:10:38 +00:00
630f4e1eb3
Trim unnecessary #includes.
...
llvm-svn: 70880
2009-05-04 17:11:06 +00:00
4ff60e0cc2
Handle implicit zext in a better way. Shamelessly stolen from x86 backend.
...
Thanks for Dan Gohman for suggestion!
llvm-svn: 70782
2009-05-03 15:50:18 +00:00
1324f810d7
Update due to mainline API change
...
llvm-svn: 70769
2009-05-03 13:19:42 +00:00
d089ef1003
Add TODO list :)
...
llvm-svn: 70768
2009-05-03 13:19:24 +00:00
47fcd72e24
Make handling of conditional stuff much more straightforward
...
llvm-svn: 70767
2009-05-03 13:19:09 +00:00
dedfa00ba1
Temporary disable imm patterns for cmp. Actually, all cmp-related stuff (select_cc, setcc, br_cc). needs to be rethought
...
llvm-svn: 70766
2009-05-03 13:18:50 +00:00
eb2152f753
Expand divisions into libcalls
...
llvm-svn: 70765
2009-05-03 13:18:33 +00:00
29747e9c26
Custom lower SIGN_EXTEND
...
llvm-svn: 70763
2009-05-03 13:17:49 +00:00
3c48ea7dbe
Some eye-candy
...
llvm-svn: 70762
2009-05-03 13:17:31 +00:00
48e21c57f1
Print function header / footer
...
llvm-svn: 70761
2009-05-03 13:17:11 +00:00
8847e3e554
Fix printing: je => jeq
...
llvm-svn: 70760
2009-05-03 13:16:54 +00:00
f3a6bc8562
Add 8bit shifts
...
llvm-svn: 70759
2009-05-03 13:16:37 +00:00
61763b532a
Handle logical shift right (at least I hope so :) )
...
llvm-svn: 70758
2009-05-03 13:16:17 +00:00
20a91130ce
Handle anyext
...
llvm-svn: 70757
2009-05-03 13:15:57 +00:00
e31559576f
Expand all sorts of indirect branches
...
llvm-svn: 70755
2009-05-03 13:15:40 +00:00
41917df643
Add InsertBranch() hook for tail mergeing
...
llvm-svn: 70754
2009-05-03 13:15:22 +00:00
4b0a0f18fb
Implement bswap
...
llvm-svn: 70753
2009-05-03 13:15:03 +00:00
ba0e81d4b2
Properly handle ExternalSymbol's
...
llvm-svn: 70752
2009-05-03 13:14:46 +00:00
de60d1caef
Expand muls (all mulls!) to libcalls for now
...
llvm-svn: 70751
2009-05-03 13:14:25 +00:00
0da755ee3e
Provide addc and subc
...
llvm-svn: 70748
2009-05-03 13:13:34 +00:00
a3f7a83ad8
Add left shift
...
llvm-svn: 70747
2009-05-03 13:13:17 +00:00
aa43d0b182
Add direct branch
...
llvm-svn: 70746
2009-05-03 13:12:58 +00:00
24bfb51416
It's error-prone to maintain two separate variants of asmprinting stuff, one of which is even used. Drop second (aka 'intel') variant of operands. It can be added later, if needed.
...
llvm-svn: 70745
2009-05-03 13:12:37 +00:00
b6321e15f7
Lower select with custom inserted and make condjumps generic
...
llvm-svn: 70744
2009-05-03 13:12:23 +00:00
962720129d
Add first draft for conditions, conditional branches, etc
...
llvm-svn: 70743
2009-05-03 13:12:06 +00:00
aa51bff808
Hanle i8 returns
...
llvm-svn: 70742
2009-05-03 13:11:48 +00:00
7212c15e70
Small tweaking
...
llvm-svn: 70741
2009-05-03 13:11:35 +00:00
f2b50994ca
Add prologue/epilogue emission. Fix frame pointer handling.
...
llvm-svn: 70740
2009-05-03 13:11:20 +00:00
1af0b61e7c
Add code for save/restore of callee-saved registers
...
llvm-svn: 70739
2009-05-03 13:11:04 +00:00
b85f4ec819
Two more hooks for RA and FP registers
...
llvm-svn: 70738
2009-05-03 13:10:40 +00:00
7784ae9a6f
Proper handle loading of effective address of stack slot stuff
...
llvm-svn: 70737
2009-05-03 13:10:26 +00:00
0d1234fd69
Match frame indexes
...
llvm-svn: 70736
2009-05-03 13:10:11 +00:00
f6af822c76
First draft of stack slot loads / stores lowering
...
llvm-svn: 70735
2009-05-03 13:09:57 +00:00
ed65671768
Reverse order of memory arguments
...
llvm-svn: 70734
2009-05-03 13:09:40 +00:00
04888305f6
Remove bogus pattern
...
llvm-svn: 70733
2009-05-03 13:09:24 +00:00
6399a3d628
Correct asmprinting of memory operands
...
llvm-svn: 70732
2009-05-03 13:09:10 +00:00
a3bce28ae0
Match wrapper node for address
...
llvm-svn: 70731
2009-05-03 13:08:51 +00:00
cfc97056e7
Add lowering for global address nodes. Not pretty efficient though.
...
llvm-svn: 70730
2009-05-03 13:08:33 +00:00
b5613928f5
Some early full call lowering draft for direct calls
...
llvm-svn: 70729
2009-05-03 13:08:13 +00:00
ec3f0b3f9d
Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
...
llvm-svn: 70728
2009-05-03 13:07:54 +00:00
5613510c81
Add CALL lowering.
...
llvm-svn: 70727
2009-05-03 13:07:31 +00:00
c995ddd017
Add bunch of mem-whatever patterns
...
llvm-svn: 70726
2009-05-03 13:07:10 +00:00
f702a0085c
Add bunch of reg-mem inst patterns
...
llvm-svn: 70725
2009-05-03 13:06:46 +00:00
ed1c3dfa0f
Add normal and trunc stores
...
llvm-svn: 70724
2009-05-03 13:06:26 +00:00
31ecd23a9e
Basic support for mem=>reg moves
...
llvm-svn: 70723
2009-05-03 13:06:03 +00:00
80a73e7d8b
Add 8-bit insts. zext behaviour is not modelled yet
...
llvm-svn: 70722
2009-05-03 13:05:42 +00:00
b900245e13
Add 8-bit regclass and pattern for sext_inreg
...
llvm-svn: 70721
2009-05-03 13:05:22 +00:00
b638fb10f5
Add pattern for OR
...
llvm-svn: 70720
2009-05-03 13:05:00 +00:00
654cb0a761
Add reg-imm variants
...
llvm-svn: 70719
2009-05-03 13:04:41 +00:00
37709c3584
Add hint to nop
...
llvm-svn: 70718
2009-05-03 13:04:23 +00:00
6339db830e
Add more instructions
...
llvm-svn: 70717
2009-05-03 13:04:06 +00:00
e32c817d2c
Cleanup
...
llvm-svn: 70716
2009-05-03 13:03:50 +00:00
15a515b1af
Add dummy lowering for shifts
...
llvm-svn: 70715
2009-05-03 13:03:33 +00:00
55a085b539
We don't have any div at all - thus mark it as expensive
...
llvm-svn: 70714
2009-05-03 13:03:14 +00:00
abb51755c8
We're not going to spend 100% of time in interrupts, do we? :)
...
llvm-svn: 70713
2009-05-03 13:02:57 +00:00
8a17dff7d0
Add simple reg-reg add.
...
llvm-svn: 70712
2009-05-03 13:02:39 +00:00
6ff6fc95a0
gas uses lower letter for register names
...
llvm-svn: 70711
2009-05-03 13:02:22 +00:00
d7afd69e3b
Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
...
llvm-svn: 70710
2009-05-03 13:02:04 +00:00
c942782b3b
Add function body printing routine
...
llvm-svn: 70709
2009-05-03 13:01:41 +00:00
ef811d8e05
Add 'msp430' target triple recognizer
...
llvm-svn: 70708
2009-05-03 13:01:23 +00:00
a9b7df98e6
Make emit{Prologue,Epilogue}() noop for now
...
llvm-svn: 70707
2009-05-03 13:01:04 +00:00
69f51f0b41
Add callee-saved regs & reg classes getter hooks
...
llvm-svn: 70706
2009-05-03 13:00:46 +00:00
efcd5aa381
Add simple FP indicator for given function hook
...
llvm-svn: 70705
2009-05-03 13:00:28 +00:00
c10f98ace3
Provide set of reserved registers
...
llvm-svn: 70704
2009-05-03 13:00:11 +00:00
7bfc3ea2ee
Add proper ISD::RET lowering
...
llvm-svn: 70703
2009-05-03 12:59:50 +00:00
3849be6ca1
Add first draft of MSP430 calling convention stuff and draft of ISD::FORMAL_ARGUMENTS node lowering.
...
llvm-svn: 70702
2009-05-03 12:59:33 +00:00
77e5a11ec2
Fix register names, fix register allocation order, handle frame pointer.
...
llvm-svn: 70701
2009-05-03 12:59:16 +00:00
64717bbc14
Clearify the usage and add some debug stuff
...
llvm-svn: 70700
2009-05-03 12:58:58 +00:00
e10f69a8a7
Cleanup
...
llvm-svn: 70699
2009-05-03 12:58:40 +00:00
128e8a188f
Add cmake script. No idea whether it works or not :)
...
llvm-svn: 70698
2009-05-03 12:58:22 +00:00
4130a7c1e7
Add a note
...
llvm-svn: 70697
2009-05-03 12:58:05 +00:00
7c4db99df3
Typo
...
llvm-svn: 70695
2009-05-03 12:57:47 +00:00
101380015c
Dummy MSP430 backend
...
llvm-svn: 70694
2009-05-03 12:57:15 +00:00
e01821edbd
'The attached patch fixes an issue where llc -march=cpp fails with
...
"Invalid primitive type" on input containing the x86_fp80 type.'
Patch by Collin Winter!
llvm-svn: 70610
2009-05-01 23:54:26 +00:00
31af617924
Fix compilation for some targets other than x86.
...
llvm-svn: 70522
2009-04-30 23:50:26 +00:00
a5037484a4
Make DebugLoc independent of DwarfWriter.
...
-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)
llvm-svn: 70520
2009-04-30 23:22:31 +00:00
e651f25a7b
getCommonSubClass() - Calculate the largest common sub-class of two register
...
classes.
This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.
llvm-svn: 70512
2009-04-30 21:23:32 +00:00
db3a57ec5c
Set mayLoad on MOVZX32_NOREXrm8 too.
...
llvm-svn: 70466
2009-04-30 03:11:48 +00:00
99578674fd
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
...
llvm-svn: 70461
2009-04-30 00:58:57 +00:00
1fba01bbcd
remove progname which is never set. PR4085
...
llvm-svn: 70453
2009-04-30 00:24:33 +00:00
026e5d7667
Instead of passing in an unsigned value for the optimization level, use an enum,
...
which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
7e6e352735
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
...
llvm-svn: 70425
2009-04-29 22:47:44 +00:00
5f829d896d
Implement review feedback for vector shuffle work.
...
llvm-svn: 70372
2009-04-29 05:20:52 +00:00
ccd30945f9
Add a public method called getAddressSpace() to the GlobalAddressSDNode.
...
llvm-svn: 70366
2009-04-29 04:43:24 +00:00
084669a1c9
Second attempt:
...
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
dac88bae4f
Properly print 'P' modifier on inline asm memory operands.
...
This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!
llvm-svn: 70328
2009-04-28 21:49:33 +00:00
7bfed8a9f4
GlobalValue is always pointer type, so an assert isn't required.
...
llvm-svn: 70300
2009-04-28 16:39:45 +00:00
56f2987a87
r70270 isn't ready yet. Back this out. Sorry for the noise.
...
llvm-svn: 70275
2009-04-28 01:04:53 +00:00
d0ae15946c
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
...
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...
llvm-svn: 70270
2009-04-28 00:21:31 +00:00
8d6d4b9289
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
...
PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
llvm-svn: 70225
2009-04-27 18:41:29 +00:00
2986972118
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
...
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
llvm-svn: 70211
2009-04-27 16:41:36 +00:00
ec542ca65e
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
...
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
llvm-svn: 70210
2009-04-27 16:33:14 +00:00
ba99bddf1f
Break up long multi-mnemonic strings into separate lines for readability.
...
llvm-svn: 70209
2009-04-27 15:13:28 +00:00
e15bf109be
Revised 68749 to allow matching of load/stores for address spaces < 256.
...
llvm-svn: 70197
2009-04-27 07:22:10 +00:00
3ad60b18cb
add support for detecting process features on win64, patch by
...
Nicolas Capens!
llvm-svn: 70057
2009-04-25 18:27:23 +00:00
0041bd3523
Change LowerCallResult method so that CCValAssign::BCvt can be used with
...
f64 types. This is not used for anything yet.
llvm-svn: 70006
2009-04-25 00:33:20 +00:00
40e784ce69
Adjust a comment to reflect what the code does. Splitting a 64-bit argument
...
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.
llvm-svn: 69978
2009-04-24 17:05:01 +00:00
f134b2d212
Fix up some problems with getCopyToReg and getCopyFromReg nodes being
...
chained and "flagged" together. I also made a few changes to handle the
chain and flag values more consistently. I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).
llvm-svn: 69977
2009-04-24 17:00:36 +00:00
62d47d2361
Remove unnecessary references to f32 types. After specifying that f32
...
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.
llvm-svn: 69973
2009-04-24 16:55:25 +00:00
c1396a2313
Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
...
very elegant, but neither is the tls specification :-(
llvm-svn: 69968
2009-04-24 12:59:40 +00:00
b93db668b3
Revert 69952. Causes testsuite failures on linux x86-64.
...
llvm-svn: 69967
2009-04-24 12:40:33 +00:00
bb881d66f4
PR2957
...
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
2009-04-24 03:42:54 +00:00
870c33f14b
Fix spurious indentation in a comment.
...
llvm-svn: 69934
2009-04-23 22:41:05 +00:00
5058f240d9
Banksel immediate constant will always immediately follow the GA/ES, so scan an insn from beginnin to find out the banksel operand.
...
llvm-svn: 69883
2009-04-23 10:34:58 +00:00
14efb90fcf
Add support for printing MO_ExternalSymbol operands in
...
memory operand tuples. This doesn't ever come up in normal
code however.
llvm-svn: 69848
2009-04-23 00:57:37 +00:00
107b2818ce
Make the function begin label start after ther data pointer.
...
The address of data frame for function can be obtained by subtracting 2 from the function begin label.
llvm-svn: 69801
2009-04-22 12:02:36 +00:00
7ce5cc6bd1
Get rid of what looks like a copy-and-pasted typo.
...
Spotted by gcc-4.5.
llvm-svn: 69673
2009-04-21 09:44:39 +00:00
47ed1f5293
TLS_addr64 and TLS_addr32 define RDI and EAX. They don't use them.
...
This fixes PR4002.
llvm-svn: 69672
2009-04-21 08:22:09 +00:00
3e3ef7c4d9
Handle direct aggregate type arguments.
...
llvm-svn: 69665
2009-04-21 05:54:51 +00:00
1addf64735
Make X86's copyRegToReg able to handle copies to and from subclasses.
...
This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.
llvm-svn: 69635
2009-04-20 22:54:34 +00:00
2c441c6afe
Remove unused variable.
...
llvm-svn: 69624
2009-04-20 20:34:38 +00:00
f8b85477ae
Move duplicated AddLiveIn function from X86 and ARM backends to be a method
...
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
2009-04-20 18:36:57 +00:00
958d5eb032
Match C backend only if it explicitly requested.
...
llvm-svn: 69613
2009-04-20 18:07:22 +00:00
0fcc019d36
Emit the auto variables of a function into a different section than parameters.
...
llvm-svn: 69605
2009-04-20 16:59:35 +00:00
6c8bcf9da1
Fixed a few 64 bit cases in X86InstrInfo::commuteInstruction
...
llvm-svn: 69417
2009-04-18 05:16:01 +00:00
06684350c4
Recommit r69335 and r69336. These were not causing problems.
...
llvm-svn: 69394
2009-04-17 22:40:38 +00:00
b0b10f8bf6
Move the AddLiveIn function definition closer to its uses.
...
llvm-svn: 69382
2009-04-17 20:42:34 +00:00
deeaf70dad
Rearrange code to reduce indentation.
...
llvm-svn: 69381
2009-04-17 20:40:45 +00:00
ea09d4aca8
Clean up formatting, remove trailing whitespace, fix comment typos and
...
punctuation. No functional changes.
llvm-svn: 69378
2009-04-17 20:35:10 +00:00
a4c2290e5f
Use CallConvLower.h and TableGen descriptions of the calling conventions
...
for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
355fe12c82
For general dynamic TLS access we must use
...
leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
llvm-svn: 69350
2009-04-17 14:35:58 +00:00
30527b1114
Revert r69335 and r69336. They were causing build failures.
...
llvm-svn: 69347
2009-04-17 04:19:22 +00:00
09dbb0b5e0
MOV8rr_NOREX is a "Move" instruction. This doesn't currently
...
matter, because this instruction isn't generated until after
things that care.
llvm-svn: 69336
2009-04-17 00:45:17 +00:00
74835ce1cb
Don't use MOV8rr_NOREX on x86-32. It doesn't actually hurt anything at
...
present, but it's inconsistent.
llvm-svn: 69335
2009-04-17 00:43:09 +00:00
a8919d0a35
Fix some failures in targets on available_externally functions,
...
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
llvm-svn: 69333
2009-04-17 00:26:12 +00:00
5e42177a0f
fix PR3995. A scale must be 1, 2, 4 or 8.
...
llvm-svn: 69284
2009-04-16 12:34:53 +00:00
de7b3e74be
Fix 80-column violations.
...
llvm-svn: 69204
2009-04-15 19:48:57 +00:00
6711216e84
Add a folding table entry for MOV8rr_NOREX.
...
llvm-svn: 69203
2009-04-15 19:48:28 +00:00
Mike Stump