Commit Graph

18347 Commits

Author SHA1 Message Date
Bill Wendling e9434778f7 Temporary revert of 175320.
llvm-svn: 175322
2013-02-15 23:22:32 +00:00
Bill Wendling a060d0efd8 Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.

llvm-svn: 175320
2013-02-15 23:18:01 +00:00
Derek Schuff 8878bcc9e7 If bundle alignment is enabled, do not add data to a fragment with instructions
With bundle alignment, instructions all get their own MCFragments
(unless they are in a bundle-locked group). For instructions with
fixups, this is an MCDataFragment. Emitting actual data (e.g. for
.long) attempts to re-use MCDataFragments, which we don't want int
this case since it leads to fragments which exceed the bundle size.
So, don't reuse them in this case.
Also adds a test and fixes some formatting.

llvm-svn: 175316
2013-02-15 22:50:52 +00:00
Pekka Jaaskelainen 62848c9c24 Forgot to 'svn add' the LoopVectorizer tests for the new parallel loop metadata, sorry.
llvm-svn: 175311
2013-02-15 21:50:19 +00:00
Paul Redmond f29ddfe93f enable SDISel sincos optimization for GNU environments
- add sincos to runtime library if target triple environment is GNU
- added canCombineSinCosLibcall() which checks that sincos is in the RTL and
  if the environment is GNU then unsafe fpmath is enabled (required to
  preserve errno)
- extended sincos-opt lit test

Reviewed by: Hal Finkel

llvm-svn: 175283
2013-02-15 18:45:18 +00:00
Arnaud A. de Grandmaison 61c167c62b Teach InstCombine to work with smaller legal types in icmp (shl %v, C1), C2
It enables to work with a smaller constant, which is target friendly for those which can compare to immediates.
It also avoids inserting a shift in favor of a trunc, which can be free on some targets.

This used to work until LLVM-3.1, but regressed with the 3.2 release.

llvm-svn: 175270
2013-02-15 14:35:47 +00:00
Kostya Serebryany a968568165 [asan] support long double on 64-bit. See https://code.google.com/p/address-sanitizer/issues/detail?id=151
llvm-svn: 175266
2013-02-15 12:46:06 +00:00
Tim Northover 3533ad6bbd AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

llvm-svn: 175258
2013-02-15 09:33:43 +00:00
Tim Northover 5466e36fb5 AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

llvm-svn: 175257
2013-02-15 09:33:26 +00:00
Bill Wendling 26b95756c1 Simplify the 'operator<' for the attribute object.
llvm-svn: 175252
2013-02-15 05:25:26 +00:00
Anna Zaks 269d1fa991 Revert "Fix testcase for attribute ordering."
This reverts commit 58f20a3cbfca7384fe5e25e095f18572736a4792.

llvm-svn: 175249
2013-02-15 04:15:53 +00:00
Anna Zaks 61040b915d Revert "Fix testcase for attribute ordering."
This reverts commit 997c6516ca161073a1d516ebca7c0ca7722f64e2.

llvm-svn: 175248
2013-02-15 04:15:50 +00:00
Bill Wendling f7d8d767fb Fix testcase for attribute ordering.
llvm-svn: 175238
2013-02-15 01:04:46 +00:00
Reed Kotler f022147790 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 

llvm-svn: 175237
2013-02-15 01:04:38 +00:00
Bill Wendling fa1d248ccf Fix testcase for attribute ordering.
llvm-svn: 175236
2013-02-15 00:58:25 +00:00
Joel Jones 0f8617b17e The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.

This patch uses TwoOperandAliasConstraint to add the two argument form.

It also fixes an 80-column formatting problem in:
  test/MC/ARM/neon-bitwise-encoding

<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions

llvm-svn: 175221
2013-02-14 23:18:40 +00:00
Kay Tiong Khoo 7b564da474 death to extra whitespace
llvm-svn: 175200
2013-02-14 19:15:14 +00:00
Kay Tiong Khoo f809c6491d added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases

llvm-svn: 175196
2013-02-14 19:08:21 +00:00
Nadav Rotem 495b1a43c1 Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
llvm-svn: 175190
2013-02-14 18:28:52 +00:00
Weiming Zhao c598700788 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186
2013-02-14 18:10:21 +00:00
Vincent Lejeune f940fd05bd R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183
2013-02-14 16:57:19 +00:00
Rafael Espindola 86d5345988 Revert r15266. This fixes llvm.org/pr15266.
llvm-svn: 175173
2013-02-14 16:23:08 +00:00
Krzysztof Parzyszek f71a69d608 Add testcase for llvm-dwarfdump to test parsing of the pubnames data.
llvm-svn: 175168
2013-02-14 16:10:58 +00:00
Kristof Beyls 2efb59a719 Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164
2013-02-14 14:46:12 +00:00
Elena Demikhovsky 5b9d426907 Moved line-info.ll to DebugInfo\X86 directory
llvm-svn: 175150
2013-02-14 09:07:34 +00:00
Elena Demikhovsky 70247a807b The test failed on Windows. I've changed the platform to run to "x86_64-apple-darwin".
llvm-svn: 175146
2013-02-14 08:23:08 +00:00
Elena Demikhovsky d0a0cc80cd Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

llvm-svn: 175144
2013-02-14 08:20:26 +00:00
Michel Danzer 51d5eb2f63 R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175138
2013-02-14 07:43:51 +00:00
Andrew Trick 6871e5f4e5 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85.

Use a triple this time.

llvm-svn: 175134
2013-02-14 03:45:08 +00:00
Nick Lewycky 06417743cf Teach the DataLayout aware constant folder to be much more aggressive towards
'and' instructions. This is a pattern that shows up a lot in ubsan binaries.

llvm-svn: 175128
2013-02-14 03:23:37 +00:00
Andrew Trick 836bf1526b Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

llvm-svn: 175124
2013-02-14 03:00:57 +00:00
Weiming Zhao 090edf7e67 temporarily revert the patch due to some conflicts
llvm-svn: 175107
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta e96f804eba Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Tom Stellard 91da4e9199 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096
2013-02-13 22:05:20 +00:00
Eli Bendersky 3ffeb68dd7 s/grep/FileCheck/ in some tests
llvm-svn: 175093
2013-02-13 22:00:37 +00:00
Eli Bendersky 04553985d7 s/grep/FileCheck/ in some tests
llvm-svn: 175089
2013-02-13 21:46:38 +00:00
Weiming Zhao 0632a4b002 Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
llvm-svn: 175088
2013-02-13 21:43:02 +00:00
Chad Rosier da05cf7ba7 [ms-inline asm] Fix up test case for non-Darwin platforms.
llvm-svn: 175087
2013-02-13 21:41:58 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Chad Rosier 282edd7caa [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533

llvm-svn: 175083
2013-02-13 21:33:44 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Manman Ren 7a4c8a783c Clean up LDV, no functionality change.
Remove dead functions: renameRegister
Move private member variables from LDV to Impl
Remove ssp/uwtable from testing case

llvm-svn: 175072
2013-02-13 20:23:48 +00:00
David Peixotto 6eecb28d3a PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
2013-02-13 19:21:47 +00:00
Benjamin Kramer 8e2637e2b0 X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

llvm-svn: 175057
2013-02-13 13:40:35 +00:00
Reed Kotler 9cb8e7b9f5 Make jumptables work for -static
llvm-svn: 175044
2013-02-13 08:32:14 +00:00
Elena Demikhovsky 9e0df7cb01 Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
llvm-svn: 175043
2013-02-13 08:02:04 +00:00
Eric Christopher 389ee71b0a Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

llvm-svn: 175036
2013-02-13 06:01:05 +00:00
Eric Christopher 2398a9a175 Finish obviously broken thought.
llvm-svn: 175035
2013-02-13 06:01:00 +00:00
Kostya Serebryany 3838f27905 [tsan] disable load widening in ThreadSanitizer mode
llvm-svn: 175034
2013-02-13 05:59:45 +00:00
Manman Ren f019cd62da Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.
RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs
without emitting them at the end.

We fix this by removing LDV from RegisterCoalescer. Also add an assertion to
make sure we call emitDebugValues if DBG_VALUEs are removed at
runOnMachineFunction.

rdar://problem/13183203
Reviewed by Andy & Jakob

llvm-svn: 175023
2013-02-13 01:14:49 +00:00