Commit Graph

14675 Commits

Author SHA1 Message Date
Elena Demikhovsky f6a30e05d5 Optimization for the following SIGN_EXTEND pairs:
v8i8  -> v8i64, 
v8i8  -> v8i32, 
v4i8  -> v4i64, 
v4i16 -> v4i64 
for AVX and AVX2.

Bug 14865.

llvm-svn: 172708
2013-01-17 09:59:53 +00:00
Eric Christopher 4c7765f166 Fix the assembly and dissassembly of DW_FORM_sec_offset. Found this by
changing both the string of the dwo_name to be correct and the type of
the statement list.

Testcases all around.

llvm-svn: 172699
2013-01-17 03:00:04 +00:00
Eric Christopher 1826617133 Add the DW_AT_GNU_addr_base for the skeleton cu. Add support for
emitting the dwarf32 version of DW_FORM_sec_offset and correct
disassembler support.

llvm-svn: 172698
2013-01-17 02:59:59 +00:00
Jakob Stoklund Olesen 965665bb48 Move MachineTraceMetrics.h into include/llvm/CodeGen.
Let targets use it.

llvm-svn: 172688
2013-01-17 01:06:04 +00:00
Jakob Stoklund Olesen 213a2f8b3f Provide a place for targets to insert ILP optimization passes.
Move the early if-conversion pass into this group.

ILP optimizations usually need to find the right balance between
register pressure and ILP using the MachineTraceMetrics analysis to
identify critical paths and estimate other costs. Such passes should run
together so they can share dominator tree and loop info analyses.

Besides if-conversion, future passes to run here here could include
expression height reduction and ARM's MLxExpansion pass.

llvm-svn: 172687
2013-01-17 00:58:38 +00:00
Eric Christopher 4d23a4ae1f Define metadata interfaces for describing a static data member
of a class. Emit static data member declarations and definitions
through correctly.

Part of PR14471.

Patch by Paul Robinson!

llvm-svn: 172590
2013-01-16 01:22:23 +00:00
Eric Christopher 962c9089d9 Split address information for DWARF5 split dwarf proposal. This involves
using the DW_FORM_GNU_addr_index and a separate .debug_addr section which
stays in the executable and is fully linked.

Sneak in two other small changes:

a) Print out the debug_str_offsets.dwo section.
b) Change form we're expecting the entries in the debug_str_offsets.dwo
   section to take from ULEB128 to U32.

Add tests for all of this in the fission-cu.ll test.

llvm-svn: 172578
2013-01-15 23:56:56 +00:00
Bill Schmidt d006c6938b This patch addresses an incorrect transformation in the DAG combiner.
The included test case is derived from one of the GCC compatibility tests.
The problem arises after the selection DAG has been converted to type-legalized
form.  The combiner first sees a 64-bit load that can be converted into a
pre-increment form.  The original load feeds into a SRL that isolates the
upper 32 bits of the loaded doubleword.  This looks like an opportunity for
DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load.

However, this transformation is not valid, as the replacement load is not
a pre-increment load.  The pre-increment load produces an extra result,
which feeds a subsequent add instruction.  The replacement load only has
one result value, and this value is propagated to all uses of the pre-
increment load, including the add.  Because the add is looking for the
second result value as its operand, it ends up attempting to add a constant
to a token chain, resulting in a crash.

So the patch simply disables this transformation for any load with more than
two result values.

llvm-svn: 172480
2013-01-14 22:04:38 +00:00
Benjamin Kramer 5ea0349ef5 When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

llvm-svn: 172322
2013-01-12 19:06:44 +00:00
Jakob Stoklund Olesen 3dd236cdd8 Limit the search space in RAGreedy::tryEvict().
When tryEvict() is looking for a cheaper register in the allocation
order, skip the tail of too expensive registers when possible.

llvm-svn: 172281
2013-01-12 00:57:44 +00:00
Jakob Stoklund Olesen 8f644449af Precompute some information about register costs.
Remember the minimum cost of the registers in an allocation order and
the number of registers at the end of the allocation order that have the
same cost per use.

This information can be used to limit the search space for
RAGreedy::tryEvict() when looking for a cheaper register.

llvm-svn: 172280
2013-01-12 00:54:59 +00:00
Nadav Rotem dbe5c72d03 PPC: Implement efficient lowering of sign_extend_inreg.
llvm-svn: 172269
2013-01-11 22:57:48 +00:00
Benjamin Kramer fb3c009b52 Remove some accidentaly duplicated code. This needs urgent cleanup :(
llvm-svn: 172248
2013-01-11 20:11:33 +00:00
Benjamin Kramer 56b31bd9d7 Split TargetLowering into a CodeGen and a SelectionDAG part.
This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still
a complete mess but as long as the edges consist of virtual call it doesn't
cause breakage. BasicTTI did static calls and thus broke some build
configurations.

llvm-svn: 172246
2013-01-11 20:05:37 +00:00
Nadav Rotem e55aa3c848 ARM Cost Model: Modify the target independent cost model to ask
the target if it supports the different CAST types. We didn't do this
on X86 because of the different register sizes and types, but on ARM
this makes sense.

llvm-svn: 172245
2013-01-11 19:54:13 +00:00
Eric Christopher 0cb6fd930e For inline asm:
- recognize string "{memory}" in the MI generation
- mark as mayload/maystore when there's a memory clobber constraint.

PR14859.

Patch by Krzysztof Parzyszek

llvm-svn: 172228
2013-01-11 18:12:39 +00:00
Andrew Trick 5907292dfd Follow-up typo correction from building the wrong branch.
llvm-svn: 172224
2013-01-11 17:51:16 +00:00
Andrew Trick ae182ce4fc Fix typo from r170452. Affects -enable-misched heuristics.
llvm-svn: 172223
2013-01-11 17:46:50 +00:00
Tim Northover 3a51aab390 Simplify writing floating types to assembly.
This removes previous special cases for each floating-point type in favour of a
shared codepath.

llvm-svn: 172189
2013-01-11 10:36:13 +00:00
Evan Cheng c8444b159a PR14896: Handle memcpy from constant string where the memcpy size is larger than the string size.
llvm-svn: 172124
2013-01-10 22:13:27 +00:00
Jakub Staszak a9286e931c Remove unneeded includes from FunctionLoweringInfo.h.
llvm-svn: 172123
2013-01-10 22:13:13 +00:00
Jakob Stoklund Olesen f0615c71fa Allow hasProperty() to be called on bundle-internal instructions.
When calling hasProperty() on an instruction inside a bundle, it should
always behave as if IgnoreBundle was passed, and just return properties
for the current instruction.

Only attempt to aggregate bundle properties whan asked about the bundle
header.

The assertion fires on existing ARM test cases without this fix.

llvm-svn: 172082
2013-01-10 18:42:44 +00:00
Jakob Stoklund Olesen 55a7be237e Support headerless bundles in MachineInstr::hasProperty().
This function can still work without a BUNDLE header instruction.

llvm-svn: 172029
2013-01-10 01:29:42 +00:00
Manman Ren 207bcbacca Stack Alignment: throw error if we can't satisfy the minimal alignment
requirement when creating stack objects in MachineFrameInfo.

Add CreateStackObjectWithMinAlign to throw error when the minimal alignment
can't be achieved and to clamp the alignment when the preferred alignment
can't be achieved. Same is true for CreateVariableSizedObject.
Will not emit error in CreateSpillStackObject or CreateStackObject.

As long as callers of CreateStackObject do not assume the object will be
aligned at the requested alignment, we should not have miscompile since
later optimizations which look at the object's alignment will have the correct
information.

rdar://12713765

llvm-svn: 172027
2013-01-10 01:10:10 +00:00
Nadav Rotem b1791a75cd ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.
llvm-svn: 172010
2013-01-09 22:29:00 +00:00
Evan Cheng 5652a8df32 Fix a DAG combine bug visitBRCOND() is transforming br(xor(x, y)) to br(x != y).
It cahced XOR's operands before calling visitXOR() but failed to update the
operands when visitXOR changed the XOR node.

rdar://12968664

llvm-svn: 171999
2013-01-09 20:56:40 +00:00
Jakob Stoklund Olesen 6922e9ca7e Don't print bundle flags.
The bundle flags are used by MachineBasicBlock::print(), they don't need
to clutter up individual MachineInstrs.

llvm-svn: 171986
2013-01-09 18:35:09 +00:00
Jakob Stoklund Olesen 68d752bf6b Don't require BUNDLE headers in MachineInstr::getBundleSize().
It is possible to build MI bundles that don't begin with a BUNDLE
header. Add support for such bundles, counting all instructions inside
the bundle.

llvm-svn: 171985
2013-01-09 18:28:16 +00:00
Sergei Larin 3b46d7ea26 Fix a typo in MachineInstr::unbundleFromSucc() method.
llvm-svn: 171983
2013-01-09 17:54:33 +00:00
Tim Northover f1450d8d7c Refactor to expose RTLIB calls to targets.
fp128 is almost but not quite completely illegal as a type on AArch64. As a
result it needs to have a register class (for argument passing mainly), but all
operations need to be lowered to runtime calls. Currently there's no way for
targets to do this (without duplicating code), as the relevant functions are
hidden in SelectionDAG. This patch changes that.

llvm-svn: 171971
2013-01-09 13:18:15 +00:00
Eric Christopher bf7bc4966c Last in the series of removing unnecessary '0' arguments for
address space. Reordered the EmitULEB128IntValue arguments to
make this easier.

llvm-svn: 171949
2013-01-09 03:52:05 +00:00
Andrew Trick 9f0b95f260 MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

llvm-svn: 171946
2013-01-09 03:36:49 +00:00
Eric Christopher e3ab3d0e2c These functions have default arguments of 0 for the last arg. Use
them.

llvm-svn: 171933
2013-01-09 01:57:54 +00:00
Eric Christopher ce0cfce775 These functions have default arguments of 0 for the last arg. Use
them and add one where it seemed obvious that we wanted one.

llvm-svn: 171932
2013-01-09 01:35:34 +00:00
Nadav Rotem b696c36fcd Cost Model: Move the 'max unroll factor' variable to the TTI and add initial Cost Model support on ARM.
llvm-svn: 171928
2013-01-09 01:15:42 +00:00
Eric Christopher 27614589dc Move the string pools down into the units. No functional change.
llvm-svn: 171905
2013-01-08 22:22:06 +00:00
Tim Northover 4bf47bc9d7 Add fp128 rtlib function names to LLVM
llvm-svn: 171867
2013-01-08 17:09:59 +00:00
Tim Northover 7bb9992cce Allow the asm printer to print fp128 values properly.
llvm-svn: 171866
2013-01-08 16:56:23 +00:00
Chandler Carruth a7c44e6ec6 Sink a function that refers to the SelectionDAG into that library in the
one file where it is called as a static function. Nuke the declaration
and the definition in lib/CodeGen, along with the include of
SelectionDAG.h from this file.

There is no dependency edge from lib/CodeGen to
lib/CodeGen/SelectionDAG, so it isn't valid for a routine in lib/CodeGen
to reference the DAG. There is a dependency from
lib/CodeGen/SelectionDAG on lib/CodeGen. This breaks one violation of
this layering.

llvm-svn: 171842
2013-01-08 05:11:57 +00:00
Eric Christopher 72a529566c Remove the llvm-local DW_TAG_vector_type tag and add a test to
make sure that vector types do work.

llvm-svn: 171833
2013-01-08 01:53:52 +00:00
Jakob Stoklund Olesen a1b246df57 Pack MachineOperand bitfields better.
Previously, 4 bits were unused.

llvm-svn: 171814
2013-01-07 23:21:44 +00:00
Jakob Stoklund Olesen 5adc4a12fb Pack MachineInstr fields better.
This shrinks MachineInstr to 64 bytes (from 72).

llvm-svn: 171813
2013-01-07 23:21:41 +00:00
Eric Christopher b800ff70c5 Whitespace and 80-col.
llvm-svn: 171803
2013-01-07 22:40:45 +00:00
Eric Christopher fba226004d Add more comments to what's going on here.
llvm-svn: 171780
2013-01-07 19:32:45 +00:00
Eric Christopher 2cbd5767ad Add support for separating strings for the split debug info DWARF5
proposal. This leaves the strings in the skeleton die as strp,
but in all dwo files they're accessed now via DW_FORM_GNU_str_index.

Add support for dumping these sections and modify the fission-cu.ll
testcase to have the correct strings and form. Fix a small bug
in the fixed form sizes routine that involved out of array accesses
for the table and add a FIXME in the extractFast routine to fix
this up.

llvm-svn: 171779
2013-01-07 19:32:41 +00:00
Chandler Carruth 95f83e0155 Sink AddrMode back into TargetLowering, removing one of the most
peculiar headers under include/llvm.

This struct still doesn't make a lot of sense, but it makes more sense
down in TargetLowering than it did before.

llvm-svn: 171739
2013-01-07 15:14:13 +00:00
Chandler Carruth 26c59fa870 Switch the SCEV expander and LoopStrengthReduce to use
TargetTransformInfo rather than TargetLowering, removing one of the
primary instances of the layering violation of Transforms depending
directly on Target.

This is a really big deal because LSR used to be a "special" pass that
could only be tested fully using llc and by looking at the full output
of it. It also couldn't run with any other loop passes because it had to
be created by the backend. No longer is this true. LSR is now just
a normal pass and we should probably lift the creation of LSR out of
lib/CodeGen/Passes.cpp and into the PassManagerBuilder. =] I've not done
this, or updated all of the tests to use opt and a triple, because
I suspect someone more familiar with LSR would do a better job. This
change should be essentially without functional impact for normal
compilations, and only change behvaior of targetless compilations.

The conversion required changing all of the LSR code to refer to the TTI
interfaces, which fortunately are very similar to TargetLowering's
interfaces. However, it also allowed us to *always* expect to have some
implementation around. I've pushed that simplification through the pass,
and leveraged it to simplify code somewhat. It required some test
updates for one of two things: either we used to skip some checks
altogether but now we get the default "no" answer for them, or we used
to have no information about the target and now we do have some.

I've also started the process of removing AddrMode, as the TTI interface
doesn't use it any longer. In some cases this simplifies code, and in
others it adds some complexity, but I think it's not a bad tradeoff even
there. Subsequent patches will try to clean this up even further and use
other (more appropriate) abstractions.

Yet again, almost all of the formatting changes brought to you by
clang-format. =]

llvm-svn: 171735
2013-01-07 14:41:08 +00:00
David Blaikie 5d3249b554 PR14759: Debug info support for C++ member pointers.
This works fine with GDB for member variable pointers, but GDB's support for
member function pointers seems to be quite unrelated to
DW_TAG_ptr_to_member_type. (see GDB bug 14998 for details)

llvm-svn: 171698
2013-01-07 05:51:15 +00:00
Chandler Carruth d3e73556d6 Move TargetTransformInfo to live under the Analysis library. This no
longer would violate any dependency layering and it is in fact an
analysis. =]

llvm-svn: 171686
2013-01-07 03:08:10 +00:00
Chandler Carruth 664e354de7 Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

llvm-svn: 171681
2013-01-07 01:37:14 +00:00
Chandler Carruth 42e9611f15 Funnel the actual TargetTransformInfo pass from the SelectionDAGISel
pass into the SelectionDAG itself rather than snooping on the
implementation of that pass as exposed by the TargetMachine. This
removes the last direct client of the ScalarTargetTransformInfo class
outside of the TTI pass implementation.

llvm-svn: 171625
2013-01-05 12:32:17 +00:00
David Blaikie 800a916f99 Emit DW_TAG_formal_parameter for unnamed parameters.
This change essentially reverts r87069 which came without a test case. It
causes no regressions in the GDB 7.5 test suite & fixes 25 xfails (commit
to the test suite to follow). If anyone can present a test case that
demonstrates why this check is necessary I'd be happy to account for it in one
way or another.

llvm-svn: 171609
2013-01-05 07:43:02 +00:00
Jakob Stoklund Olesen dc5285f102 Don't call destructors on MachineInstr and MachineOperand.
The series of patches leading up to this one makes llc -O0 run 8% faster.

When deallocating a MachineFunction, there is no need to visit all
MachineInstr and MachineOperand objects to deallocate them. All their
memory come from a BumpPtrAllocator that is about to be purged, and they
have empty destructors anyway.

This only applies when deallocating the MachineFunction.
DeleteMachineInstr() should still be used to recycle MI memory during
the codegen passes.

Remove the LeakDetector support for MachineInstr. I've never seen it
used before, and now it definitely doesn't work. With this patch, leaked
MachineInstrs would be much less of a problem since all of their memory
will be reclaimed by ~MachineFunction().

llvm-svn: 171599
2013-01-05 05:05:51 +00:00
Jakob Stoklund Olesen 1bfeecb491 Use ArrayRecycler for MachineInstr operand lists.
Instead of an std::vector<MachineOperand>, use MachineOperand arrays
from an ArrayRecycler living in MachineFunction.

This has several advantages:

- MachineInstr now has a trivial destructor, making it possible to
  delete them in batches when destroying MachineFunction. This will be
  enabled in a later patch.

- Bypassing malloc() and free() can be faster, depending on the system
  library.

- MachineInstr objects and their operands are allocated from the same
  BumpPtrAllocator, so they will usually be next to each other in
  memory, providing better locality of reference.

- Reduce MachineInstr footprint. A std::vector is 24 bytes, the new
  operand array representation only uses 8+4+1 bytes in MachineInstr.

- Better control over operand array reallocations. In the old
  representation, the use-def chains would be reordered whenever a
  std::vector reached its capacity. The new implementation never changes
  the use-def chain order.

Note that some decisions in the code generator depend on the use-def
chain orders, so this patch may cause different assembly to be produced
in a few cases.

llvm-svn: 171598
2013-01-05 05:00:09 +00:00
Jakob Stoklund Olesen fe445cd646 Add MachineRegisterInfo::moveOperands().
This function works like memmove() for MachineOperands, except it also
updates any use-def chains containing the moved operands.

The use-def chains are updated without affecting the order of operands
in the list. That isn't possible when using the
removeRegOperandFromUseList() and addRegOperandToUseList() functions.

Callers to follow soon.

llvm-svn: 171597
2013-01-05 04:38:12 +00:00
Jakob Stoklund Olesen 7f92b7ad0a Move an assertion so it doesn't dereference end().
The R600 target has test cases that exercises this code.

llvm-svn: 171538
2013-01-04 22:17:31 +00:00
Eric Christopher cad9b53c02 Add a name for the anonymous type we're creating for subrange
types and a FIXME for what we should be doing. Should solve the
immediacy of PR12069 where our debug info is crashing another
tool.

llvm-svn: 171536
2013-01-04 21:51:53 +00:00
Pedro Artigas 3383225167 small fixes to enable the reuse of the pass manager across multiple modules
llvm-svn: 171475
2013-01-04 18:04:42 +00:00
Jakob Stoklund Olesen 725d57682b Fix PR14732 by handling all kinds of IMPLICIT_DEF live ranges.
Most IMPLICIT_DEF instructions are removed by the ProcessImplicitDefs
pass, and a few are reinserted by PHIElimination when a PHI argument is
<undef>.

RegisterCoalescer was assuming that all IMPLICIT_DEF live ranges look
like those created by PHIElimination, and that their live range never
leaves the basic block.

The PR14732 test case does tricks with PHI nodes that causes a longer
IMPLICIT_DEF live range to appear. This happens very rarely, but
RegisterCoalescer should be able to handle it.

llvm-svn: 171435
2013-01-03 00:47:51 +00:00
Tom Stellard 567f886eb0 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes
DAGCombiner::reduceBuildVecConvertToConvertBuildVec() was making two
mistakes:

1. It was checking the legality of scalar INT_TO_FP nodes and then generating
vector nodes.

2. It was passing the result value type to
TargetLoweringInfo::getOperationAction() when it should have been
passing the value type of the first operand.

llvm-svn: 171420
2013-01-02 22:13:01 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Chandler Carruth be81023d74 Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

llvm-svn: 171362
2013-01-02 10:22:59 +00:00
Hal Finkel 6dbdd4307b Support ppcf128 in SelectionDAG::getConstantFP
Fixes pr14751.

Patch by Kai; Thanks!

llvm-svn: 171261
2012-12-30 19:03:32 +00:00
Nuno Lopes b6ad98224a convert a bunch of callers from DataLayout::getIndexedOffset() to GEP::accumulateConstantOffset().
The later API is nicer than the former, and is correct regarding wrap-around offsets (if anyone cares).
There are a few more places left with duplicated code, which I'll remove soon.

llvm-svn: 171259
2012-12-30 16:25:48 +00:00
Bill Wendling 74dba875e2 Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
llvm-svn: 171256
2012-12-30 13:01:51 +00:00
Bill Wendling 94dcaf8e2b Remove Function::getParamAttributes and use the AttributeSet accessor methods instead.
llvm-svn: 171255
2012-12-30 12:45:13 +00:00
Bill Wendling 698e84fc4f Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.

llvm-svn: 171253
2012-12-30 10:32:01 +00:00
Nadav Rotem b1dd52450e Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. 

llvm-svn: 171142
2012-12-27 06:47:41 +00:00
Eric Christopher 3bf29fda91 For the dwarf5 split debug info code split out the string section
per compile unit/skeleton compile unit. Update tests accordingly.

llvm-svn: 171133
2012-12-27 02:14:01 +00:00
Bob Wilson fe73ac34c5 Rename LLVMContext diagnostic handler types and functions.
These are now generally used for all diagnostics from the backend, not just
for inline assembly, so this drops the "InlineAsm" from the names.  No
functional change.  (I've left aliases for the old names but only for long
enough to let me switch over clang to use the new ones.)

llvm-svn: 171047
2012-12-25 00:07:12 +00:00
Bob Wilson 4ed23578da Add LLVMContext::emitWarning methods and use them. <rdar://problem/12867368>
When the backend is used from clang, it should produce proper diagnostics
instead of just printing messages to errs(). Other clients may also want to
register their own error handlers with the LLVMContext, and the same handler
should work for warnings in the same way as the existing emitError methods.

llvm-svn: 171041
2012-12-24 18:15:21 +00:00
Jakob Stoklund Olesen 7bca670a8b Remove a special case that doesn't seem necessary any longer.
Back when this exception was added, it was skipping a lot more code, but
now it just looks like a premature optimization.

llvm-svn: 170989
2012-12-22 17:33:22 +00:00
Jakob Stoklund Olesen b089483993 Use getNumOperands() instead of Operands.size().
The representation of the Operands array is going to change soon so it
can be allocated from a BumpPtrAllocator.

llvm-svn: 170988
2012-12-22 17:13:06 +00:00
Roman Divacky a229186a82 Remove duplicate includes.
llvm-svn: 170902
2012-12-21 17:06:44 +00:00
Evan Cheng 59421aee3d Add targets to skip running the GC passes.
llvm-svn: 170836
2012-12-21 02:57:04 +00:00
Jakob Stoklund Olesen 2455b58551 Require the two-argument MI::addOperand(MF, MO) for dangling instructions.
Instructions that are inserted in a basic block can still be decorated
with addOperand(MO).

Make the two-argument addOperand() function contain the actual
implementation. This function will now always have a valid MF reference
that it can use for memory allocation.

llvm-svn: 170798
2012-12-20 22:54:05 +00:00
Jakob Stoklund Olesen 33f5d1492d Add an MF argument to MI::copyImplicitOps().
This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.

Also add a corresponding MachineInstrBuilder method.

llvm-svn: 170797
2012-12-20 22:54:02 +00:00
Jakob Stoklund Olesen ac4210eacb Use two-arg addOperand(MF, MO) internally in MachineInstr when possible.
llvm-svn: 170796
2012-12-20 22:53:58 +00:00
Eric Christopher 48fef599a4 Whitespace and 80-column cleanup.
llvm-svn: 170771
2012-12-20 21:58:40 +00:00
Eric Christopher e698f53740 Start splitting out the debug string section handling by moving it
into the DwarfUnits class.

llvm-svn: 170770
2012-12-20 21:58:36 +00:00
Jakob Stoklund Olesen 00b28ecfae Remove two dead functions.
llvm-svn: 170766
2012-12-20 21:12:42 +00:00
Jakob Stoklund Olesen 2705333253 Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.
llvm-svn: 170716
2012-12-20 18:46:29 +00:00
Jakob Stoklund Olesen b109a7b430 Use MachineInstrBuilder in InstrEmitter.
This is supposed to be a mechanical change with no functional effects.

InstrEmitter can generate all types of MachineOperands which revealed
that MachineInstrBuilder was missing a few methods, added by this patch.

Besides providing a context pointer to MI::addOperand(),
MachineInstrBuilder seems like a better fit for this code.

llvm-svn: 170712
2012-12-20 18:08:09 +00:00
Jakob Stoklund Olesen f623e9870d Use MachineInstrBuilder in a few CodeGen passes.
This automatically passes a context pointer to MI->addOperand().

llvm-svn: 170711
2012-12-20 18:08:06 +00:00
Bob Wilson 3365b80290 Do not introduce vector operations in functions marked with noimplicitfloat.
<rdar://problem/12879313>

llvm-svn: 170630
2012-12-20 01:36:20 +00:00
Dmitri Gribenko 349d1a35ff Add a missing 'else'. Found by grep '} if'
No testcase because it is apparently not so trivial to construct.

llvm-svn: 170595
2012-12-19 22:13:01 +00:00
Eric Christopher 3c5a1914b6 Split out abbreviations for the skeleton info from the rest of
the abbreviations. Part of implementing split dwarf.

llvm-svn: 170589
2012-12-19 22:02:53 +00:00
Jakob Stoklund Olesen b159b5ff0d Remove the explicit MachineInstrBuilder(MI) constructor.
Use the version that also takes an MF reference instead.

It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.

Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.

llvm-svn: 170588
2012-12-19 21:31:56 +00:00
Patrik Hagglund f9934613e8 Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT.
Accordingly, add MVT::getVT.

llvm-svn: 170550
2012-12-19 15:19:11 +00:00
Patrik Hagglund 00e7a11904 Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.
llvm-svn: 170540
2012-12-19 12:33:30 +00:00
Patrik Hagglund 4e0f828686 Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs.

llvm-svn: 170538
2012-12-19 12:23:01 +00:00
Patrik Hagglund e09cac9a67 Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.

llvm-svn: 170537
2012-12-19 12:02:25 +00:00
Patrik Hagglund 3f1905199b Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.

llvm-svn: 170536
2012-12-19 11:53:21 +00:00
Patrik Hagglund bad545ccba Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.

llvm-svn: 170535
2012-12-19 11:48:16 +00:00
Patrik Hagglund 93060569ba Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.

llvm-svn: 170534
2012-12-19 11:42:00 +00:00
Patrik Hagglund f9eb168ef4 Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.

llvm-svn: 170532
2012-12-19 11:30:36 +00:00
Patrik Hagglund fd41b5b969 Change TargetLowering::getTypeToPromoteTo to take and return MVTs,
instead of EVTs.

llvm-svn: 170529
2012-12-19 11:21:04 +00:00
Patrik Hagglund ffd057a3e1 Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.
llvm-svn: 170524
2012-12-19 10:19:55 +00:00
Patrik Hagglund deee9003ed Change TargetLowering::getCondCodeAction to take an MVT, instead of
EVT.

llvm-svn: 170522
2012-12-19 10:09:26 +00:00
Patrik Hagglund d7cdcf8cb5 Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.
llvm-svn: 170510
2012-12-19 08:28:51 +00:00
Elena Demikhovsky 14a4af0e66 Optimized load + SIGN_EXTEND patterns in the X86 backend.
llvm-svn: 170506
2012-12-19 07:50:20 +00:00
Nadav Rotem 33360d8ae9 After reducing the size of an operation in the DAG we zero-extend the reduced
bitwidth op back to the original size. If we reduce ANDs then this can cause
an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits
are equal or smaller than the size of the reduced operation.

llvm-svn: 170505
2012-12-19 07:39:08 +00:00
Bill Wendling 3d7b0b8ac7 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
llvm-svn: 170502
2012-12-19 07:18:57 +00:00
Craig Topper 3f194c8f4f Remove more of 'else's after 'returns'. No functional change.
llvm-svn: 170497
2012-12-19 06:43:58 +00:00
Craig Topper 5dd8291cbe Remove a bunch of 'else's after 'returns'
llvm-svn: 170496
2012-12-19 06:39:17 +00:00
Craig Topper 63f5921776 Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition.
llvm-svn: 170495
2012-12-19 06:12:28 +00:00
Jakob Stoklund Olesen d742533dbc Use bidirectional bundle flags to simplify important functions.
The bundle_iterator::operator++ function now doesn't need to dig out the
basic block and check against end(). It can use the isBundledWithSucc()
flag to find the last bundled instruction safely.

Similarly, MachineInstr::isBundled() no longer needs to look at
iterators etc. It only has to look at flags.

llvm-svn: 170473
2012-12-18 23:21:49 +00:00
Jakob Stoklund Olesen 00f6c7754b Verify bundle flag consistency when setting them.
Now that the bundle flag aware APIs are all in place, it is possible to
continuously verify the flag consistency.

llvm-svn: 170465
2012-12-18 23:00:28 +00:00
Jakob Stoklund Olesen 29c277197e Verify bundle flags for consistency in MachineVerifier.
The new bidirectional bundle flags are redundant, so inadvertent bundle
tearing can be detected in the machine code verifier.

llvm-svn: 170463
2012-12-18 22:55:07 +00:00
Jakob Stoklund Olesen a33f504b3e Don't allow the automatically updated MI flags to be set directly.
The bundle-related MI flags need to be kept in sync with the neighboring
instructions. Don't allow the bulk flag-setting setFlags() function to
change them.

Also don't copy MI flags when cloning an instruction. The clone's bundle
flags will be set when it is explicitly inserted into a bundle.

llvm-svn: 170459
2012-12-18 21:36:05 +00:00
Jakob Stoklund Olesen 78eaf05fa7 Tighten up the splice() API for bundled instructions.
Remove the instr_iterator versions of the splice() functions. It doesn't
seem useful to be able to splice sequences of instructions that don't
consist of full bundles.

The normal splice functions that take MBB::iterator arguments are not
changed, and they can move whole bundles around without any problems.

llvm-svn: 170456
2012-12-18 20:59:41 +00:00
Andrew Trick ec2564818c MISched: add dependence to ExitSU to model live-out latency.
llvm-svn: 170454
2012-12-18 20:53:01 +00:00
Andrew Trick ef23569858 MISched: Cleanup, redundant statement.
llvm-svn: 170453
2012-12-18 20:52:58 +00:00
Andrew Trick d6d5ad3d7b MISched: Heuristics, compare latency more precisely. It matters more for some targets.
llvm-svn: 170452
2012-12-18 20:52:56 +00:00
Andrew Trick 44f54d97a4 MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to compute it.
llvm-svn: 170451
2012-12-18 20:52:54 +00:00
Andrew Trick 493b867b5d MISched: cleanup, use the proper iterator type.
llvm-svn: 170450
2012-12-18 20:52:52 +00:00
Andrew Trick ffb6168e85 MISched: minor improvement, initialize remaining resources before the first scheduling decision.
llvm-svn: 170449
2012-12-18 20:52:49 +00:00
Jakob Stoklund Olesen 422e07b091 Tighten the insert() API for bundled instructions.
The normal insert() function takes an MBB::iterator position, and
inserts a stand-alone MachineInstr as before.

The insert() function that takes an MBB::instr_iterator position can
insert instructions inside a bundle, and will now update the bundle
flags correctly when that happens.

When the insert position is between two bundles, it is unclear whether
the instruction should be appended to the previous bundle, prepended to
the next bundle, or stand on its own. The MBB::insert() function doesn't
bundle the instruction in that case, use the MIBundleBuilder class for
that.

llvm-svn: 170437
2012-12-18 17:54:53 +00:00
Hal Finkel 943f76d1b3 Check multiple register classes for inline asm tied registers
A register can be associated with several distinct register classes.
For example, on PPC, the floating point registers are each associated with
both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code
would fail when provided with a floating point register and an f64 operand
because it would happen to find the register in the F4RC class first and
return that. From the F4RC class, SDAG would extract f32 as the register
type and then assert because of the invalid implied conversion between
the f64 value and the f32 register.

Instead, search all register classes. If a register class containing the
the requested register has the requested type, then return that register
class. Otherwise, as before, return the first register class found that
contains the requested register.

llvm-svn: 170436
2012-12-18 17:50:58 +00:00
Jakob Stoklund Olesen ccfb5fb472 Tighten up the erase/remove API for bundled instructions.
Most code is oblivious to bundles and uses the MBB::iterator which only
visits whole bundles. MBB::erase() operates on whole bundles at a time
as before.

MBB::remove() now refuses to remove bundled instructions. It is not safe
to remove all instructions in a bundle without deleting them since there
is no way of returning pointers to all the removed instructions.

MBB::remove_instr() and MBB::erase_instr() will now update bundle flags
correctly, lifting individual instructions out of bundles while leaving
the remaining bundle intact.

The MachineInstr convenience functions are updated so

  eraseFromParent() erases a whole bundle as before
  eraseFromBundle() erases a single instruction, leaving the rest of its bundle.
  removeFromParent() refuses to operate on bundled instructions, and
  removeFromBundle() lifts a single instruction out of its bundle.

These functions will no longer accidentally split or coalesce bundles -
bundle flags are updated to preserve the existing bundling, and explicit
bundleWith* / unbundleFrom* functions should be used to change the
instruction bundling.

This API update is still a work in progress. I am going to update APIs
first so they maintain bundle flags automatically when possible. Then
I'll add stricter verification of the bundle flags.

llvm-svn: 170384
2012-12-17 23:55:38 +00:00
Patrik Hagglund c494d24a68 Revert/correct some FastISel changes in r170104 (EVT->MVT for
TargetLowering::getRegClassFor).

Some isSimple() guards were missing, or getSimpleVT() were hoisted too
far, resulting in asserts on valid LLVM assembly input.

llvm-svn: 170336
2012-12-17 14:30:06 +00:00
Craig Topper 588ceec0f7 Add debug prints for when optimizeLoadInstr folds a load.
llvm-svn: 170298
2012-12-17 03:56:00 +00:00
Dmitri Gribenko 2943ce80f3 Declare class DwarfDebug before use instead of relying on a forward declaration
from some other unrelated header.

Patch by Kai.

llvm-svn: 170284
2012-12-16 12:57:36 +00:00
Reed Kotler aee4d5d194 This patch is needed to make c++ exceptions work for mips16.
Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 

llvm-svn: 170279
2012-12-16 04:00:45 +00:00
Eric Christopher a2de826d29 To simplify some code move the unit emission into the holders.
Make emitDIE public accordingly. No functional change.

llvm-svn: 170258
2012-12-15 00:04:07 +00:00
Eric Christopher 16485a5164 Use begin and end label names from the section for info.
llvm-svn: 170257
2012-12-15 00:04:04 +00:00
Patrik Hagglund 55d6f47a37 Change TargetLowering::getLoadExtAction to take an MVT, instead of
EVT.

llvm-svn: 170183
2012-12-14 09:05:13 +00:00
Jakob Stoklund Olesen 7bb2f97a90 Use the new MI bundling API in MachineInstrBundle itself.
The new API is higher level than just manipulating the bundle flags
directly, and the setIsInsideBundle() function will disappear soon.

llvm-svn: 170159
2012-12-13 23:23:46 +00:00
David Blaikie 37fefc3f8d Debug Info: add support to mark member variables as artificial
This is the LLVM portion of r170154.

llvm-svn: 170156
2012-12-13 22:43:07 +00:00
Patrik Hagglund 13abe5ec3c Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.
llvm-svn: 170148
2012-12-13 20:42:43 +00:00
Patrik Hagglund 05394352c0 Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.

llvm-svn: 170140
2012-12-13 18:45:35 +00:00
Patrik Hagglund 5e6c361bc0 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.

llvm-svn: 170104
2012-12-13 06:34:11 +00:00
Eric Christopher 996b2b7ae6 Use default label name for a section in emitting abbreviation
section to help prep some code to be split about.

llvm-svn: 170088
2012-12-13 03:00:38 +00:00
Evan Cheng bf0baa9de7 Fix a bug in DAGCombiner::MatchBSwapHWord. Make sure the node has operands before referencing them. rdar://12868039
llvm-svn: 170078
2012-12-13 01:34:32 +00:00
Pedro Artigas 7212ee4534 Make the MCStreamer have a reset method and call that after finalization of the asm printer,
also changed MCContext to a single reset only method for simplicity as requested on the list

llvm-svn: 170041
2012-12-12 22:59:46 +00:00
Evan Cheng b7d3d03bf9 Fix a logic bug in inline expansion of memcpy / memset with an overlapping
load / store pair. It's not legal to use a wider load than the size of
the remaining bytes if it's the first pair of load / store.

llvm-svn: 170018
2012-12-12 20:43:23 +00:00
Evan Cheng 962711ee71 Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?

This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.

llvm-svn: 169959
2012-12-12 02:34:41 +00:00
Evan Cheng c3d1aca657 - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.

llvm-svn: 169954
2012-12-12 01:32:07 +00:00
Manman Ren 82751a105c DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertion
rdar://12838504

llvm-svn: 169951
2012-12-12 01:13:50 +00:00
Evan Cheng 04e5518783 Avoid using lossy load / stores for memcpy / memset expansion. e.g.
f64 load / store on non-SSE2 x86 targets.

llvm-svn: 169944
2012-12-12 00:42:09 +00:00
Evan Cheng eb54240dc2 Replace TargetLowering::isIntImmLegal() with
ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined
term for something like integer immediate materialization. It is always possible
to materialize an integer immediate. Whether to use it for memcpy expansion is
more a "cost" conceern.

llvm-svn: 169929
2012-12-11 23:26:14 +00:00
Eric Christopher d692c1dbb7 Update some comments.
llvm-svn: 169907
2012-12-11 19:42:09 +00:00
Joel Jones 24e440d045 Add comment for load folding
llvm-svn: 169880
2012-12-11 16:10:25 +00:00
Patrik Hagglund e98b7a0389 Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
llvm-svn: 169854
2012-12-11 11:14:33 +00:00
Patrik Hagglund b31465b09b Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs.

llvm-svn: 169851
2012-12-11 10:24:48 +00:00
Patrik Hagglund ad432a8e70 Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.

Accordingly, add bitsLT (and similar) to MVT.

llvm-svn: 169850
2012-12-11 10:20:51 +00:00
Patrik Hagglund d34337495e Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,
from EVT.

llvm-svn: 169849
2012-12-11 10:16:19 +00:00
Patrik Hagglund 03e9628cfa Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of
EVTs.

llvm-svn: 169848
2012-12-11 10:09:23 +00:00
Patrik Hagglund c50489e203 Change TargetLowering::TransformToType to contain MVTs, instead of
EVTs.

llvm-svn: 169847
2012-12-11 10:05:04 +00:00
Patrik Hagglund 8d2e7cf561 Change TargetLowering::findRepresentativeClass to take an MVT, instead
of EVT.

llvm-svn: 169845
2012-12-11 09:57:18 +00:00