Commit Graph

223983 Commits

Author SHA1 Message Date
Rafael Espindola 3a4d0a7c17 Remove the old ELF linker.
I think it is clear by now that the new linker is viable.

llvm-svn: 262158
2016-02-28 00:10:58 +00:00
Xinliang David Li 985ff20a9c [PGO] Remove redundant counter copies for avail_extern functions.
Differential Revision: http://reviews.llvm.org/D17654

llvm-svn: 262157
2016-02-27 23:11:30 +00:00
Todd Fiala 6993abff14 Revert "Fix bug with register values byte order in expression evaluation."
This reverts commit r262041, which caused asserts starting yesterday on the OS X testbot.

See details in:
https://llvm.org/bugs/show_bug.cgi?id=26758

llvm-svn: 262156
2016-02-27 22:48:50 +00:00
Rui Ueyama 40c589048e ELF: Remove relSize function from ICF.cpp. NFC.
llvm-svn: 262155
2016-02-27 20:29:45 +00:00
Duncan P. N. Exon Smith ebcce78f65 CodeGen: Remove an iterator => pointer conversion, NFC
Part of PR26753.

llvm-svn: 262154
2016-02-27 20:27:44 +00:00
Matt Arsenault 3a61985b2f AMDGPU: More bits of frame index are known to be zero
The maximum private allocation for the whole GPU is 4G,
so the maximum possible index for a single workitem is the
maximum size divided by the smallest granularity for a dispatch.

This increases the number of known zero high bits, which
enables more offset folding. The maximum private size per
workitem with this is 128M but may be smaller still.

llvm-svn: 262153
2016-02-27 20:26:57 +00:00
Duncan P. N. Exon Smith d6ebd07b8d CodeGen: Use MachineInstr& in InlineSpiller::rematerializeFor()
InlineSpiller::rematerializeFor() never uses its parameter as an
iterator, so take it by reference instead.  This removes an implicit
conversion from MachineBasicBlock::iterator to MachineInstr*.

llvm-svn: 262152
2016-02-27 20:23:14 +00:00
Duncan P. N. Exon Smith be8f8c4478 CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC
These parameters aren't expected to be null, so take them by reference.

llvm-svn: 262151
2016-02-27 20:14:29 +00:00
Duncan P. N. Exon Smith fd8cc23220 CodeGen: Change MachineInstr to use MachineInstr&, NFC
Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null.  Slowly inching
toward being able to fix PR26753.

llvm-svn: 262149
2016-02-27 20:01:33 +00:00
Matt Arsenault 982224cfb8 DAGCombiner: Don't unnecessarily swap operands in ReassociateOps
In the case where op = add, y = base_ptr, and x = offset, this
transform:

(op y, (op x, c1)) -> (op (op x, y), c1)

breaks the canonical form of add by putting the base pointer in the
second operand and the offset in the first.

This fix is important for the R600 target, because for some address
spaces the base pointer and the offset are stored in separate register
classes. The old pattern caused the ISel code for matching addressing
modes to put the base pointer and offset in the wrong register classes,
which required no-trivial code transformations to fix.

llvm-svn: 262148
2016-02-27 19:57:45 +00:00
Filipe Cabecinhas b7692bc3e9 [UBSan] Fix isDerivedFromAtOffset on iOS ARM64
Summary:
iOS on ARM64 doesn't unique RTTI.
Ref: clang's iOS64CXXABI::shouldRTTIBeUnique()

Due to this, pointer-equality will not necessarily work in this
architecture, across dylib boundaries.

dynamic_cast<>() will (as expected) still work, since Apple ships with
one prepared for this, but we can't rely on the type names being
pointer-equal.

I've limited the expensive strcmp check to the specific architecture
which needs it.

Example which triggers this bug:

lib.h:
  struct X {
    virtual ~X() {}
  };
  X *libCall();

lib.mm:
  X *libCall() {
    return new X;
  }

prog.mm:
  int main() {
    X *px = libCall();
    delete px;
  }

Expected output: Nothing
Actual output:
<unknown>: runtime error: member call on address 0x00017001ef50 which does not point to an object of type 'X'
0x00017001ef50: note: object is of type 'X'
 00 00 00 00  60 00 0f 00 01 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00
              ^~~~~~~~~~~~~~~~~~~~~~~
              vptr for ‘X’

Reviewers: kubabrecka, samsonov, eugenis, rsmith

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D11502

llvm-svn: 262147
2016-02-27 19:57:44 +00:00
Duncan P. N. Exon Smith d3a7467221 CodeGen: Use MachineInstr& in HashMachineInstr, NFC
Also update HashEndOfMBB to take MachineBasicBlock&.

llvm-svn: 262146
2016-02-27 19:48:01 +00:00
Duncan P. N. Exon Smith 5e6e8c7a0a CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC
Take parameters as MachineInstr& instead of MachineInstr* in
AntiDepBreaker API, since these are required to be non-null.  No
functionality change intended.  Looking toward PR26753.

llvm-svn: 262145
2016-02-27 19:33:37 +00:00
Duncan P. N. Exon Smith bd529fbb4a CodeGen: Assert valid MI in AntiDepBreaker::UpdateDbgValue
This already assumes a valid MI, since it dereferences the MI in an
assertion before checking for null.  At an explicit assert.

llvm-svn: 262144
2016-02-27 19:23:34 +00:00
Duncan P. N. Exon Smith 1f6624ae34 AArch64: Use MachineInstr& in guaranteesZeroRegInBlock(), NFC
llvm-svn: 262143
2016-02-27 19:12:54 +00:00
Duncan P. N. Exon Smith 5702287809 CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*.  In DFAPacketizer::endPacket(), take
MachineBasicBlock::iterator.  Besides cleaning up the API, this is in
search of PR26753.

llvm-svn: 262142
2016-02-27 19:09:00 +00:00
Duncan P. N. Exon Smith f9ab416d70 WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null.  Besides
being a nice cleanup, this is tacking toward a fix for PR26753.

llvm-svn: 262141
2016-02-27 17:05:33 +00:00
JF Bastien 13d3b9b777 WebAssembly: fix build
It was broken by the work for PR26753.

llvm-svn: 262140
2016-02-27 16:38:23 +00:00
Renato Golin 9a5419ecf7 Revert "[sancov] do not instrument nodes that are full pre-dominators"
This reverts commit r262103, as it broke all ARM and AArch64 bots.

llvm-svn: 262139
2016-02-27 14:19:19 +00:00
Alexander Kornienko 70f97c9bfb Workaround doxygen bug https://bugzilla.gnome.org/show_bug.cgi?id=506243
llvm-svn: 262138
2016-02-27 14:02:08 +00:00
Simon Pilgrim 9e10b1655c Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI.
llvm-svn: 262137
2016-02-27 13:26:58 +00:00
Aaron Ballman b1be8f6928 Correcting indentation for an RST code block.
llvm-svn: 262136
2016-02-27 13:13:16 +00:00
Chris Dewhurst 0a2c033e2d Addition of tests to previous check-in. Tests for coprocessor register usage in Sparc.
Previous check-in message was:

The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.

Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.

llvm-svn: 262135
2016-02-27 12:52:26 +00:00
Simon Pilgrim 83e76327e8 [X86][AVX] vpermilvar.pd mask element indices only use bit1
llvm-svn: 262134
2016-02-27 12:51:46 +00:00
Chris Dewhurst 053826af69 The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.

Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.

llvm-svn: 262133
2016-02-27 12:49:59 +00:00
Simon Pilgrim a9a7bf68ee [X86][AVX] Added AVX1 target shuffle combine tests
llvm-svn: 262132
2016-02-27 12:33:08 +00:00
Simon Pilgrim 3b42ca0760 Strip trailing whitespace. NFCI.
llvm-svn: 262131
2016-02-27 11:49:16 +00:00
Chandler Carruth 30811a4dde [PM] Loosen the regex for the proxy template name even further to cope
with 'class' keywords in the template arguments and other silliness.

llvm-svn: 262130
2016-02-27 11:07:16 +00:00
Chandler Carruth 08a25ce0e3 [PM] Use a boring regex instead of explicitly naming the analysis
manager as some compilers print the typedef name and others print the
"canonical" name of the underlying class template.

This isn't really an important artifact of the test anyways so it seems
fine to just loosen the test assertions here.

llvm-svn: 262129
2016-02-27 10:48:14 +00:00
Chandler Carruth afcec4c55a [PM] Provide explicit instantiation declarations and definitions for the
PassManager and AnalysisManager template specializations as well.

llvm-svn: 262128
2016-02-27 10:45:35 +00:00
Chandler Carruth 2a54094d40 [PM] Provide two templates for the two directionalities of analysis
manager proxies and use those rather than repeating their definition
four times.

There are real differences between the two directions: outer AMs are
const and don't need to have invalidation tracked. But every proxy in
a particular direction is identical except for the analysis manager type
and the IR unit they proxy into. This makes them prime candidates for
nice templates.

I've started introducing explicit template instantiation declarations
and definitions as well because we really shouldn't be emitting all this
everywhere. I'm going to go back and add the same for the other
templates like this in a follow-up patch.

I've left the analysis manager as an opaque type rather than using two
IR units and requiring it to be an AnalysisManager template
specialization. I think its important that users retain the ability to
provide their own custom analysis management layer and provided it has
the appropriate API everything should Just Work.

llvm-svn: 262127
2016-02-27 10:38:10 +00:00
Matt Arsenault 39edcd0e1d AMDGPU: Add builtins for recently added intrinsics
llvm-svn: 262126
2016-02-27 09:54:43 +00:00
Matt Arsenault 360d244d5b DAGCombiner: Relax sqrt NaN folding check
This is OK for +0 since compares to +/-0 give the same result.

llvm-svn: 262125
2016-02-27 09:38:05 +00:00
Matt Arsenault 5e020b2628 AMDGPU: Fix broken/confusing predefined macro
amdgcn should not be defining __R600__

llvm-svn: 262124
2016-02-27 09:06:26 +00:00
Matt Arsenault b015d623d6 AMDGPU: Fix inconsistent register name for flat_scratch
llvm-svn: 262123
2016-02-27 09:06:22 +00:00
Matt Arsenault 2d9339890f Add __builtin_canonicalize
llvm-svn: 262122
2016-02-27 09:06:18 +00:00
Matt Arsenault 9d82ee7526 AMDGPU: Split vi-insts subtarget feature
This will be more useful for marking builtins acceptable for which
subtargets.

llvm-svn: 262121
2016-02-27 08:53:55 +00:00
Matt Arsenault 274d34e725 AMDGPU: Add s_sleep intrinsic
llvm-svn: 262120
2016-02-27 08:53:52 +00:00
Matt Arsenault 61738cbcb6 AMDGPU: Implement readcyclecounter
This matches the behavior of the HSAIL clock instruction.
s_realmemtime is used if the subtarget supports it, and falls
back to s_memtime if not.

Also introduces new intrinsics for each of s_memtime / s_memrealtime.

llvm-svn: 262119
2016-02-27 08:53:46 +00:00
Duncan P. N. Exon Smith 353c84e747 CodeGen: Avoid implicit conversion in MachineInstrBuilder, NFC
Avoid another implicit conversion from MachineInstrBundleIterator to
MachineInstr*, this time in MachineInstrBuilder.h (this is in pursuit of
PR26753).

llvm-svn: 262118
2016-02-27 07:00:35 +00:00
Tobias Grosser 4fb9e51664 ScopInfo: Drop some debug statements
This debug output distracts from the -debug-only=polly-scops output. As it is
rather verbose and only really needed for debugging the domain construction
I drop this output. The domain construction is meanwhile stable enough to
not require regular debugging.

llvm-svn: 262117
2016-02-27 06:59:30 +00:00
Duncan P. N. Exon Smith b6bb889dfd CodeGen: Remove implicit iterator to pointer conversions, NFC
Remove a couple of implicit conversions from MachineInstrBundleIterator
to MachineInstr*.

llvm-svn: 262116
2016-02-27 06:51:00 +00:00
Duncan P. N. Exon Smith 3ac9cc6156 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals.  The MachineInstrs here are
never null, so this cleans up the API a bit.  It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).

At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.

llvm-svn: 262115
2016-02-27 06:40:41 +00:00
Tobias Grosser 0bed1eab39 LoopGenerators: Expose some parts of the parallel loop generator
Some of this functionality is useful beyond the generation of a normal OpenMP
loop.

llvm-svn: 262114
2016-02-27 06:24:58 +00:00
Tobias Grosser abafafe07c ScopInfo: Add function to invalidate ScopArrayInfo object
In case the underlying basepointer of a ScopArrayInfo object is moved to another
module while the scop is still processed is it necessary to free dependent
ScopArrayInfo objects as they might otherwise be looked accidentally when a
new llvm basepointer value is reassigned the very same memory location as the
llvm value that has been moved earlier.

This function is not yet used in Polly itself, but is useful for external users.

llvm-svn: 262113
2016-02-27 06:04:40 +00:00
Sean Silva ea399f0242 [instrprof] Use __{start,stop}_SECNAME on PS4 too.
Summary:
The PS4 linker seems to handle this fine.

Hi David, it seems that indeed most ELF linkers support
__{start,stop}_SECNAME, as our proprietary linker does as well.

This follows the pattern of r250679 w.r.t. the testing.

Maggie, Phillip, Paul: I've tested this with the PS4 SDK 3.5 toolchain
prerelease and it seems to work fine.

Reviewers: davidxl

Subscribers: probinson, phillip.power, MaggieYi

Differential Revision: http://reviews.llvm.org/D17672

llvm-svn: 262112
2016-02-27 06:01:26 +00:00
Mike Aizatsky 9056284912 [sancov] properly initializing pass.
llvm-svn: 262111
2016-02-27 05:50:40 +00:00
Kostya Serebryany 3c767db3c5 [libFuzzer] don't emit callbacks to sanitizer run-time in -fsanitize-coverage=trace-pc mode; update libFuzzer doc for previous commit
llvm-svn: 262110
2016-02-27 05:45:12 +00:00
Philip Reames 70b391864d Suppress an uncovered switch warning [NFC]
llvm-svn: 262109
2016-02-27 05:18:30 +00:00
Chandler Carruth ad8cb382fa [LICM] Teach LICM how to handle cases where the alias set tracker was
merged into a loop that was subsequently unrolled (or otherwise nuked).

In this case it can't merge in the ASTs for any remaining nested loops,
it needs to re-add their instructions dircetly.

The fix is very isolated, but I've pulled the code for merging blocks
into the AST into a single place in the process. The only behavior
change is in the case which would have crashed before.

This fixes a crash reported by Mikael Holmen on the list after r261316
restored much of the loop pass pipelining and allowed us to actually do
this kind of nested transformation sequenc. I've taken that test case
and further reduced it into the somewhat twisty maze of loops in the
included test case. This does in fact trigger the bug even in this
reduced form.

llvm-svn: 262108
2016-02-27 04:34:07 +00:00