Evan Cheng
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
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llvm-svn: 28459
2006-05-25 00:24:28 +00:00
Evan Cheng
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
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non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
Owen Anderson
88812b5c0a
Make all of the TargetMachine subclasses use the new string TargetData methods.
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This is part of the on-going work on PR 761.
llvm-svn: 28414
2006-05-20 00:24:56 +00:00
Evan Cheng
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Evan Cheng
dcec882286
Remove PointerType from class Target
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llvm-svn: 28368
2006-05-17 21:20:27 +00:00
Andrew Lenharth
1dc9ec5874
Move this code to a common place
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llvm-svn: 28329
2006-05-16 17:42:15 +00:00
Chris Lattner
768bc20b74
Fix build breakage :(
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llvm-svn: 28267
2006-05-12 23:26:11 +00:00
Chris Lattner
d63ec521c5
Actually override the right method. :)
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Bug identified by coverity.
llvm-svn: 28259
2006-05-12 18:19:25 +00:00
Owen Anderson
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
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TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
Chris Lattner
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
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llvm-svn: 28184
2006-05-09 04:59:56 +00:00
Chris Lattner
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
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llvm-svn: 28104
2006-05-04 18:05:43 +00:00
Chris Lattner
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
fef7a2d0f5
There shalt be only one "immediate" operand type!
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llvm-svn: 28099
2006-05-04 17:21:20 +00:00
Chris Lattner
940cc978ef
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
Chris Lattner
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
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llvm-svn: 28091
2006-05-04 00:44:25 +00:00
Owen Anderson
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Nate Begeman
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
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basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
Nate Begeman
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Nate Begeman
3f9c17906f
Disable switch lowering for targets based on the selection dag isel,
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letting the code generator handle them directly.
llvm-svn: 27539
2006-04-08 19:46:55 +00:00
Jim Laskey
2d7298c362
Foundation for call frame information.
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llvm-svn: 27491
2006-04-07 16:34:46 +00:00
Jim Laskey
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
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llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Jim Laskey
fa53b276d0
Translate llvm target registers to dwarf register numbers properly.
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llvm-svn: 27180
2006-03-27 20:18:45 +00:00
Chris Lattner
5d70a7c4a5
#include Intrinsics.h into all dag isels
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llvm-svn: 27109
2006-03-25 06:47:10 +00:00
Jim Laskey
f0729b4067
Add dwarf register numbering to register data.
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llvm-svn: 27081
2006-03-24 21:15:58 +00:00
Jim Laskey
3c43609f1f
Add support to locate local variables in frames (early version.)
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llvm-svn: 26994
2006-03-23 18:12:57 +00:00
Chris Lattner
6f95ab7abb
Eliminate IntrinsicLowering from TargetMachine.
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Make the CBE and V9 backends create their own, since they're the only ones that use it.
llvm-svn: 26974
2006-03-23 05:43:16 +00:00
Nate Begeman
bb01d4f272
Remove BRTWOWAY*
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Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
Evan Cheng
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
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llvm-svn: 26742
2006-03-13 23:20:37 +00:00
Chris Lattner
e363fdf318
Add support for 'special' llvm globals like debug info and static ctors/dtors.
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llvm-svn: 26628
2006-03-09 06:14:35 +00:00
Duraid Madina
5005b01c20
doo de doo
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llvm-svn: 26614
2006-03-08 06:18:46 +00:00
Chris Lattner
9c7f50376a
Copysign needs to be expanded everywhere. Note that Alpha and IA64 should
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implement copysign as a native op if they have it.
llvm-svn: 26541
2006-03-05 05:08:37 +00:00
Duraid Madina
36a2ee299e
distinguish between objects and register names, now we can have stuff
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with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
Chris Lattner
62c3484e43
Switch targets over to using SelectionDAG::getCALLSEQ_START to create
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CALLSEQ_START nodes.
llvm-svn: 26143
2006-02-13 09:00:43 +00:00
Duraid Madina
4698e4f5fe
fix storing booleans (grawp missed this one)
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llvm-svn: 26120
2006-02-11 07:33:17 +00:00
Duraid Madina
0010a92375
now short immediates will get matched (previously constants were all
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triggering movl 64bit imm fat instructions)
llvm-svn: 26119
2006-02-11 07:32:15 +00:00
Evan Cheng
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
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llvm-svn: 26085
2006-02-09 07:17:49 +00:00
Evan Cheng
6dc90ca172
Change Select() from
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SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
Evan Cheng
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
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llvm-svn: 25997
2006-02-05 06:46:41 +00:00
Nate Begeman
7e7f439f85
Fix some of the stuff in the PPC README file, and clean up legalization
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of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.
llvm-svn: 25875
2006-02-01 07:19:44 +00:00
Evan Cheng
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
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llvm-svn: 25855
2006-01-31 22:23:14 +00:00
Chris Lattner
61c9a8e942
Targets all now request ConstantFP to be legalized into TargetConstantFP.
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'fpimm' in .td files is now TargetConstantFP.
llvm-svn: 25771
2006-01-29 06:26:08 +00:00
Nate Begeman
595ec734fc
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
Chris Lattner
b292de6703
Remove some dead code
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llvm-svn: 25719
2006-01-28 00:02:51 +00:00
Nate Begeman
8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Chris Lattner
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
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llvm-svn: 25674
2006-01-27 01:46:15 +00:00
Duraid Madina
0ebb0b1c5c
fix stack corruption! Previously, 16-byte whole-FP-register stores were
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being treated as needing only 8 bytes (though they were 16 byte aligned.)
This should fix a bunch of tests - anyone have any comments, though?
- in Target.td , SpillSize and SpillAlignment seem dead - is this what
Size and Alignment do now?
- in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
DeclaredSpillAlignment seem dead.
- there are a bunch of comments here and there that don't clearly
distinguish between 'size' and 'spillsize' etc. hmm.
llvm-svn: 25644
2006-01-26 09:45:03 +00:00
Duraid Madina
c090ac13bd
some hoovering
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llvm-svn: 25643
2006-01-26 09:08:31 +00:00
Evan Cheng
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
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llvm-svn: 25607
2006-01-25 18:52:42 +00:00
Nate Begeman
e74795cd70
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
1092a02619
Default scheduling preference is SchedulingForLatency.
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llvm-svn: 25603
2006-01-25 09:15:54 +00:00