dce01792f2
Add Thumb tests for the ARMv8 FP instructions that I recently added.
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Also, fix the namespace for two instructions that I missed previously.
llvm-svn: 186572
2013-07-18 10:20:25 +00:00
0f12aa2b0f
Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
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llvm-svn: 185929
2013-07-09 11:26:18 +00:00
3b693c42b5
Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
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llvm-svn: 185926
2013-07-09 11:03:21 +00:00
2d0175e8fb
Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
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llvm-svn: 185922
2013-07-09 09:59:04 +00:00
2efaa733a2
Add MC support for the v8fp instructions: vmaxnm and vminnm.
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llvm-svn: 185767
2013-07-06 20:50:18 +00:00
cc4ff9e907
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
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This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
llvm-svn: 185642
2013-07-04 14:57:20 +00:00
39f7488294
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
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llvm-svn: 185620
2013-07-04 10:04:08 +00:00
1c7be576c5
This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.
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llvm-svn: 183733
2013-06-11 09:39:51 +00:00
2773f1deb4
ARM sched model: Add divsion, loads, branches, vfp cvt
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Add some generic SchedWrites and assign resources for Swift and Cortex A9.
Reapply of r183257. (Removed empty InstRW for division on swift)
llvm-svn: 183319
2013-06-05 16:06:11 +00:00
2a70c69d31
Revert series of sched model patches until I figure out what is going on.
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llvm-svn: 183273
2013-06-04 22:35:17 +00:00
d5b9794a53
ARM sched model: Add divsion, loads, branches, vfp cvt
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Add some generic SchedWrites and assign resources for Swift and Cortex A9.
llvm-svn: 183257
2013-06-04 22:15:46 +00:00
4173e29a98
ARM: add fstmx and fldmx instructions for assembly
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These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
llvm-svn: 183011
2013-05-31 15:55:51 +00:00
e8a549cd92
Add LLVM support for Swift.
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llvm-svn: 164899
2012-09-29 21:43:49 +00:00
1e28826abe
fp16-to-fp32 conversion instructions are available in Thumb mode as well.
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Make sure the generic pattern is used.
llvm-svn: 162170
2012-08-18 13:08:43 +00:00
eec6bc6270
Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029
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llvm-svn: 161962
2012-08-15 17:44:53 +00:00
c6d945b11a
The names of VFP variants of half-to-float conversion instructions were
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reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.
llvm-svn: 161907
2012-08-14 23:36:01 +00:00
1dc44dcedd
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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llvm-svn: 159989
2012-07-10 12:51:09 +00:00
aeed158f75
Revert r159938 (and r159945) to appease the buildbots.
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llvm-svn: 159960
2012-07-09 20:43:34 +00:00
c9e1c94fae
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
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llvm-svn: 159938
2012-07-09 16:41:33 +00:00
90b2a4cbad
Add a missing llvm.fma -> VFNMS pattern to the ARM backend.
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llvm-svn: 158902
2012-06-21 06:10:00 +00:00
ea001225c1
Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
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<rdar://problem/11325085>.
llvm-svn: 155724
2012-04-27 18:51:24 +00:00
671ad2a572
Tidy up. 80 columns, whitespace, et. al.
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llvm-svn: 155399
2012-04-23 22:04:10 +00:00
9cc324d31a
ARM some VFP tblgen'erated two-operand aliases.
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llvm-svn: 155178
2012-04-20 00:15:00 +00:00
5efc442290
Add more fused mul+add/sub patterns. rdar://10139676
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llvm-svn: 154484
2012-04-11 06:59:47 +00:00
48346c1cd9
Clean up ARM fused multiply + add/sub support some more: rename some isel
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predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?
rdar://10139676
llvm-svn: 154480
2012-04-11 05:33:07 +00:00
67a09fc397
Match (fneg (fma) to vfnma. rdar://10139676
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llvm-svn: 154469
2012-04-11 01:21:25 +00:00
d0007f3c83
Handle llvm.fma.* intrinsics. rdar://10914096
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llvm-svn: 154439
2012-04-10 21:40:28 +00:00
db7db7d3a3
ARM divided syntax fmrx/fmxr mnemonics.
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llvm-svn: 152946
2012-03-16 21:06:13 +00:00
24d90e2ddc
ARM vmrs system registers mvfr0 and mvfr1 handling.
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rdar://11058464
llvm-svn: 152881
2012-03-16 00:27:18 +00:00
d28888dd77
ARM case-insensitive checking for APSR_nzcv.
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rdar://11056591
llvm-svn: 152846
2012-03-15 21:34:14 +00:00
d74560b170
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
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rdar://11056647
llvm-svn: 152834
2012-03-15 20:48:18 +00:00
327d2f9da5
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
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llvm-svn: 152814
2012-03-15 17:50:29 +00:00
718cfbe05a
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
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The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
llvm-svn: 152076
2012-03-06 00:19:55 +00:00
8dc347fc27
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
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rdar://10988114
llvm-svn: 152068
2012-03-05 23:16:31 +00:00
957a6583f1
updated patch for the ARM fused multiply add/sub
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In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.
Patch by Ana Pazos <apazos@codeaurora.org>
llvm-svn: 152036
2012-03-05 17:39:52 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
5482b9f535
Add fused multiple+add instructions from VFPv4.
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Patch by Ana Pazos!
llvm-svn: 148658
2012-01-22 12:07:33 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
b65dd04923
Remove some bogus comments.
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llvm-svn: 147169
2011-12-22 19:45:01 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
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llvm-svn: 147158
2011-12-22 19:20:45 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
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llvm-svn: 147104
2011-12-21 23:24:15 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
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llvm-svn: 146892
2011-12-19 19:43:50 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
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llvm-svn: 146887
2011-12-19 19:02:41 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
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llvm-svn: 146514
2011-12-13 20:40:37 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
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llvm-svn: 146507
2011-12-13 20:08:32 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146296
2011-12-09 23:34:09 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
9a6ba3c94e
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Joey Gouly