Commit Graph

78274 Commits

Author SHA1 Message Date
Eli Friedman c1870b2633 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
llvm-svn: 145553
2011-12-01 01:43:47 +00:00
Jim Grosbach 8eeb353071 Replace an assert() with an actual diagnostic.
llvm-svn: 145535
2011-11-30 23:16:25 +00:00
Kostya Serebryany dc436f95d2 make asan work at -O0, llvm part. Patch by glider@google.com
llvm-svn: 145530
2011-11-30 22:19:26 +00:00
Jan Sjödin 9430e284a9 Support for encoding all FMA4 instructions and tablegen patterns for all
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
2011-11-30 22:09:42 +00:00
Eli Friedman 6cff9df298 Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
<rdar://problem/10497732>.

llvm-svn: 145523
2011-11-30 21:54:15 +00:00
Bill Wendling ad8b58b2ac More cleanups. No content change.
llvm-svn: 145522
2011-11-30 21:52:43 +00:00
Bill Wendling b6c2220600 Minor cleanup. No content change.
llvm-svn: 145521
2011-11-30 21:43:43 +00:00
Bob Wilson a0c69014f8 Remove the install-clang-c makefile target.
When I did this before it broke a buildbot that was testing that target, but
we've removed that buildbot now.

llvm-svn: 145519
2011-11-30 21:06:12 +00:00
Bill Wendling 3eb84cc75b Remove an XXX which hasn't been fixed yet. It's too late now.
llvm-svn: 145518
2011-11-30 20:53:52 +00:00
Matt Beaumont-Gay 23c30b90e3 Remove unused variable
llvm-svn: 145517
2011-11-30 19:53:11 +00:00
Jim Grosbach 7d8517b1d4 Add some tests for all-lanes VLD1 parsing.
llvm-svn: 145512
2011-11-30 19:37:38 +00:00
Jim Grosbach a68c9a847e ARM parsing for VLD1 all lanes, with writeback.
llvm-svn: 145510
2011-11-30 19:35:44 +00:00
Chad Rosier 738da252ab Add a few functions to TargetLibraryInfo.
llvm-svn: 145508
2011-11-30 19:19:00 +00:00
Jim Grosbach 3ecf976ca9 ARM parsing for VLD1 two register all lanes, no writeback.
llvm-svn: 145504
2011-11-30 18:21:25 +00:00
Nadav Rotem 0a1801015c Add test arch to make it pass on non x86 targets
llvm-svn: 145498
2011-11-30 17:34:28 +00:00
Benjamin Kramer 5feb3dab79 X86: Turns out bulldozer also supports sse42 and lzcnt.
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

llvm-svn: 145494
2011-11-30 15:48:16 +00:00
Benjamin Kramer 981f32327d X86: Add subtargets for AMD's bulldozer.
llvm-svn: 145493
2011-11-30 15:27:46 +00:00
Nadav Rotem 66427bcce9 Add a tripple to the test
llvm-svn: 145489
2011-11-30 11:20:56 +00:00
Nadav Rotem 96923cc2bb X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
llvm-svn: 145488
2011-11-30 10:13:37 +00:00
Craig Topper c4977ba413 Add instruction selection support for AVX2 horizontal add/sub instructions.
llvm-svn: 145487
2011-11-30 09:10:50 +00:00
Duncan Sands e9adf5c860 Mention that -O4 does result in more optimization when used with
-fplugin-arg-dragonegg-enable-gcc-optzns, though it usually isn't
a win.

llvm-svn: 145486
2011-11-30 08:46:05 +00:00
Craig Topper 0a672eaf9e Merge VPERM2F128/VPERM2I128 ISD node types.
llvm-svn: 145485
2011-11-30 07:47:51 +00:00
Andrew Trick 613c67e475 Better test case found in duplicate PR10570.
llvm-svn: 145484
2011-11-30 06:26:42 +00:00
Craig Topper bafd224c8b Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
llvm-svn: 145483
2011-11-30 06:25:25 +00:00
Andrew Trick ceafa2c746 LSR: handle the expansion of phi operands that use postinc forms of the IV.
Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.

llvm-svn: 145482
2011-11-30 06:07:54 +00:00
Chad Rosier 385d9f6c24 Whitespace.
llvm-svn: 145470
2011-11-30 01:59:59 +00:00
Chad Rosier abba0947db Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
change intended.

llvm-svn: 145468
2011-11-30 01:51:49 +00:00
Jim Grosbach f09b1c46cf llvm_unreachable() is not for user diagnostics....
llvm-svn: 145465
2011-11-30 01:15:55 +00:00
Jim Grosbach cd6f5e757c ARM parsing aliases for VLD1 single register all lanes.
llvm-svn: 145464
2011-11-30 01:09:44 +00:00
Chad Rosier 82e1bd8e94 Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

llvm-svn: 145460
2011-11-29 23:57:10 +00:00
Jim Grosbach 182b6a077e Tidy up a bit.
llvm-svn: 145458
2011-11-29 23:51:09 +00:00
Jim Grosbach ae672f8118 Add comment.
llvm-svn: 145456
2011-11-29 23:33:40 +00:00
Jim Grosbach e1154eef0b ARM parsing aliases for data-size suffices on VST1.
llvm-svn: 145454
2011-11-29 23:21:31 +00:00
Jakob Stoklund Olesen f50d2eafdb FileCheckize.
llvm-svn: 145452
2011-11-29 23:09:16 +00:00
Akira Hatanaka dc25f9f38a Change names for MIPS "generic" processors defined in Mips.td to match what GNU
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451
2011-11-29 23:08:41 +00:00
Jim Grosbach 5ee209ce3a ARM assembly parsing and encoding for four-register VST1.
llvm-svn: 145450
2011-11-29 22:58:48 +00:00
Daniel Dunbar 8d5cc33ad8 llvm-config: Replace with C++ version (was llvm-config-2).
- Reapply of r144300, with lots of fixes/migration easement in between.

llvm-svn: 145449
2011-11-29 22:56:31 +00:00
Evan Cheng 648e48d02e Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
llvm-svn: 145448
2011-11-29 22:48:34 +00:00
Jim Grosbach 2a9c43649a Enable some VST1 tests and add a few more.
llvm-svn: 145443
2011-11-29 22:40:32 +00:00
Jim Grosbach 98d032fd67 ARM assembly parsing and encoding for three-register VST1.
llvm-svn: 145442
2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen bde32d36bb Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
2011-11-29 22:27:25 +00:00
Stepan Dyatkovskiy 31798ef3c0 Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop.
llvm-svn: 145432
2011-11-29 20:34:39 +00:00
Eric Christopher b2d03a6d00 Update the docs for some of the test-suite configure changes and
be more clear about what to do and how to do it.

llvm-svn: 145426
2011-11-29 19:40:56 +00:00
Chad Rosier 46addb9e07 If fast-isel fails, remove dead instructions generated during the failed
attempt.  

llvm-svn: 145425
2011-11-29 19:40:47 +00:00
Rafael Espindola b61cc44265 grammar.
llvm-svn: 145423
2011-11-29 19:38:09 +00:00
Andrew Trick 312b97c267 comment.
llvm-svn: 145422
2011-11-29 19:33:49 +00:00
Daniel Dunbar 539d0a8a09 build/CMake: Finish removal of add_llvm_library_dependencies.
llvm-svn: 145420
2011-11-29 19:25:30 +00:00
Benjamin Kramer 098c1d9680 Add a link to Bill's blog post.
llvm-svn: 145419
2011-11-29 19:24:11 +00:00
Rafael Espindola 866a22aba7 Release notes for segmented stacks.
Patch by Sanjoy Das.

llvm-svn: 145416
2011-11-29 19:08:23 +00:00
Duncan Sands ca6f8ddbf8 Fix a theoretical problem (not seen in the wild): if different instances of a
weak variable are compiled by different compilers, such as GCC and LLVM, while
LLVM may increase the alignment to the preferred alignment there is no reason to
think that GCC will use anything more than the ABI alignment.  Since it is the
GCC version that might end up in the final program (as the linkage is weak), it
is wrong to increase the alignment of loads from the global up to the preferred
alignment as the alignment might only be the ABI alignment.

Increasing alignment up to the ABI alignment might be OK, but I'm not totally
convinced that it is.  It seems better to just leave the alignment of weak
globals alone.

llvm-svn: 145413
2011-11-29 18:26:38 +00:00