a2881ee8a4
Avoid some 's' 16-bit instruction which partially update CPSR
...
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208
llvm-svn: 129773
2011-04-19 18:11:49 +00:00
df612ba006
Avoid write-after-write issue hazards for Cortex-A9.
...
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
llvm-svn: 129772
2011-04-19 18:11:45 +00:00
3e5944d96b
Some single-precision VFP instructions can execute in either the VPF or Neon
...
pipelines, at least on Cortex-A9.
llvm-svn: 129771
2011-04-19 18:11:38 +00:00
f33715e554
Improvements for the Cortex-A9 scheduling itineraries.
...
llvm-svn: 129770
2011-04-19 18:11:36 +00:00
ee92a6b332
Add support for FastISel'ing varargs calls.
...
llvm-svn: 129765
2011-04-19 17:22:22 +00:00
af12138d10
Force the greedy register allocator to be linked alongside linear scan.
...
This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'.
llvm-svn: 129764
2011-04-19 17:17:58 +00:00
bcd09b3a7f
SelectBasicBlock is rather slow even when it doesn't do anything; skip the
...
unnecessary work where possible.
llvm-svn: 129763
2011-04-19 17:01:08 +00:00
0b68c1219f
Support nested CALLSEQ_BEGIN/END; necessary for ARM byval support. <rdar://problem/7662569>
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llvm-svn: 129761
2011-04-19 16:16:58 +00:00
6a85be25a4
Trivial simplification.
...
llvm-svn: 129759
2011-04-19 15:23:29 +00:00
fb1249548f
Tighten test case a bit.
...
Ideally, we would match an S-register to its containing D-register, but that
requires arithmetic (divide by 2).
llvm-svn: 129756
2011-04-19 06:14:45 +00:00
91328b317b
Implement support for x86 fastisel of small fixed-sized memcpys, which are generated
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en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x
and shrinks the generated .s file by 5%
llvm-svn: 129755
2011-04-19 05:52:03 +00:00
34a08c2344
tidy up
...
llvm-svn: 129753
2011-04-19 05:15:59 +00:00
5f4b783426
Implement support for fast isel of calls of i1 arguments, even though they are illegal,
...
when they are a truncate from something else. This eliminates fully half of all the
fastisel rejections on a test c++ file I'm working with, which should make a substantial
improvement for -O0 compile of c++ code.
This fixed rdar://9297003 - fast isel bails out on all functions taking bools
llvm-svn: 129752
2011-04-19 05:09:50 +00:00
d7f7c93914
Handle i1/i8/i16 constant integer arguments to calls by prepromoting them.
...
Before we would bail out on i1 arguments all together, now we just bail on
non-constant ones. Also, we used to emit extraneous code. e.g. test12 was:
movb $0, %al
movzbl %al, %edi
callq _test12
and test13 was:
movb $0, %al
xorl %edi, %edi
movb %al, 7(%rsp)
callq _test13f
Now we get:
movl $0, %edi
callq _test12
and:
movl $0, %edi
callq _test13f
llvm-svn: 129751
2011-04-19 04:42:38 +00:00
c59290a34c
be layout aware, to produce:
...
testb $1, %al
je LBB0_2
## BB#1: ## %if.then
movb $0, %al
instead of:
testb $1, %al
jne LBB0_1
jmp LBB0_2
LBB0_1: ## %if.then
movb $0, %al
how 'bout that.
llvm-svn: 129749
2011-04-19 04:26:32 +00:00
2c8a4c3b1b
fix rdar://9297006 - fast isel bails out on trunc to i1 -> bools cry,
...
a common cause of fast isel rejects on c++ code.
llvm-svn: 129748
2011-04-19 04:22:17 +00:00
7d6cd4902e
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That
...
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833
llvm-svn: 129742
2011-04-19 01:21:49 +00:00
bf78618db6
Make tests register allocation independent again.
...
llvm-svn: 129739
2011-04-19 00:14:43 +00:00
4079133796
Do not lose mem_operands while lowering VLD / VST intrinsics.
...
llvm-svn: 129738
2011-04-19 00:04:03 +00:00
939efc5b0d
Disable warning C4181: "qualifier applied to reference type; ignored"
...
This was causing a flooding of warnings with MSVC 2008. This warning was removed in MSVC 2010.
llvm-svn: 129737
2011-04-19 00:03:17 +00:00
fc8d930f6e
docs: Use <Hn> as Heading elements instead of <DIV class="doc_foo">.
...
H1 ... doc_title
H2 ... doc_section
H3 ... doc_subsection
H4 ... doc_subsubsection
llvm-svn: 129736
2011-04-18 23:59:50 +00:00
0c7732499b
Use ArrayRef variants.
...
llvm-svn: 129735
2011-04-18 23:51:03 +00:00
28af26d878
Add BumpPtrAllocator::getTotalMemory() to allow clients to query how much memory a BumpPtrAllocator allocated.
...
llvm-svn: 129727
2011-04-18 22:44:46 +00:00
75f5cd671b
Remove test to check line numbers. There are other numerous tests in our test harness to check line number information.
...
llvm-svn: 129725
2011-04-18 22:27:20 +00:00
ddac5dd269
Trim a few unneeded includes.
...
llvm-svn: 129723
2011-04-18 21:35:54 +00:00
2e3fbaab39
Invert the meaning of printAliasInstr's return value. It now returns
...
true on success and false on failure. Update callers.
llvm-svn: 129722
2011-04-18 21:28:11 +00:00
ec138b4b27
Simplify declarations slightly by using typedefs.
...
llvm-svn: 129720
2011-04-18 21:21:37 +00:00
b2545fbc2a
malloc elimination: it's a bad idea to use raw_svector_ostream on a
...
small heap-allocated SmallString because it unconditionally forces a malloc.
(Revised version of r129688, with the necessary flush() call.)
llvm-svn: 129716
2011-04-18 20:54:46 +00:00
17740e70d5
Reduce clutter in asm output. Do not emit source location as comment for each instruction.
...
llvm-svn: 129715
2011-04-18 20:26:49 +00:00
9f294a9e52
Handle spilling around an instruction that has an early-clobber re-definition of
...
the spilled register.
This is quite common on ARM now that some stores have early-clobber defines.
llvm-svn: 129714
2011-04-18 20:23:27 +00:00
5d73033e0f
Small fix to the ARM AsmParser to ensure that a
...
superclass variable is instantiated properly.
llvm-svn: 129713
2011-04-18 20:20:44 +00:00
c37aa0b26a
Fix a bug where we were counting the alias sets as completely used
...
registers for fast allocation a different way. This has us updating
used registers only when we're using that exact register.
Fixes rdar://9207598
llvm-svn: 129711
2011-04-18 19:26:25 +00:00
2b1ba48f8d
Mark some functions as used which are used within debug-only code. This
...
silences Clang's -Wunused-function when building in release mode.
llvm-svn: 129709
2011-04-18 18:49:44 +00:00
f2e8397b4b
Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
...
llvm-svn: 129708
2011-04-18 18:42:26 +00:00
7170f064c0
Make the empty StructType::get overload use an empty ArrayRef.
...
llvm-svn: 129696
2011-04-18 14:02:06 +00:00
48f75ad678
while we're at it, handle 'sdiv exact' of a power of 2 also,
...
this fixes a few rejects on c++ iterator loops.
llvm-svn: 129694
2011-04-18 07:00:40 +00:00
562d6e82bd
fix rdar://9297011 - udiv by power of two causing fast-isel rejects
...
llvm-svn: 129693
2011-04-18 06:55:51 +00:00
80254a53cc
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
...
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8
since ADD16ri will do just fine. This is a small codesize win in the generated
instruction selector.
llvm-svn: 129692
2011-04-18 06:36:55 +00:00
07add49a4b
Implement major new fastisel functionality: the matcher can now handle immediates with
...
value constraints on them (when defined as ImmLeaf's). This is particularly important
for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand,
which has a value constraint. Before this patch we ended up iseling the examples into
such amazing code as:
movabsq $7, %rax
imulq %rax, %rdi
movq %rdi, %rax
ret
now we produce:
imulq $7, %rdi, %rax
ret
This dramatically shrinks the generated code at -O0 on x86-64.
llvm-svn: 129691
2011-04-18 06:22:33 +00:00
353fda159d
relax this test to just check that the lock prefix is encoded properly,
...
and to not rely on the register allocator's arbitrary operand choices.
llvm-svn: 129690
2011-04-18 06:15:35 +00:00
3f8ecf5cc5
Revert r129688; it's breaking buildbots.
...
llvm-svn: 129689
2011-04-18 05:54:54 +00:00
2dc287a147
More malloc elimination: it's a bad idea to use raw_svector_ostream on a
...
small heap-allocated SmallString because it unconditionally forces a malloc.
llvm-svn: 129688
2011-04-18 05:38:58 +00:00
0e40208d7b
Make the StringMaps attached to MCContext use the MCContext's allocator;
...
reduces the number of calls to malloc().
llvm-svn: 129687
2011-04-18 05:02:31 +00:00
73a559fe93
Use an empty ArrayRef instead of an empty std::vector for the Function::get overload that takes no parameters.
...
llvm-svn: 129686
2011-04-18 04:55:06 +00:00
6483513a6d
docs: Redefine Heading elements as below;
...
H1 ... Title (and might be Chapter in future)
H2 ... Section
H3 ... Subsection
H4 ... Sub-subsection
llvm-svn: 129683
2011-04-18 01:17:51 +00:00
722f0ccdf9
introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper.
...
No functionality change.
llvm-svn: 129680
2011-04-17 23:29:05 +00:00
9080391b55
change OperandsSignature to use SmallVector<char> instead of std::vector<string>
...
since the strings are always exactly one character, and there are usually only 2-3 operands.
llvm-svn: 129678
2011-04-17 22:24:13 +00:00
0d7a5a7daa
since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code.
...
llvm-svn: 129677
2011-04-17 22:17:27 +00:00
c479e0631f
switch the rest of the x86 immediate patterns over to ImmLeaf,
...
simplifying them and exposing more information to tblgen. It would be nice
if other target authors adopted this as well, particularly arm since it has fastisel.
llvm-svn: 129676
2011-04-17 22:12:55 +00:00
2ff8c1a25f
now that predicates have a decent abstraction layer on them, introduce a new
...
kind of predicate: one that is specific to imm nodes. The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's. The virtue of this is that it means that fastisel and other things
can reason about these predicates.
llvm-svn: 129675
2011-04-17 22:05:17 +00:00
Bob Wilson