5 Commits

Author	SHA1	Message	Date
Krzysztof Parzyszek	64e5d7d3ae	[Hexagon] Reorganize and update instruction patterns ... llvm-svn: 316228	2017-10-20 19:33:12 +00:00
Matt Arsenault	f10061ec70	Add address space mangling to lifetime intrinsics ... In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876	2017-04-10 20:18:21 +00:00
Krzysztof Parzyszek	a72fad980c	[Hexagon] Replace instruction definitions with auto-generated ones ... llvm-svn: 294753	2017-02-10 15:33:13 +00:00
James Molloy	196ad0823e	[LSR] Don't try and create post-inc expressions on non-rotated loops ... If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs! Motivating testcase: void f(float *a, float *b, float *c, int n) { while (n-- > 0) *c++ = *a++ + *b++; } It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage. llvm-svn: 278658	2016-08-15 07:53:03 +00:00
Brendon Cahoon	d11c92a41c	[Hexagon] Generate loop1 instruction for nested loops ... loop1 is for the outer loop and loop0 is for the inner loop. Differential Revision: http://reviews.llvm.org/D9680 llvm-svn: 237266	2015-05-13 17:56:03 +00:00