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10 Commits

Author SHA1 Message Date
Krzysztof Parzyszek f3a778d757 Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane 
This should eliminate most uses of countPopulation and Log2_32 on
the lane mask values.

llvm-svn: 308658
 2017-07-20 19:43:19 +00:00
Krzysztof Parzyszek e9f0c1e031 Use LaneBitmask::getLane in a few more places 
llvm-svn: 308655
 2017-07-20 19:15:56 +00:00
Evandro Menezes 0cd23f5642 [CodeGen] Rename DEBUG_TYPE to match passnames 
Rename missing DEBUG_TYPE "machine-scheduler" from backend files, which were
absent from https://reviews.llvm.org/rL303921.

Differential revision: https://reviews.llvm.org/D35231

llvm-svn: 307719
 2017-07-11 22:08:28 +00:00
Benjamin Kramer debb3c35e0 Make helper functions static. NFC. 
llvm-svn: 304029
 2017-05-26 20:09:00 +00:00
Valery Pykhtin 74cb9c8831 [AMDGPU] Fix incorrect register usage tracking in GCNUpwardTracker 
Differential revision: https://reviews.llvm.org/D33289

llvm-svn: 303548
 2017-05-22 13:09:40 +00:00
Stanislav Mekhanoshin acca0f5c02 [AMDGPU] Use GCNRPTracker dumper methods in scheduler 
Differential Revision: https://reviews.llvm.org/D33244

llvm-svn: 303186
 2017-05-16 16:31:45 +00:00
Stanislav Mekhanoshin 464cecf81e [AMDGPU] Turn register pressure estimation into forward tracker 
This factors register pressure estimation mechanism from the
GCNSchedStrategy into the forward tracker to unify interface
with other strategies and expose it to other interested phases.

Differential Revision: https://reviews.llvm.org/D33105

llvm-svn: 303179
 2017-05-16 15:43:52 +00:00
Stanislav Mekhanoshin 7e3794d5c3 [AMDGPU] Fixed typo in GCNRegPressure, NFC 
VGRP -> VGPR, SGRP -> SGPR

llvm-svn: 302586
 2017-05-09 20:50:04 +00:00
Krzysztof Parzyszek 44e25f37ae Move size and alignment information of regclass to TargetRegisterInfo 
1. RegisterClass::getSize() is split into two functions:
   - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const;
   - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const;
2. RegisterClass::getAlignment() is replaced by:
   - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const;

This will allow making those values depend on subtarget features in the
future.

Differential Revision: https://reviews.llvm.org/D31783

llvm-svn: 301221
 2017-04-24 18:55:33 +00:00
Valery Pykhtin fd4c410f4d [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler 
Differential revision: https://reviews.llvm.org/D31046

llvm-svn: 298368
 2017-03-21 13:15:46 +00:00