Commit Graph

155482 Commits

Author SHA1 Message Date
Craig Topper a1f9c9dd8b [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and Knights Landing CPUs.
Summary: I see nothing in Agner Fog's tables to indicate that this improved between Ivy Bridge and Haswell. It's also set for all Atom CPUs so I assume KNL should have it too.

Reviewers: RKSimon, zvi, gadi.haber

Reviewed By: gadi.haber

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38890

llvm-svn: 315859
2017-10-15 16:41:15 +00:00
Krzysztof Parzyszek 4b3876f7a3 [TableGen] Remove error checks incorrectly failing on non-error conditions
In type inference, an empty type set for a specific hw mode is not an
error. In earlier stages of the design it was, but having to use non-
parameterized types with target intrinsics necessarily led to type
contradictions: since the intrinsics used specific types, they were
only valid for a specific hw mode, and the resulting type set for other
modes ended up empty. To accommodate the existence of such intrinsics
individual type sets were allowed to be empty as long as not all sets
were empty.

llvm-svn: 315858
2017-10-15 15:39:56 +00:00
Sanjay Patel 934738a3da revert r314984: revert r314698 - [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1)
Recommitting r314698. The bug exposed by this change should be fixed with:
https://reviews.llvm.org/rL315579 

llvm-svn: 315857
2017-10-15 15:39:15 +00:00
Sanjay Patel 30f30d37fb [SimplifyCFG] use range-for-loops, tidy; NFCI
There seems to be something missing here as shown in PR34471:
https://bugs.llvm.org/show_bug.cgi?id=34471 

llvm-svn: 315855
2017-10-15 14:43:39 +00:00
Aaron Ballman 615eb47035 Reverting r315590; it did not include changes for llvm-tblgen, which is causing link errors for several people.
Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1

llvm-svn: 315854
2017-10-15 14:32:27 +00:00
whitequark ae12efab20 [MergeFunctions] Merge small functions if possible without a thunk.
This can result in significant code size savings in some cases,
e.g. an interrupt table all filled with the same assembly stub
in a certain Cortex-M BSP results in code blowup by a factor of 2.5.

Differential Revision: https://reviews.llvm.org/D34806

llvm-svn: 315853
2017-10-15 12:29:09 +00:00
whitequark b2ce9ffede [MergeFunctions] Replace all uses of unnamed_addr functions.
This reduces code size for constructs like vtables or interrupt
tables that refer to functions in global initializers.

Differential Revision: https://reviews.llvm.org/D34805

llvm-svn: 315852
2017-10-15 12:29:01 +00:00
Amjad Aboud c8d67979c0 [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve PR34565
Differential Revision: https://reviews.llvm.org/D38359

llvm-svn: 315851
2017-10-15 11:00:56 +00:00
Hongbin Zheng 73f650435b [LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the Loop Pass, NFC.
This avoid code duplication and allow us to add the disable unroll metadata elsewhere.

Differential Revision: https://reviews.llvm.org/D38928

llvm-svn: 315850
2017-10-15 07:31:02 +00:00
Craig Topper a9cd59fb5d [X86] Lower vselect with constant condition to vector_shuffle even with AVX512 instructions.
Summary:
It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register.

It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day.

Reviewers: RKSimon, delena, zvi

Reviewed By: delena

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38932

llvm-svn: 315849
2017-10-15 06:39:07 +00:00
Craig Topper f02e97859b [X86] Don't use constant condition for select instruction when testing masking ops.
We should be able to fold constant conditions by converting to shuffles, but fixing that would break these tests in their current form. Since they are really trying to test masking ops, add a non-constant mask to the selects.

llvm-svn: 315848
2017-10-15 06:05:50 +00:00
Vitaly Buka 7450398e01 Remove unused variables
llvm-svn: 315847
2017-10-15 05:35:02 +00:00
Daniel Sanders 39690bdf42 [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC
Summary:
There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for
ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load
and atomic loads are handled by a separate node. However, this is not true of
GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity
of the operation. As a result, this mapping must also add a predicate that
checks for non-atomic MachineMemOperands.

This is NFC since these nodes always have predicates in practice and are
therefore always rejected at the moment.

Depends on D37443

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Reviewed By: qcolombet

Subscribers: kristof.beyls, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37445

llvm-svn: 315843
2017-10-15 02:41:12 +00:00
Daniel Sanders 3f267bf769 [tablegen] Handle common load/store predicates inside tablegen. NFC.
Summary:
GlobalISel and SelectionDAG require different code for the common
load/store predicates due to differences in the representation.
For example:
   SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG
   GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr))
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.

This patch moves the implementation of the common load/store predicates
into tablegen so that it can handle these differences.

It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.

Depends on D36618

Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37443

Includes a partial revert of r315826 since this patch makes it necessary for
getPredCode() to return a std::string and getImmCode() should have the same
interface as getPredCode().

llvm-svn: 315841
2017-10-15 02:06:44 +00:00
Davide Italiano 76067588dc [Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.
GCC otherwise emits a "defined but not used" warning on the
member function.

llvm-svn: 315838
2017-10-14 23:46:01 +00:00
Konstantin Zhuravlyov 263f7f6676 AMDGPU: Temporary disable pal metadata check line in llvm-readobj test
It fails on mips

llvm-svn: 315837
2017-10-14 23:42:11 +00:00
Konstantin Zhuravlyov 8c18f5b3d4 AMDGPU: Don't use TargetStreamer if it has not been initialized
Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl
test after r315808

We may hit few other similar issues, but I want to discuss good
solution offline.

llvm-svn: 315830
2017-10-14 22:16:26 +00:00
Craig Topper dfb443e88c [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.
llvm-svn: 315828
2017-10-14 21:46:55 +00:00
Simon Pilgrim 6ecae9fc97 [TableGen] Avoid unnecessary std::string creations
Avoid unnecessary std::string creations in the TreePredicateFn getters.

llvm-svn: 315826
2017-10-14 21:27:53 +00:00
Simon Pilgrim 36fe00ee17 [X86][SSE] Don't attempt to reduce the imul vector width of odd sized vectors (PR34947)
llvm-svn: 315825
2017-10-14 19:57:19 +00:00
Simon Pilgrim 3f49b988e0 [X86][SSE] Test vector imul reduction on 32 and 64-bit targets
llvm-svn: 315824
2017-10-14 19:46:08 +00:00
Bruno Cardoso Lopes caac2fbd19 Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for COPY"
This reverts commit r315781, breaks:
http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882

llvm-svn: 315823
2017-10-14 19:31:03 +00:00
Konstantin Zhuravlyov 13376a4bdf AMDGPU: Add AMDGPU HSA Kernel Descriptor
- Update docs to match llvm coding style
  - Add missing FP16_OVFL bit for gfx9
  - Fix the size of the kernel descriptor in the docs

Differential Revision: https://reviews.llvm.org/D38902

llvm-svn: 315822
2017-10-14 19:17:08 +00:00
Konstantin Zhuravlyov a01d8b0b63 AMDGPU: Bring HSA metadata on par with the specification
Differential Revision: https://reviews.llvm.org/D38753

llvm-svn: 315821
2017-10-14 19:03:51 +00:00
Konstantin Zhuravlyov b3c605d680 llvm-readobj: Print AMDGPU note contents
Differential Revision: https://reviews.llvm.org/D38752

llvm-svn: 315819
2017-10-14 18:21:42 +00:00
Simon Pilgrim f5b9f353c3 Pull out repeated calls to VT.getVectorNumElements(). NFCI.
llvm-svn: 315818
2017-10-14 17:37:42 +00:00
Simon Pilgrim 5bd4431aec Cleanup update_llc_test_checks.py notes.
llvm-svn: 315817
2017-10-14 17:37:03 +00:00
Konstantin Zhuravlyov 7b4be1ed89 AMDGPU: Cleanup elf-notes.ll test
llvm-svn: 315816
2017-10-14 17:36:53 +00:00
Simon Pilgrim cded82837d Use DAG::getBitcast() helper. NFCI.
llvm-svn: 315815
2017-10-14 17:14:42 +00:00
Konstantin Zhuravlyov 716af741e9 llvm-readobj: Print AMDGPU note type names
Differential Revision: https://reviews.llvm.org/D38751

llvm-svn: 315813
2017-10-14 16:43:46 +00:00
Konstantin Zhuravlyov 219066bab8 AMDGPU: Improve note directive verification in assembler
- Do not allow amd_amdgpu_isa directives on non-amdgcn architectures
  - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes
  - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes

Differential Revision: https://reviews.llvm.org/D38750

llvm-svn: 315812
2017-10-14 16:15:28 +00:00
Konstantin Zhuravlyov eda425edd4 AMDGPU: Do not emit deprecated notes for code object v3
Differential Revision: https://reviews.llvm.org/D38749

llvm-svn: 315810
2017-10-14 15:59:07 +00:00
Konstantin Zhuravlyov 9c05b2bc3b AMDGPU: Add support for isa version note
- Emit NT_AMD_AMDGPU_ISA
  - Add assembler parsing for isa version directive
    - If isa version directive does not match command line arguments, then return error

Differential Revision: https://reviews.llvm.org/D38748

llvm-svn: 315808
2017-10-14 15:40:33 +00:00
Simon Pilgrim f367c27d2d [X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))
If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle.

Fixes the last issue with PR22415

llvm-svn: 315807
2017-10-14 15:01:36 +00:00
Craig Topper f7e777763d [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.
llvm-svn: 315802
2017-10-14 07:04:48 +00:00
Craig Topper 61010a85b8 [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.
llvm-svn: 315801
2017-10-14 05:55:43 +00:00
Craig Topper ee277e190c [X86] Add patterns for vzmovl+cvtpd2ps with a load.
llvm-svn: 315800
2017-10-14 05:55:42 +00:00
Craig Topper aec05a9303 [X86] Remove some patterns for bitcasted alignednonedtemporalloads.
These select the same instruction as the non-bitcasted pattern. So this provides no additional value.

llvm-svn: 315799
2017-10-14 04:18:11 +00:00
Craig Topper 009f0aaeb0 [X86] Remove unnecessary bitconverts as the root of patterns for zero extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr.
We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions.

llvm-svn: 315798
2017-10-14 04:18:10 +00:00
Craig Topper d746747d03 [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and VCVTUDQ2PD.
This matches the patterns we have for the SSE/AVX version.

This is a prerequisite for D38714.

llvm-svn: 315797
2017-10-14 04:18:09 +00:00
Craig Topper 134241e4af [X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding tables.
llvm-svn: 315796
2017-10-14 04:18:08 +00:00
Craig Topper 0b64e67b0d [X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load folding tables.
I believe these were added incorrectly under the belief that the load size was smaller than the input register size, but that's not true.

llvm-svn: 315795
2017-10-14 04:18:07 +00:00
Craig Topper 53b0cb7fa9 [X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable load folding without the peephole pass.
This pattern is already used in AVX512VL version of these instructions. Though AVX512VL version is missing other patterns.

llvm-svn: 315794
2017-10-14 04:18:06 +00:00
Jordan Rose e55d9a1403 Revert "lit.py: Add new %{shared_output(LABEL)} substitution"
This reverts r315697 and my ill-fated attempts to fix it on Windows.
I'll try again when I get access to a Windows machine.

llvm-svn: 315793
2017-10-14 04:01:27 +00:00
Jordan Rose a33a17605d lit.py: Give up and disable the new shared-output.py test on Windows
"No such file or directory: C:\\...\\tests\\Output\\shared-output.py.tmp/Output/Shared/SHARED.tmp"

And yet other forward-slashes don't seem to be causing the same
problem. I'll see if I can get ahold of a Windows machine to poke at
this directly later.

llvm-svn: 315792
2017-10-14 03:33:46 +00:00
Yaxun Liu adde4e4c01 Fix assembler for alloca of multiple elements in non-zero addr space
Currently llvm assembler emits parsing error for valid IR assembly

alloca i32, i32 9, addrspace(5)
when alloca addr space is 5.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D38713

llvm-svn: 315791
2017-10-14 03:23:18 +00:00
Jakub Kuderski 369e85a900 [Dominators] Remove the NCA check
Summary:
This patch removes the `verifyNCD` check.

The reason for this is that the other checks are sufficient to prove or disprove correctness of any DominatorTree, and that `verifyNCD` doesn't provide (in my option) better error messages then the other ones.
Additionally, this should give a (small) improvement to the total verification time, as the check is O(n), and checking the sibling property takes O(n^3).

Reviewers: dberlin, grosser, davide, brzycki

Reviewed By: brzycki

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38802

llvm-svn: 315790
2017-10-14 03:00:56 +00:00
Vedant Kumar 1963f51f14 [llvm-cov] Factor out logic to iterate over line coverage stats (NFC)
There were two copies of the logic needed to construct a line stats
object for each line in a range: this patch brings it down to one. In
the future, this will make it easier for IDE clients to display coverage
in-line in source editors. To do that, we just need to move the new
LineCoverageIterator class to libCoverage.

llvm-svn: 315789
2017-10-14 02:27:29 +00:00
Daniel Sanders 0eb929b08b [globalisel][tablegen] Fix an unused variable warning caused by a typo (corrected OtherInsnID->OtherOpIdx).
The tests were passing by luck since the instruction ID and operand index happened to be the same.

llvm-svn: 315788
2017-10-14 01:51:46 +00:00
Daniel Sanders ab3a464482 [globalisel][tablegen] Fix undefined references to dump()
Two debugging statements snuck into the commit.

llvm-svn: 315783
2017-10-14 00:56:01 +00:00