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12 Commits

Author SHA1 Message Date
Luís Marques 46e3edcc2c [RISCV] Fix test for inline asm z constraint modifier 
Summary: Use an `i` constraint in the test, to correctly trigger the code for
handling the `z` constraint modifier.

Reviewers: asb, lenary, jrtc27
Reviewed By: lenary, jrtc27
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72134
 2020-01-15 13:50:50 +00:00
Luís Marques 043c5eafa8 [RISCV] Handle globals and block addresses in asm operands 
Summary: These seem to be the machine operand types currently needed by the
RISC-V target.

Reviewers: asb, lenary
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72275
 2020-01-13 15:34:56 +00:00
Luis Marques c2b3d527fa [RISCV] Fix a couple of tests' CHECKs 
llvm-svn: 370466
 2019-08-30 12:11:47 +00:00
Lewis Revill 7abf863f76 [RISCV] Lower inline asm constraint A for RISC-V 
This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296

llvm-svn: 369095
 2019-08-16 10:28:34 +00:00
Alex Bradbury e1e036a33b [RISCV] Support z and i operand modifiers 
Differential Revision: https://reviews.llvm.org/D57792
Patch by James Clarke.

llvm-svn: 365291
 2019-07-08 05:00:26 +00:00
Alex Bradbury aa6f2af4e6 [RISCV] Fix inline-asm.ll test by adding nounwind attribute 
This test failed since CFI directive support was added in r361320.

llvm-svn: 363123
 2019-06-12 05:32:30 +00:00
Lewis Revill 28a5cadb3a [RISCV] Lower inline asm constraints I, J & K for RISC-V 
This validates and lowers arguments to inline asm nodes which have the
constraints I, J & K, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Differential Revision: https://reviews.llvm.org/D54093

llvm-svn: 363054
 2019-06-11 12:42:13 +00:00
Alex Bradbury 5dabe03b41 [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 
r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives.

llvm-svn: 361493
 2019-05-23 12:43:13 +00:00
Alex Bradbury 4efa0b674d [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test 
llvm-svn: 354028
 2019-02-14 13:09:54 +00:00
Alex Bradbury 0171a9f4ec [RISCV] Peephole optimisation for load/store of global values or constant addresses 
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)

This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.

llvm-svn: 327831
 2018-03-19 11:54:28 +00:00
Alex Bradbury 7d6aa1f7ae [RISCV] Implement frame pointer elimination 
llvm-svn: 322839
 2018-01-18 11:34:02 +00:00
Alex Bradbury 9330e64485 [RISCV] Add basic support for inline asm constraints 
llvm-svn: 322217
 2018-01-10 20:05:09 +00:00