Commit Graph

4185 Commits

Author SHA1 Message Date
Evan Cheng 96c1457bff Teach if-conversion about instructions that were already predicated, e.g. conditional move.
llvm-svn: 37964
2007-07-06 23:24:39 +00:00
Duncan Sands 9d97420473 The exception handling intrinsics return values,
so must be lowered to a value, not nothing at all.
Subtle point: I made eh_selector return 0 and
eh_typeid_for return 1.  This means that only
cleanups (destructors) will be run as the exception
unwinds [if eh_typeid_for returned 0 then it would
be as if the first catch always matched, and the
corresponding handler would be run], which is
probably want you want in the CBE.

llvm-svn: 37947
2007-07-06 14:46:23 +00:00
Duncan Sands c5b1984f57 Indexes into the list of filter ids cannot be output
directly: they need to be turned into byte offsets
(often the same, but may not be if there are many
type infos).

llvm-svn: 37942
2007-07-06 12:46:24 +00:00
Rafael Espindola b567e3ffb0 Add the byval attribute
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
Duncan Sands 003c0b1f90 Remove propagateEHRegister in favour of a more limited
fix, that is adequate while PR1508 remains unresolved.

llvm-svn: 37938
2007-07-06 09:18:59 +00:00
Duncan Sands 81df18a50a Remove ExtractGlobalVariable - use StripPointerCasts
instead.

llvm-svn: 37937
2007-07-06 09:10:03 +00:00
Evan Cheng fc7010d962 Workaround of getCopyToRegs and getCopyFromRegs bugs for big-endian machines.
llvm-svn: 37935
2007-07-06 01:47:35 +00:00
Evan Cheng 642be16bbf Change CalculateHeights and CalculateDepths to be non-recursive.
llvm-svn: 37934
2007-07-06 01:37:28 +00:00
Dan Gohman a282694acf Make the debug string for ISD::MERGE_VALUES consistent with the others.
llvm-svn: 37922
2007-07-05 20:15:43 +00:00
Dan Gohman d258e80583 Add a parameter to getCopyToParts and getCopyFromParts to specify whether
endian swapping should be done, and update the code to use it. This fixes
some register ordering issues on big-endian systems, such as PowerPC,
introduced by the recent illegal by-val arguments changes.

llvm-svn: 37921
2007-07-05 20:12:34 +00:00
Gabor Greif e16561cd5d Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
2007-07-05 17:07:56 +00:00
Duncan Sands 4836e3a6f8 Make sure only one copy of a filter is placed in the
exception handling table if we encounter it multiple
times.  Filters could be folded harder than this, but
that would mean a lot more work for not much gain.

llvm-svn: 37908
2007-07-05 15:15:01 +00:00
Evan Cheng bb6ecf0067 Better assertion messages.
llvm-svn: 37890
2007-07-05 07:05:38 +00:00
Duncan Sands fe80638417 Extend eh.selector to support both catches and filters.
Drop the eh.filter intrinsic.

llvm-svn: 37875
2007-07-04 20:52:51 +00:00
Dan Gohman 06563a8702 Fix several over-aggressive folds for undef nodes in dagcombine, to
follow the rules for undef used in instcombine.

llvm-svn: 37851
2007-07-03 14:03:57 +00:00
Dale Johannesen a2b3c175db Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
2007-07-03 00:53:03 +00:00
Dan Gohman 533dd16a7f Replace ExpandScalarFormalArgs and ExpandScalarCallArgs with the newly
refactored getCopyFromParts and getCopyToParts, which are more general.
This effectively adds support for lowering illegal by-val vector call
arguments.

llvm-svn: 37843
2007-07-02 16:18:06 +00:00
Dan Gohman 9a70823375 Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.

This fixes test/CodeGen/X86/negative-sin.ll.

llvm-svn: 37842
2007-07-02 15:48:56 +00:00
Evan Cheng fa68d069ad Only do FNEG xform when the vector type is a floating point type.
llvm-svn: 37818
2007-06-29 21:44:35 +00:00
David Greene cf2a51e8db Remove unused variables.
llvm-svn: 37816
2007-06-29 21:42:03 +00:00
Evan Cheng 9458e6a551 Fix a vector FP constant CSE bug.
llvm-svn: 37814
2007-06-29 21:36:04 +00:00
David Greene 4c1e6f3804 Remove unnecessary attributions in comments.
llvm-svn: 37799
2007-06-29 03:42:23 +00:00
David Greene 9468bfd932 Fix reference to cached end iterator invalidated by an erase operation.
Uncovered by _GLIBCXX_DEBUG.

llvm-svn: 37795
2007-06-29 02:49:11 +00:00
David Greene 5b6f755575 Remove the "special tie breaker" because it resulted in inconsistent
ordering and thus violated the strict weak ordering requirement of
priority_queue.  Uncovered by _GLIBCXX_DEBUG.

llvm-svn: 37794
2007-06-29 02:48:09 +00:00
David Greene 451d1a6ecd Fix misue of iterator pointing to erased object. Uncovered by
_GLIBCXX_DEBUG.

llvm-svn: 37793
2007-06-29 02:45:24 +00:00
Dan Gohman 0de7694de6 Fix an assertion failure in legalizing bitcast operators on targets where
vectors are split down to single elements as part of legalization.

llvm-svn: 37785
2007-06-29 00:09:08 +00:00
Dan Gohman 7867793aff Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.

Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.

llvm-svn: 37781
2007-06-28 23:29:44 +00:00
Evan Cheng df0c705d7d If a livein is not used in the block. It's live through.
llvm-svn: 37764
2007-06-27 18:47:28 +00:00
Evan Cheng 77f541ddfd Partial fix for PR1502: If a EH register is needed in a successor of landing pad, add it as livein to all the blocks in the paths between the landing pad and the specified block.
llvm-svn: 37763
2007-06-27 18:45:32 +00:00
Dan Gohman 3b62d7265d Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
llvm-svn: 37758
2007-06-27 16:08:04 +00:00
Dan Gohman 7139a48057 Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
to compute the number and type of registers needed for vector values
instead of computing it manually. This fixes PR1529.

llvm-svn: 37755
2007-06-27 14:34:07 +00:00
Dan Gohman f4e86da3a6 Make the comment for ScalarizeVectorOp mention that it is only for use
with single-element vectors.

llvm-svn: 37752
2007-06-27 14:06:22 +00:00
Duraid Madina 95759c0e78 ok, this is something of a dirty hack, but it seems to work. (fixes e.g.
the SPASS miscompilation)

llvm-svn: 37750
2007-06-27 09:01:14 +00:00
Duraid Madina 89183dcc14 ok, this much doesn't seem to bork anything
llvm-svn: 37749
2007-06-27 08:31:07 +00:00
Duraid Madina a415dcaa2a revert evan's fixes (and my doofusness) since they had a huge code
quality hit. will look at this soon.

llvm-svn: 37748
2007-06-27 08:11:59 +00:00
Duraid Madina 540d329542 pull evan's fixes - should help the nightly tester (but there are still
some issues)

llvm-svn: 37747
2007-06-27 07:07:13 +00:00
Evan Cheng e66f822ecc Replace std::set with SmallPtrSet.
llvm-svn: 37746
2007-06-27 05:23:00 +00:00
Evan Cheng 6cf1371456 Fix an obvious bug. Old code only worked for the entry block.
llvm-svn: 37743
2007-06-27 01:16:36 +00:00
Evan Cheng 4bf87f1f44 Correctly handle implcit def / use operands.
llvm-svn: 37740
2007-06-26 21:05:13 +00:00
Evan Cheng d8417d9199 Properly handle kills of a physical register which has sub-registers that are read by later instructions.
llvm-svn: 37739
2007-06-26 21:03:35 +00:00
Duraid Madina f4dc5b26e2 tidy this file up a bit
llvm-svn: 37725
2007-06-26 00:21:58 +00:00
Duraid Madina 77416383e8 A bunch of fixes to the BigBlock allocator improve compile-time by ~20%
and code quality by ~2% on my tests.

A big thank you to Roman Levenstein for this patch! See
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070618/050717.html
for more details.

llvm-svn: 37724
2007-06-25 23:46:54 +00:00
Dan Gohman a866514528 Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
2007-06-25 16:23:39 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Duraid Madina 81a752aa95 check in the BigBlock local register allocator
llvm-svn: 37703
2007-06-22 08:27:12 +00:00
Evan Cheng e3c4419953 std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec.
llvm-svn: 37701
2007-06-22 01:35:51 +00:00
Dan Gohman 8e8d34b220 Tidy up ValueType names in comments.
llvm-svn: 37688
2007-06-21 14:48:26 +00:00
Dan Gohman 04deef3a49 Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.

llvm-svn: 37687
2007-06-21 14:42:22 +00:00
Evan Cheng aa5f5d960d Xforms:
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))

llvm-svn: 37685
2007-06-21 07:39:16 +00:00
Evan Cheng a955c02c9b Avoid if-converting simple block that ends with unconditional branch or fallthrough unless it branches / falls to the 'false' block. Not profitable, may end up increasing code size.
llvm-svn: 37660
2007-06-19 21:45:13 +00:00
Dan Gohman a7644dd9b9 Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656
2007-06-19 14:13:56 +00:00
Chris Lattner 37228f6ce5 document and hide two options.
llvm-svn: 37651
2007-06-19 05:47:49 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Chris Lattner 26be02febf add isVarArg to CCState
llvm-svn: 37640
2007-06-19 00:11:09 +00:00
Evan Cheng 0598b2d5eb Fix some fragile code wrt CFG edge updating.
llvm-svn: 37634
2007-06-18 22:44:57 +00:00
Evan Cheng 2afd702c20 Move CorrectExtraCFGEdges() from BranchFolding.cpp to a MachineBasicBlock method.
llvm-svn: 37633
2007-06-18 22:43:58 +00:00
Chris Lattner e31adc8ab9 make ComputeTopDownOrdering significantly faster and use less stack space
by making it non-recursive

llvm-svn: 37629
2007-06-18 21:28:10 +00:00
Dan Gohman 8c7333266c Make chain dependencies blue, in addition to being dashed.
llvm-svn: 37626
2007-06-18 15:30:16 +00:00
Evan Cheng 51eb2c3bbe Properly remove duplicate instructions as result of diamond if-conversion. Other bug fixes.
llvm-svn: 37623
2007-06-18 08:37:25 +00:00
Evan Cheng 3a51c854d0 Really turn if-converter loose:
1. Consider all possible ifcvt cases at once. No longer restricted to bottom
   up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
   ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.

llvm-svn: 37613
2007-06-16 09:34:52 +00:00
Tanya Lattner e199f97fa8 Codegen support (stripped out) for the annotate attribute.
llvm-svn: 37608
2007-06-15 22:26:58 +00:00
Evan Cheng 23402fcaef Not every predicable block can be safely duplicated.
llvm-svn: 37607
2007-06-15 21:18:05 +00:00
Chris Lattner f852e339b6 Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
for tied register constraints.

llvm-svn: 37601
2007-06-15 19:11:01 +00:00
Evan Cheng 234a90e83e MachineInstr::isPredicable() is no longer needed.
llvm-svn: 37599
2007-06-15 19:06:07 +00:00
Duncan Sands 92bf2c628c Workaround for PR1508.
llvm-svn: 37597
2007-06-15 19:04:19 +00:00
Evan Cheng cd5f5e3ecd Extra edges are deleted later if needed.
llvm-svn: 37593
2007-06-15 17:34:48 +00:00
Evan Cheng 92fb5453c3 Allow small blocks to be duplicated to enable if-conversion.
llvm-svn: 37590
2007-06-15 07:36:12 +00:00
Evan Cheng add977670f No really, clear predcessors states.
llvm-svn: 37581
2007-06-14 23:34:09 +00:00
Evan Cheng 9fc56c079d If BB is predicated, invalidate its predecessor(s) which would if-convert it. It needs to be re-analyzed.
llvm-svn: 37580
2007-06-14 23:13:19 +00:00
Dan Gohman 5c4413120f Rename MVT::getVectorBaseType to MVT::getVectorElementType.
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
Evan Cheng e08f0eefa6 Fix typo.
llvm-svn: 37577
2007-06-14 21:26:08 +00:00
Dan Gohman 4a4a8eb00e Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.

llvm-svn: 37576
2007-06-14 20:50:44 +00:00
Evan Cheng 1e6f08b2a2 Fix some stupid bugs that have effectively disabled if-conversion.
llvm-svn: 37575
2007-06-14 20:28:52 +00:00
Duncan Sands 7413736a7e Only correctly lower exception handing intrinsics if exception handling is
turned on.  Likewise for scanning of invokes to mark landing pads.

llvm-svn: 37570
2007-06-13 16:53:21 +00:00
Dan Gohman 26455c4ae0 Introduce new SelectionDAG node opcodes VEXTRACT_SUBVECTOR and
VCONCAT_VECTORS. Use these for CopyToReg and CopyFromReg legalizing in
the case that the full register is to be split into subvectors instead
of scalars. This replaces uses of VBIT_CONVERT to present values as
vector-of-vector types in order to make whole subvectors accessible via
BUILD_VECTOR and EXTRACT_VECTOR_ELT.

This is in preparation for adding extended ValueType values, where
having vector-of-vector types is undesirable.

llvm-svn: 37569
2007-06-13 15:12:02 +00:00
Dan Gohman cbd51c8b60 When creating CopyFromReg nodes, always use legal types. And use the
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.

llvm-svn: 37568
2007-06-13 14:55:16 +00:00
Duncan Sands 97f7236e70 The fix that was applied for PR1224 stops the compiler
crashing but breaks exception handling.  The problem
described in PR1224 is that invoke is a terminator that
can produce a value.  The value may be needed in other
blocks.  The code that writes to registers values needed
in other blocks runs before terminators are lowered (in
this case invoke) so asserted because the value was not
yet available.  The fix that was applied was to do invoke
lowering earlier, before writing values to registers.

The problem this causes is that the code to copy values
to registers can be output after the invoke call.  If
an exception is raised and control is passed to the
landing pad then this copy-code will never execute.  If
the value is needed in some code path reached via the
landing pad then that code will get something bogus.

So revert the original fix and simply skip invoke values
in the general copying to registers code.  Instead copy
the invoke value to a register in the invoke lowering code.

llvm-svn: 37567
2007-06-13 05:51:31 +00:00
Evan Cheng cbaaff58bf Typo
llvm-svn: 37566
2007-06-13 00:04:00 +00:00
Evan Cheng 9acfa7b063 Now if-converting all 4 variants of triangles.
llvm-svn: 37565
2007-06-12 23:54:05 +00:00
Lauro Ramos Venancio 4c2f003971 Fix a typo in bswap lowering.
llvm-svn: 37544
2007-06-11 23:16:16 +00:00
Evan Cheng 4dd31a7b1b Restructure code to reduce ifcvt compile time cost.
llvm-svn: 37543
2007-06-11 22:26:22 +00:00
Reid Spencer 14b62a553e Fix the build.
llvm-svn: 37537
2007-06-10 00:19:17 +00:00
Evan Cheng 2117d1f20e Don't change CFG during analysis stage. Do so during ifcvt and invalidate predecessors accordingly.
llvm-svn: 37531
2007-06-09 01:03:43 +00:00
Evan Cheng 288f1545a6 Carefully remove extraneous CFG edges after each ifcvt.
llvm-svn: 37529
2007-06-08 22:01:07 +00:00
Evan Cheng df1a42935b Correct transfer predicate information.
llvm-svn: 37524
2007-06-08 19:17:12 +00:00
Evan Cheng e93ccc013f Hidden options to help debugging ifcvt issues.
llvm-svn: 37523
2007-06-08 19:10:51 +00:00
David Greene 02f6e9b621 Factor live variable analysis so it does not do register coalescing
simultaneously.  Move that pass to SimpleRegisterCoalescing.

This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.

llvm-svn: 37520
2007-06-08 17:18:56 +00:00
Evan Cheng 7783f82e21 Allow more cmp / bcc to be predicated; clean up triangle ifcvt checking code.
llvm-svn: 37518
2007-06-08 09:36:04 +00:00
Duncan Sands dc8fc1550e Use more realistically sized vectors. Reserve capacity if we know in advance
how much will be used.

llvm-svn: 37515
2007-06-08 08:59:11 +00:00
Dale Johannesen 86798e5e11 Make throttle a hidden parameter, per review.
llvm-svn: 37511
2007-06-08 01:08:52 +00:00
Dale Johannesen 52fcf022f7 Throttle tail merging; handling blocks with large numbers of predecessors
is too slow.

llvm-svn: 37509
2007-06-08 00:34:27 +00:00
Evan Cheng 1236ef7bcc Only remove the edge from entry to false if false block is merged.
llvm-svn: 37503
2007-06-07 22:31:28 +00:00
Dale Johannesen 9a4d987a5f Do not change the size of function arguments. PR 1489.
llvm-svn: 37496
2007-06-07 21:07:15 +00:00
Evan Cheng d3f3f0adad ifcvt a triangle: don't merge ifcvt block with rejoin block if it can fall through to it. If merged, the resulting block is not a candidate for iterative ifcvting since it contains both predicated and non-predicated code.
llvm-svn: 37487
2007-06-07 08:13:00 +00:00
Evan Cheng be9859eea2 Lots of bug fixes. Now finally in a reasonable state.
llvm-svn: 37485
2007-06-07 02:12:15 +00:00
Owen Anderson cfb6f40424 Quick patch to fix the build, based on what it appears Evan meant to write.
Evan, please check that this is in fact correct.

llvm-svn: 37471
2007-06-06 16:22:00 +00:00
Duncan Sands 29d1dc6f1a Fold the exception actions table harder: if two typeid lists start the
same, only output one copy of the common part.

llvm-svn: 37470
2007-06-06 15:37:31 +00:00
Evan Cheng 9030b98aca Lots of bug fixes.
llvm-svn: 37467
2007-06-06 10:16:17 +00:00
Duncan Sands 61166501a1 Additional fix for PR1422: make sure the landing pad label is placed in the
correct machine basic block - do not rely on the eh.exception intrinsic
being in the landing pad: the loop optimizers can move it out.

llvm-svn: 37463
2007-06-06 10:05:18 +00:00
Evan Cheng e4ec918be0 If a unconditional branch is added to branch to the false path during ifcvt, the predicated block cannot be iteratively ifcvted.
llvm-svn: 37456
2007-06-06 02:08:52 +00:00
Evan Cheng b30a89457c Minor statistics counting bug.
llvm-svn: 37451
2007-06-06 01:12:44 +00:00
Evan Cheng 30565998bb Fix a couple of typos and be smarter about order of blocks when ifcvt a diamond.
llvm-svn: 37449
2007-06-06 00:57:55 +00:00
Evan Cheng 7948422b78 Fix diamond shape ifcvt bugs.
llvm-svn: 37444
2007-06-05 23:46:14 +00:00
Evan Cheng c1a0b8ce1d ReplaceUsesOfBlockWith() can modify the predecessors list.
llvm-svn: 37441
2007-06-05 22:03:53 +00:00
Evan Cheng 3e5bf0827c Do not ifcvt if either true / false path is a backedge. Not profitable in almost all cases.
llvm-svn: 37440
2007-06-05 20:38:42 +00:00
Evan Cheng 2c1acd6d9e I had a senior moment.
llvm-svn: 37433
2007-06-05 07:05:25 +00:00
Evan Cheng 6e4babe8cc If the predicated block requires an early exit, end the block there and add a unconditional branch to false block. AnalyzeBranch() does not understand early exits.
llvm-svn: 37430
2007-06-05 01:31:40 +00:00
Evan Cheng 17aad8164e Fix some subtle bugs: bug during succeessor copying; incorrectly updating states of ifcvted blocks.
llvm-svn: 37429
2007-06-05 00:07:37 +00:00
Dale Johannesen 0558dda319 Tail merging wasn't working for predecessors of landing pads. PR 1496.
llvm-svn: 37427
2007-06-04 23:52:54 +00:00
Evan Cheng 53ce7de03b Global ctors / dtors alignment shouldn't be hard-coded at 4. e.g. It could be 8 for 64-bit targets.
llvm-svn: 37421
2007-06-04 20:39:18 +00:00
Evan Cheng 91233153bf Forgot to check for if iterator reached the end.
llvm-svn: 37420
2007-06-04 20:33:36 +00:00
Dan Gohman b4c2690446 Pass the DAG to SDNode::dump to let it do more detailed dumps in some cases.
llvm-svn: 37413
2007-06-04 16:17:33 +00:00
Dan Gohman 92a7f3a65e Resolve implicit alignment before computing the FoldingSet information so
that the CSE map always contains explicit alignment information. This allows
more loads to be CSE'd when there is a mix of explicit-alignment loads and
implicit-alignment loads.

Also, in SelectionDAG::FindModifiedNodeSlot, add the operands to the
FoldingSetNodeID before the load/store information instead of after, so
that it matches what is done elsewhere.

llvm-svn: 37411
2007-06-04 15:49:41 +00:00
Evan Cheng 312b723af2 Let IfConverter loose. Allow more aggressive subsumptions; reorder basic blocks to expose more ifcvt opportunities; code clean up and fixes.
llvm-svn: 37409
2007-06-04 06:47:22 +00:00
Evan Cheng df75785594 Move ReplaceUsesOfBlockWith() out of BranchFolding into a MachineBasicBlock general facility.
llvm-svn: 37408
2007-06-04 06:44:01 +00:00
Duncan Sands f708f73a1b The semantics of invoke require that we always jump to the unwind block
(landing pad) when an exception unwinds through the call.  This doesn't
quite match the way the dwarf unwinder works: by default it only jumps to
the landing pad if the catch or filter specification matches, and otherwise
it keeps on unwinding.  There are two ways of specifying to the unwinder
that it should "always" (more on why there are quotes here later) jump to
the landing pad: follow the specification by a 0 typeid, or follow it by
the typeid for the NULL typeinfo.  GCC does the first, and this patch makes
LLVM do the same as gcc.  However there is a problem: the unwinder performs
optimizations based on C++ semantics (it only expects destructors to be
run if the 0 typeid fires - known as "cleanups"), meaning it assumes that no
exceptions will be raised and that the raised exception will be reraised
at the end of the cleanup code.  So if someone writes their own LLVM code
using the exception intrinsics they will get a nasty surprise if they don't
follow these rules.  The other possibility of using the typeid corresponding
to NULL (catch-all) causes the unwinder to make no assumptions, so this is
probably what we should use in the long-run.  However since we are still
having trouble getting exception handling working properly, for the moment
it seems best to closely imitate GCC.

llvm-svn: 37399
2007-06-02 17:16:06 +00:00
Duncan Sands c063f5f362 Integrate exception filter support and exception catch support. This
simplifies the code in DwarfWriter, allows for multiple filters and
makes it trivial to specify filters accompanied by cleanups or catch-all
specifications (see next patch).  What a deal!  Patch blessed by Anton.

llvm-svn: 37398
2007-06-02 16:53:42 +00:00
Zhou Sheng 0a0ae932ca Make LowerCTPOP() support arbitrary bitwidth integer type.
llvm-svn: 37397
2007-06-02 04:10:33 +00:00
Dale Johannesen 6e7cdce773 Fix CorrectExtraCFGEdges to allow for multiple LandingPad targets.
llvm-svn: 37394
2007-06-02 00:08:15 +00:00
Dale Johannesen 9746e3a22b Fancier algorithm in tail-merge comment implemented, so remove comment.
llvm-svn: 37393
2007-06-01 23:04:28 +00:00
Dale Johannesen 3c0a13762d Implement smarter algorithm for choosing which blocks to tail-merge.
See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark.  I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.

llvm-svn: 37392
2007-06-01 23:02:45 +00:00
Evan Cheng 4dcf1e8582 Correctly mark early-exit on the false path.
llvm-svn: 37387
2007-06-01 20:29:21 +00:00
Duncan Sands 706421e712 Since TypeInfos are passed as i8 pointers, a NULL TypeInfo should be passed
as a null i8 pointer not as a 0 i32.

llvm-svn: 37383
2007-06-01 08:18:30 +00:00
Evan Cheng 6a2cf070cc Ifcvt triangle: don't ifcvt 'true' BB if it has other predecessors; don't merge 'false' BB if it has other predecessors.
llvm-svn: 37382
2007-06-01 07:41:07 +00:00
Evan Cheng 95c7917d92 Remove a bogus check. Even terminators in a ifcvt need to be predicated. Unconditional branches can usually be converted to conditional ones.
llvm-svn: 37380
2007-06-01 00:55:26 +00:00
Evan Cheng 20e05997f5 Allow multiple ifcvt candidates to share children blocks; add some debugging code.
llvm-svn: 37379
2007-06-01 00:12:12 +00:00
Dale Johannesen 1a401e68a8 Arrange for only 1 of multiple branches to landing pad to be kept.
Do not remove empty landing pads (EH table needs to be updated)

llvm-svn: 37375
2007-05-31 21:54:00 +00:00
Evan Cheng e6ccb6c5ed Fix a typo.
llvm-svn: 37374
2007-05-31 20:53:33 +00:00
Chris Lattner 3e3ff30aa2 Fix the asmprinter so that a globalvalue can specify an explicit alignment
smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373
2007-05-31 18:57:45 +00:00
Lauro Ramos Venancio 5b0757a401 Fix PR1424.
When a function has FP, the register scavenging spill slot offset already
was calculated.

llvm-svn: 37371
2007-05-31 18:27:58 +00:00
Evan Cheng 905a8f4940 Change traversal order to bottom up in preparation for more aggressive if-conversion.
llvm-svn: 37365
2007-05-30 19:49:19 +00:00
Chris Lattner 397c4d9ef6 Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.
llvm-svn: 37362
2007-05-30 16:30:06 +00:00
Dale Johannesen d14ad078c6 Changed per review comment.
llvm-svn: 37355
2007-05-30 00:32:01 +00:00
Dale Johannesen a69ebdbebc Make stable_sort in tail merging actually be stable (it never was, but didn't
matter until my last change).  Reenable tail merging by default.

llvm-svn: 37354
2007-05-29 23:47:50 +00:00
Evan Cheng 20f7d30f92 Don't merge in tail block of a diamond if it has more than one predecessors after if-conversion.
llvm-svn: 37353
2007-05-29 23:37:20 +00:00
Evan Cheng c2237ce217 If there is an empty block between a source and its successor block, it still requires a unconditional branch.
llvm-svn: 37344
2007-05-29 22:31:16 +00:00
Evan Cheng 5983bdbb2c Add missing const qualifiers.
llvm-svn: 37341
2007-05-29 18:35:22 +00:00
Zhou Sheng d7dc1ed64c Correct the logic in LowerPartSet which cleared the bits from 0 to low-1.
llvm-svn: 37331
2007-05-26 03:43:13 +00:00
Chris Lattner 4698083b96 tighten up recursion depth again
llvm-svn: 37330
2007-05-25 02:19:06 +00:00
Evan Cheng 13f5f7df95 Silly boog.
llvm-svn: 37328
2007-05-25 00:59:01 +00:00
Dale Johannesen 1409b6a59b Blocks that cond-br and uncond-br/fallthrough to same block should have
only one successor.

llvm-svn: 37324
2007-05-24 18:31:55 +00:00
Dale Johannesen 1af8c870c7 Fix for PR1444: do not create two successors to the same block.
Temporarily, this breaks CodeGen/Generic/2006-02-12-InsertLibraryCall.ll
by exposing an unrelated latent problem; working on that.

llvm-svn: 37323
2007-05-24 17:39:32 +00:00
Dan Gohman 30978078bf Minor comment cleanups.
llvm-svn: 37321
2007-05-24 14:36:04 +00:00
Dan Gohman 703e0f8608 Add explicit qualification for namespace MVT members.
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
Evan Cheng a4d187b8ce Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer.
llvm-svn: 37318
2007-05-24 02:35:39 +00:00
Dale Johannesen f4a77d2481 Two tail merging improvements:
When considering blocks with more than 2 predecessors, merge the block with
the largest number of matching insns, rather than the first block found.
Considering that 1 matching insn is enough to show a win for candidates that
already end with a branch.

llvm-svn: 37315
2007-05-23 21:07:20 +00:00
Anton Korobeynikov 3b327826db Mark all calls as "could throw", when exceptions are enabled. Emit necessary LP info too. This fixes PR1439
llvm-svn: 37311
2007-05-23 11:08:31 +00:00
Chris Lattner 6509c0673f prevent exponential recursion in isNegatibleForFree
llvm-svn: 37310
2007-05-23 07:35:22 +00:00
Evan Cheng d0e669199b Preliminary iterative if-conversion support.
llvm-svn: 37309
2007-05-23 07:23:16 +00:00
Dale Johannesen f9cbdc676c name change requested by review of previous patch
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
Owen Anderson 0ae7eb5e7c Silence a warning.
llvm-svn: 37288
2007-05-22 18:13:40 +00:00
Dale Johannesen 82810c8a13 Make tail merging the default, except on powerPC. There was no prior art
for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285
2007-05-22 17:14:46 +00:00
Evan Cheng e26c0916a3 If-convert early exit blocks (returns, etc.); bug fixes, etc.
llvm-svn: 37270
2007-05-21 22:22:58 +00:00
Duncan Sands 34e82a4508 Only emit one entry in the exception action table for each action, even if
it occurs for multiple landing pads.

llvm-svn: 37267
2007-05-21 18:50:28 +00:00
Chris Lattner 1fa8276e70 same patch as the previous one, but the symmetric case
llvm-svn: 37249
2007-05-19 00:46:51 +00:00
Chris Lattner b08cbbd737 Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (in
this case, the xform introduces an extra operation).  This compiles
PowerPC/compare-duplicate.ll into:

_test:
        subf r2, r3, r4
        cmplw cr0, r2, r3
        bne cr0, LBB1_2 ;F

instead of:

_test:
        slwi r2, r3, 1
        subf r3, r3, r4
        cmplw cr0, r4, r2
        bne cr0, LBB1_2 ;F

This is target independent of course.

llvm-svn: 37246
2007-05-19 00:43:44 +00:00
Evan Cheng 018cffbca4 Clean up.
llvm-svn: 37237
2007-05-18 19:32:08 +00:00
Evan Cheng faaf716540 Change to depth-first traversal.
llvm-svn: 37236
2007-05-18 19:26:33 +00:00
Dale Johannesen dafda82755 Document an inefficiency in tail merging.
llvm-svn: 37235
2007-05-18 18:46:40 +00:00
Dan Gohman b539df3389 Qualify calls to getTypeForValueType with MVT:: too.
llvm-svn: 37233
2007-05-18 18:41:29 +00:00
Evan Cheng 2e82cefd24 Some restructuring in preparation for most aggressive if-conversion.
llvm-svn: 37231
2007-05-18 18:14:37 +00:00
Dan Gohman 1796f1f8e9 Qualify several calls to functions in the MVT namespace, for consistency.
llvm-svn: 37230
2007-05-18 17:52:13 +00:00
Evan Cheng f25d3a5d73 Watch out for blocks that end with a return.
llvm-svn: 37227
2007-05-18 17:06:53 +00:00
Evan Cheng 478b805956 If true / false blocks fallthrough before ifcvt, add unconditional branches to ifcvt'd block.
llvm-svn: 37200
2007-05-18 01:55:58 +00:00
Dale Johannesen f8956178af Remove some unneeded branches. (spotted by Evan, thanks)
llvm-svn: 37198
2007-05-18 01:28:58 +00:00
Evan Cheng 0f745da4fe Make use of target specific block size limits; bug fixes.
llvm-svn: 37195
2007-05-18 00:20:58 +00:00
Evan Cheng a92b2b38ff Move isSuccessor() offline, change it to use std::find.
llvm-svn: 37190
2007-05-17 23:58:53 +00:00
Chris Lattner 0184f88deb disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for
i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169
2007-05-17 18:19:23 +00:00
Chris Lattner 2135bc08d6 add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets
llvm-svn: 37168
2007-05-17 18:15:41 +00:00
Evan Cheng 429178d727 Add target hook to specify block size limit for if-conversion.
llvm-svn: 37134
2007-05-16 23:45:53 +00:00
Dale Johannesen 7a6c175e7a Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
llvm-svn: 37130
2007-05-16 22:45:30 +00:00
Evan Cheng af71610429 isBlockPredicable() always ignore terminal instructions; add comments.
llvm-svn: 37126
2007-05-16 21:54:37 +00:00
Evan Cheng 5ea933a009 Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.
llvm-svn: 37121
2007-05-16 20:56:08 +00:00
Duncan Sands 59ae77486c Output exception call-sites in address order, as required by the unwinding
runtime.

llvm-svn: 37104
2007-05-16 12:12:23 +00:00
Chris Lattner 48fb92f75d Use a ptr set instead of a linear search to unique TokenFactor operands.
This fixes PR1423

llvm-svn: 37102
2007-05-16 06:37:59 +00:00
Evan Cheng 35fc2119b0 Devang points out that we need an assertion here.
llvm-svn: 37097
2007-05-16 05:11:10 +00:00
Evan Cheng 288f133c71 Bug fix: should check ABI alignment, not pref. alignment.
llvm-svn: 37094
2007-05-16 02:04:50 +00:00
Evan Cheng f5e53a58db Initial commit of (very basic) if converter.
llvm-svn: 37092
2007-05-16 02:00:57 +00:00
Dale Johannesen 420a85d0cf Remove extra CFG edges before doing these passes; it makes them happier.
llvm-svn: 37089
2007-05-15 21:19:17 +00:00
Lauro Ramos Venancio 3f142cbca2 Fix an infinite recursion in GetNegatedExpression.
llvm-svn: 37086
2007-05-15 17:05:43 +00:00
Duncan Sands 750e8c5d4d The index into the actions table is a ULEB128 not a SLEB128.
llvm-svn: 37084
2007-05-15 13:54:14 +00:00
Reid Spencer daed139420 Un-brain-dead-ify the lowering of part set for the reverse case.
llvm-svn: 37071
2007-05-15 02:26:52 +00:00
Chris Lattner c7596efdad Fix some subtle issues handling immediate values. This fixes
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069
2007-05-15 01:33:58 +00:00
Evan Cheng 4d728b0419 Added getNumExplicitOperands and findFirstPredOperand.
llvm-svn: 37064
2007-05-15 01:26:09 +00:00
Chris Lattner e49c974a7c implement a simple fneg optimization/propagation thing. This compiles:
CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054
2007-05-14 22:04:50 +00:00
Evan Cheng e1595b6859 Only worry about intervening kill if there are more than one live ranges in the interval.
llvm-svn: 37052
2007-05-14 21:23:51 +00:00
Evan Cheng c690cba7d9 Fix for PR1406:
v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050
2007-05-14 21:10:05 +00:00
Evan Cheng fc2377d4ed When marking a register as being implicitly defined, make sure to clear its partial use info as well.
llvm-svn: 37046
2007-05-14 20:39:18 +00:00
Reid Spencer 764ae2a21b Give names to the final result values of the part_set computations. This
just aids in readability and debugability of the output. No functional change.

llvm-svn: 37037
2007-05-14 17:21:17 +00:00
Anton Korobeynikov 1ee0c8d563 Emit function debug frames in one atom. This will prevent us from generating incorrect assembler in case of both
debug information & exception information presented.

llvm-svn: 37019
2007-05-13 17:30:11 +00:00
Anton Korobeynikov bbaf55448b Emit multiple common EH frames for multiple (including blank) personality
functions. This partly fixes PR1414: now we're restricted only to one
personality function per eh frame, not per module. Further work on
"multiple personalities" topic needs representative example.

llvm-svn: 37018
2007-05-13 15:42:26 +00:00
Anton Korobeynikov 13da17843c More DWARF-related things cleanup:
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.

llvm-svn: 37015
2007-05-12 22:36:25 +00:00
Reid Spencer bf283708f7 Get the size of auto arrays right, regardless of its changing size.
llvm-svn: 37006
2007-05-12 11:07:40 +00:00
Devang Patel 79a71ec3ad Fix http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070507/049516.html
llvm-svn: 36998
2007-05-11 23:14:43 +00:00
Anton Korobeynikov 67286b1266 Perform correct actions numbers/sizes computation
llvm-svn: 36988
2007-05-11 08:47:35 +00:00
Anton Korobeynikov 00d02442b0 Fix action No calculation in multiple-invoke-one-LP mode
llvm-svn: 36987
2007-05-11 08:23:57 +00:00
Dale Johannesen cc8f571bc8 Do not generate branches to entry block. This fixes several test suite
failures on PPC (can happen only when prologue code is null)

llvm-svn: 36979
2007-05-10 23:59:23 +00:00
Anton Korobeynikov ee02c7d2fb Ooops. Some debugging stuff :)
llvm-svn: 36978
2007-05-10 22:38:46 +00:00
Anton Korobeynikov 96142de3f0 Allow multiple invokes per landing pad. This (probably) fixes PR1410.
llvm-svn: 36977
2007-05-10 22:34:59 +00:00
Duncan Sands b43fe52136 Later computations assume we are aligned at this point.
llvm-svn: 36975
2007-05-10 18:40:24 +00:00
Anton Korobeynikov ed5dad4306 TypeIds are indexed by j, not i
llvm-svn: 36974
2007-05-10 15:10:34 +00:00
Dale Johannesen 6e16d09252 Make tail merging handle many more cases (all it can, I think).
llvm-svn: 36966
2007-05-10 01:01:49 +00:00
Evan Cheng f325c2a65e Can't fold the bit_convert is the store is a truncating store.
llvm-svn: 36962
2007-05-09 21:49:47 +00:00
Anton Korobeynikov 192d09c2d9 Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This
fixes PR1403.

llvm-svn: 36959
2007-05-09 20:07:08 +00:00
Bill Wendling 31fd60ba0c Change names from RA to something unique to get rid of naming conflicts with
certain linkers...

llvm-svn: 36944
2007-05-08 19:02:46 +00:00
Evan Cheng 9e17872c1d Eliminate MarkVirtRegAliveInBlock recursion.
llvm-svn: 36943
2007-05-08 19:00:00 +00:00
Evan Cheng 562e45692e Forgot a check.
llvm-svn: 36910
2007-05-07 21:36:06 +00:00
Evan Cheng a4cf58a103 Enable a couple of xforms:
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment

llvm-svn: 36908
2007-05-07 21:27:48 +00:00
Dale Johannesen 9a25b3afcd Handle some non-exit blocks in tail merging.
llvm-svn: 36907
2007-05-07 20:57:21 +00:00
Duncan Sands 671e8c4444 Parameter attributes on invoke calls were being lost due to the wrong
attribute index being used.  Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him.  This is PR1398.

llvm-svn: 36906
2007-05-07 20:49:28 +00:00
Anton Korobeynikov a8fd7fdc25 Detabify
llvm-svn: 36891
2007-05-06 20:14:21 +00:00
Nick Lewycky e7da2d6ac3 Fix typo in comment.
llvm-svn: 36873
2007-05-06 13:37:16 +00:00
Duncan Sands 00282a21a5 Use the personality function that was registered with MMI rather than
hardwiring in the C++ one.

llvm-svn: 36789
2007-05-05 20:27:00 +00:00
Chris Lattner 07e6f3257c Propagate alignment/volatility in two places.
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1).  This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll

llvm-svn: 36787
2007-05-05 19:39:05 +00:00
Duncan Sands 02528f5425 Spelling fix.
llvm-svn: 36781
2007-05-05 16:32:57 +00:00
Anton Korobeynikov 4db0090339 Emit sections/directives in the proper order. This fixes PR1376. Also,
some small cleanup was made.

llvm-svn: 36780
2007-05-05 09:04:50 +00:00
Duncan Sands 4cb9eb81ef A bitcast of a global variable may have been constant folded to a GEP -
handle this case too.

llvm-svn: 36745
2007-05-04 17:12:26 +00:00
Evan Cheng 044a0a8cfb Don't create indexed load / store with zero offset!
llvm-svn: 36716
2007-05-03 23:52:19 +00:00
Chris Lattner 44a2ed66b1 Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
and PR1382

llvm-svn: 36672
2007-05-03 16:54:34 +00:00
Devang Patel 8c78a0bff0 Drop 'const'
llvm-svn: 36662
2007-05-03 01:11:54 +00:00
Anton Korobeynikov 11940fbba3 Properly set arguments bitwidth of EHSELECT node
llvm-svn: 36654
2007-05-02 22:15:48 +00:00
Devang Patel e95c6ad802 Use 'static const char' instead of 'static const int'.
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652
2007-05-02 21:39:20 +00:00
Lauro Ramos Venancio 41223586a2 Fix build error.
llvm-svn: 36648
2007-05-02 20:37:47 +00:00
Anton Korobeynikov b538f67b1a Fix couple of bugs connected with eh info:
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.

llvm-svn: 36633
2007-05-01 22:23:12 +00:00
Devang Patel 09f162ca6a Do not use typeinfo to identify pass in pass manager.
llvm-svn: 36632
2007-05-01 21:15:47 +00:00
Evan Cheng 8cd28f0fb1 If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames.
llvm-svn: 36625
2007-05-01 09:01:42 +00:00
Evan Cheng b68343cdd8 Forgot about chain result; also UNDEF cannot have multiple values.
llvm-svn: 36622
2007-05-01 08:53:39 +00:00
Nate Begeman 27a625a74b llvm bug #1350, parts 1, 2, and 3.
llvm-svn: 36618
2007-05-01 05:57:02 +00:00
Evan Cheng 77c545e6b8 Under normal circumstances, when a frame pointer is not required, we reserve
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.

llvm-svn: 36607
2007-05-01 00:52:08 +00:00
Evan Cheng a684cd23a5 * Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
produce two results.)
* Do not touch volatile loads.

llvm-svn: 36604
2007-05-01 00:38:21 +00:00
Chris Lattner 4dbbace4ff Fix PR1228 and CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
llvm-svn: 36602
2007-04-30 23:35:00 +00:00
Chris Lattner f90c8fbd2b print isLandingPad() for MBBs
llvm-svn: 36600
2007-04-30 23:12:53 +00:00
Chris Lattner 8cfd33b647 Continue refactoring inline asm code. If there is an earlyclobber output
register, preallocate all input registers and the early clobbered output.

This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll

llvm-svn: 36599
2007-04-30 21:11:17 +00:00
Evan Cheng 6b77c3ed52 Updates.
llvm-svn: 36594
2007-04-30 18:42:09 +00:00
Chris Lattner 4333f8b1cf refactor GetRegistersForValue to take OpInfo as an argument instead of various
pieces of it.  No functionality change.

llvm-svn: 36592
2007-04-30 17:29:31 +00:00
Chris Lattner ef07332504 refactor some code, no functionality change
llvm-svn: 36590
2007-04-30 17:16:27 +00:00
Chris Lattner b58f93f273 Clean up multi-line asam string printing. Instead of printing:
# InlineAsm Start
        subfc r3,r5,r4
                subfze r4,r3
        # InlineAsm End

print:

        # InlineAsm Start
        subfc r3,r5,r4
        subfze r4,r3
        # InlineAsm End

llvm-svn: 36589
2007-04-30 17:00:18 +00:00
Chris Lattner 412d61af43 generalize aggregate handling
llvm-svn: 36568
2007-04-29 18:58:03 +00:00
Anton Korobeynikov 546ea7ea88 Implement review feedback
llvm-svn: 36564
2007-04-29 18:02:48 +00:00
Chris Lattner 401d8db381 memory operands that have a direct operand should have their stores created
before the copies into physregs are done.  This avoids having flag operands
skip the store, causing cycles in the dag at sched time.  This fixes infinite
loops on these tests:

test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828

llvm-svn: 36547
2007-04-28 21:12:06 +00:00
Chris Lattner de339fa55d eliminate more redundant constraint type analysis
llvm-svn: 36546
2007-04-28 21:03:16 +00:00
Chris Lattner b2e55562ed merge constraint type analysis stuff together.
llvm-svn: 36545
2007-04-28 21:01:43 +00:00
Chris Lattner d7e3b6c442 Significant refactoring of the inline asm stuff, to support future changes.
No functionality change.

llvm-svn: 36544
2007-04-28 20:49:53 +00:00
Anton Korobeynikov b18f8f85e9 Implement review feedback. Aliasees can be either GlobalValue's or
bitcasts of them.

llvm-svn: 36537
2007-04-28 13:45:00 +00:00
Chris Lattner 1deacd61f4 memory inputs to an inline asm are required to have an address available.
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.

This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

llvm-svn: 36536
2007-04-28 06:42:38 +00:00
Chris Lattner d102ed0ac6 Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

llvm-svn: 36534
2007-04-28 06:08:13 +00:00
Chris Lattner 4df3e8093b Fix this to match change to InlineAsm class.
llvm-svn: 36524
2007-04-28 04:05:59 +00:00
Chris Lattner 1cbe208cda Fix incorrect legalization of EHSELECTOR. This fixes
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326

llvm-svn: 36510
2007-04-27 17:12:52 +00:00
Evan Cheng bf535fc8bd Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available.
llvm-svn: 36501
2007-04-27 07:33:31 +00:00
Chris Lattner 784fe9dbbb improve EH global handling, patch by Duncan Sands.
llvm-svn: 36499
2007-04-27 01:20:11 +00:00
Chris Lattner 8131ab7c0f enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap
successfully! woohoo...

llvm-svn: 36496
2007-04-26 21:09:43 +00:00
Anton Korobeynikov d7ae7f1659 Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32
llvm-svn: 36490
2007-04-26 20:44:04 +00:00
Dan Gohman e131e3ac02 Fix a typo in a comment.
llvm-svn: 36485
2007-04-26 19:40:56 +00:00
Evan Cheng 910c80851e Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
Evan Cheng ed23a1387e Minor bug.
llvm-svn: 36473
2007-04-26 08:24:22 +00:00
Evan Cheng 43a17fe826 Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation.
llvm-svn: 36458
2007-04-26 01:40:09 +00:00
Evan Cheng 0ba174534c Match MachineFunction::UsedPhysRegs changes.
llvm-svn: 36452
2007-04-25 22:13:27 +00:00
Evan Cheng d21968d11a Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.
llvm-svn: 36451
2007-04-25 22:10:09 +00:00
Evan Cheng d4549c5527 Clean up.
llvm-svn: 36449
2007-04-25 21:34:08 +00:00
Evan Cheng 0fbe14ab87 Data structure change to improve compile time (especially in debug mode).
llvm-svn: 36447
2007-04-25 19:34:00 +00:00
Evan Cheng 15f269afa3 This was lefted out. Fixed sumarray-dbl.
llvm-svn: 36445
2007-04-25 18:33:21 +00:00
Anton Korobeynikov a97b694c82 Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part
will follow.

llvm-svn: 36435
2007-04-25 14:27:10 +00:00
Evan Cheng 7818c03c6b Fix for PR1306.
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434
2007-04-25 07:30:23 +00:00
Evan Cheng 11dc5abde1 Clean up.
llvm-svn: 36431
2007-04-25 07:18:20 +00:00
Chris Lattner b975bebec1 support for >4G stack frames
llvm-svn: 36425
2007-04-25 04:30:24 +00:00
Chris Lattner 9bd98ea4c1 support > 4G stack objects
llvm-svn: 36422
2007-04-25 04:20:54 +00:00
Chris Lattner cb0ed0cfbd allow support for 64-bit stack objects
llvm-svn: 36420
2007-04-25 04:08:28 +00:00
Chris Lattner 01a26c74ae Be more careful about folding op(x, undef) when we have vector operands.
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413
2007-04-25 00:00:45 +00:00
Bill Wendling 47917b697f Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case.

llvm-svn: 36402
2007-04-24 21:13:23 +00:00
Scott Michel 4cfa616cee Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about
tests always being true in the process.

llvm-svn: 36387
2007-04-24 01:24:20 +00:00
Dale Johannesen 8653d29b45 modify per review commentary
llvm-svn: 36383
2007-04-23 23:33:31 +00:00
Dale Johannesen 14a28f13c8 make EmitAlignment work the way Chris says it should
llvm-svn: 36368
2007-04-23 19:58:54 +00:00
Christopher Lamb 8af6d5896f PR400 phase 2. Propagate attributed load/store information through DAGs.
llvm-svn: 36356
2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio 4e91908f17 X86 TLS: Implement review feedback.
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
Reid Spencer 0c1349e6bc Revert Christopher Lamb's load/store alignment changes.
llvm-svn: 36309
2007-04-21 18:36:27 +00:00
Christopher Lamb bff50208c8 add support for alignment attributes on load/store instructions
llvm-svn: 36301
2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio 94314be0e0 Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
llvm-svn: 36290
2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio 2518889872 Implement "general dynamic", "initial exec" and "local exec" TLS models for
X86 32 bits.

llvm-svn: 36283
2007-04-20 21:38:10 +00:00
Evan Cheng 4c53d321aa VarInfo::UsedBlocks is no longer used. Remove.
llvm-svn: 36250
2007-04-18 05:04:38 +00:00
Chris Lattner f03c90bee6 allow SRL to simplify its operands, as it doesn't demand all bits as input.
llvm-svn: 36245
2007-04-18 03:06:49 +00:00
Chris Lattner bf14f20632 When replacing a node in SimplifyDemandedBits, if the old node used any
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
2007-04-18 03:05:22 +00:00
Chris Lattner 15c1b820cc fix a pasto
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
Evan Cheng b408e8f11d Don't populate TryAgainList when coalescing only physical registers with virtual registers.
llvm-svn: 36240
2007-04-18 02:30:19 +00:00
Evan Cheng a5a0c7c909 Increment use count of new virtuals created during PHI elimination.
llvm-svn: 36233
2007-04-18 00:36:11 +00:00
Chris Lattner 4aff52bf3d Fix a bug in my previous patch, grabbing the shift amount width from the
wrong operand.

llvm-svn: 36223
2007-04-17 22:53:02 +00:00
Chris Lattner 9a861a8550 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221
2007-04-17 21:14:16 +00:00
Evan Cheng b881bdabd9 Copy coalescing change to prevent a physical register from being pin to a
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218
2007-04-17 20:32:26 +00:00
Evan Cheng 57b5214d59 Add a register allocation preference field; add a method to compute size of a live interval.
llvm-svn: 36216
2007-04-17 20:25:11 +00:00
Evan Cheng 8387cf1100 Keep track of number of uses within the function per virtual register.
llvm-svn: 36214
2007-04-17 20:22:11 +00:00
Chris Lattner 9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
2007-04-17 19:03:21 +00:00
Reid Spencer 58ec791b4c Fix problems in the PartSet lowering having to do with incorrect bit width.
llvm-svn: 36180
2007-04-16 22:21:14 +00:00
Anton Korobeynikov fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.

llvm-svn: 36146
2007-04-16 18:10:23 +00:00
Chris Lattner 6bd7b7b30b disable switch lowering using shift/and. It still breaks ppc bootstrap for
some reason.  :(  Will investigate.

llvm-svn: 36011
2007-04-14 19:39:41 +00:00
Anton Korobeynikov 8a1a84f96e Fix PR1325: Case range optimization was performed in the case it
shouldn't. Also fix some "latent" bug on 64-bit platforms

llvm-svn: 35990
2007-04-14 13:25:55 +00:00
Chris Lattner 7196f09edc disable shift/and lowering to work around PR1325 for now.
llvm-svn: 35985
2007-04-14 02:26:56 +00:00
Anton Korobeynikov e288040abf Fix PR1323 : we haven't updated phi nodes in good manner :)
llvm-svn: 35963
2007-04-13 06:53:51 +00:00
Reid Spencer 1b9213730f Make sure intrinsics that are lowered to functions make the function weak
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.

llvm-svn: 35956
2007-04-12 21:53:38 +00:00
Reid Spencer 0f2f65f723 Fix bugs in generated code for part_select and part_set so that llc doesn't
barf when CBE is run with a program that contains these intrinsics.

llvm-svn: 35946
2007-04-12 13:30:14 +00:00
Reid Spencer 83faeb7611 Fix a bug in PartSet. The replacement value needs to be zext or trunc to
the size of the value, not just zext. Also, give better names to two BBs.

llvm-svn: 35945
2007-04-12 12:46:33 +00:00
Chris Lattner 5111499136 the result of an inline asm copy can be an arbitrary VT that the register
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll

llvm-svn: 35944
2007-04-12 06:00:20 +00:00
Chris Lattner a77cb3ce68 fold noop vbitconvert instructions
llvm-svn: 35943
2007-04-12 05:58:43 +00:00
Chris Lattner 784a68a702 Fix weirdness handling single element vectors.
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
Reid Spencer c6251a7dfd For PR1284:
Implement the "part_set" intrinsic.

llvm-svn: 35938
2007-04-12 02:48:46 +00:00
Chris Lattner 18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC.
llvm-svn: 35910
2007-04-11 16:51:53 +00:00
Chris Lattner a083ffcad7 Fix this harder.
llvm-svn: 35888
2007-04-11 06:50:51 +00:00
Chris Lattner c5f85d3738 don't create shifts by zero, fix some problems with my previous patch
llvm-svn: 35887
2007-04-11 06:43:25 +00:00
Chris Lattner 65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
2007-04-11 05:32:27 +00:00
Chris Lattner 41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
2007-04-11 05:11:38 +00:00
Reid Spencer a472f66dd0 For PR1146:
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.

llvm-svn: 35877
2007-04-11 02:44:20 +00:00
Chris Lattner f269d84ca0 apparently some people commit without building the tree, or they forget to
commit a LOT of files.

llvm-svn: 35858
2007-04-10 03:20:39 +00:00
Jeff Cohen e0bbbd3774 No longer needed.
llvm-svn: 35850
2007-04-09 23:42:32 +00:00
Chris Lattner 35f0417ec1 remove dead target hooks.
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
Chris Lattner 39f65335d5 remove some dead target hooks, subsumed by isLegalAddressingMode
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
Anton Korobeynikov da964a2852 Use integer log for metric calculation
llvm-svn: 35834
2007-04-09 21:57:03 +00:00
Jeff Cohen 0475f3b4e9 Unbreak VC++ build.
llvm-svn: 35817
2007-04-09 14:32:59 +00:00
Anton Korobeynikov 506eaf7915 Next stage into switch lowering refactoring
1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.

llvm-svn: 35816
2007-04-09 12:31:58 +00:00
Reid Spencer 71b79e3d99 For PR1146:
Adapt handling of parameter attributes to use the new ParamAttrsList class.

llvm-svn: 35814
2007-04-09 06:17:21 +00:00
Chris Lattner 7b2decfa0a implement CodeGen/X86/inline-asm-x-scalar.ll:test3
llvm-svn: 35802
2007-04-09 05:31:20 +00:00
Chris Lattner 18d6718e78 add some assertions
llvm-svn: 35800
2007-04-09 05:23:13 +00:00
Chris Lattner f73d215023 Fix a bug introduced with my previous patch, where it didn't correctly handle
instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll

llvm-svn: 35789
2007-04-09 01:19:33 +00:00
Chris Lattner 0df5357436 Fix CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll and PR1308:
some instructions can have multiple frame indices in them.  If this happens,
rewrite all of them.

llvm-svn: 35785
2007-04-09 00:46:10 +00:00
Chris Lattner b49917da92 Fix PR1316
llvm-svn: 35783
2007-04-09 00:33:58 +00:00
Chris Lattner e55ecfb870 Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
llvm-svn: 35779
2007-04-08 22:23:26 +00:00
Chris Lattner 1c741e95d3 minor comment fix
llvm-svn: 35696
2007-04-06 17:47:14 +00:00
Reid Spencer 85460acfbf Change the bit_part_select (non)implementation from "return 0" to abort.
llvm-svn: 35679
2007-04-05 01:20:18 +00:00
Reid Spencer cce90f55ed Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
llvm-svn: 35678
2007-04-04 23:48:25 +00:00
Anton Korobeynikov 915e61736b Properly emit range comparisons for switch cases, where neighbour cases
go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672
2007-04-04 21:14:49 +00:00
Evan Cheng 8be98c1572 Re-materialize all loads from fixed stack slots.
llvm-svn: 35660
2007-04-04 07:40:01 +00:00
Evan Cheng 2bf2aadd9a Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.
llvm-svn: 35658
2007-04-04 07:04:55 +00:00
Evan Cheng 06a7041ff9 Bad bad bug. findRegisterUseOperand() returns -1 if a use if not found.
llvm-svn: 35618
2007-04-03 06:43:29 +00:00
Scott Michel 16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
2007-04-02 21:36:32 +00:00
Evan Cheng 476fb6a5c9 Ugh. Copy coalescer does not update register numbers.
llvm-svn: 35600
2007-04-02 18:49:18 +00:00
Reid Spencer fad9bd6b92 For PR1297:
Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567
2007-04-02 01:01:49 +00:00
Reid Spencer 6bba6c8143 For PR1297:
Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547
2007-04-01 07:35:23 +00:00
Reid Spencer 3a0843e734 For PR1297:
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546
2007-04-01 07:34:11 +00:00
Reid Spencer a090ffb2ab For PR1297:
Change getOperationName to return std::string instead of const char*

llvm-svn: 35545
2007-04-01 07:32:19 +00:00
Chris Lattner f6a6d3c8b0 move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
llvm-svn: 35529
2007-03-31 04:18:03 +00:00
Chris Lattner f2d71d49e2 switch TL::getValueType to use MVT::getValueType.
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
Chris Lattner bafc837c83 Add a -print-lsr-output option to LLC, to print the output of the LSR pass.
llvm-svn: 35522
2007-03-31 00:24:43 +00:00
Chris Lattner ac3f81508c add one addressing mode description hook to rule them all.
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
Dale Johannesen 4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate
combination.

llvm-svn: 35517
2007-03-30 21:38:07 +00:00
Evan Cheng 9a2a7b174a Don't add the same MI to register reuse "last def/use" twice if it reads the
register more than once.

llvm-svn: 35513
2007-03-30 20:21:35 +00:00
Evan Cheng 48dd5e7d44 Bug fix for PR1279. When isDead is propagate by copy coalescing, we keep length
of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512
2007-03-30 20:18:35 +00:00
Evan Cheng ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
2007-03-29 07:56:46 +00:00
Evan Cheng 86de3a009d New entries.
llvm-svn: 35445
2007-03-29 02:48:56 +00:00
Evan Cheng d771485d89 Notes on re-materialization.
llvm-svn: 35420
2007-03-28 08:30:04 +00:00
Evan Cheng 603e49c6da Move rematerialization out of beta.
llvm-svn: 35419
2007-03-28 08:26:40 +00:00
Evan Cheng 4388043b25 Scale 1 is always ok.
llvm-svn: 35407
2007-03-28 01:55:52 +00:00
Evan Cheng c2cba18f2b Remove isLegalAddressImmediate.
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
Evan Cheng 07c42d43a2 GEP index sinking fixes:
1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403
2007-03-28 01:49:39 +00:00
Evan Cheng b41697c006 Fix for PR1279. Dead def has a live interval of length 1. Copy coalescing should
not violate that.

llvm-svn: 35396
2007-03-28 01:30:37 +00:00
Anton Korobeynikov 37a0bfe128 Remove dead code
llvm-svn: 35380
2007-03-27 12:05:48 +00:00
Anton Korobeynikov 3a9d68181a Split big monster into small helpers. No functionality change.
llvm-svn: 35379
2007-03-27 11:29:11 +00:00
Evan Cheng c42406b5ad SDISel does not preserve all, it changes CFG and other info.
llvm-svn: 35376
2007-03-27 00:53:36 +00:00
Evan Cheng fdbdf43632 Don't call getOperandConstraint() if operand index is greater than
TID->numOperands.

llvm-svn: 35375
2007-03-27 00:48:28 +00:00
Evan Cheng 4a09b1b5be Fix for PR1266. Don't mark a two address operand IsKill.
llvm-svn: 35365
2007-03-26 22:40:42 +00:00
Evan Cheng ec3ac316e2 Change findRegisterUseOperand() to return operand index instead.
llvm-svn: 35363
2007-03-26 22:37:45 +00:00
Dale Johannesen fd18a0cdf4 Fix reversed logic in getRegsUsed. Rename RegStates to RegsAvailable to
hopefully forestall similar errors.

llvm-svn: 35362
2007-03-26 22:23:54 +00:00
Evan Cheng 8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
llvm-svn: 35350
2007-03-26 07:12:51 +00:00
Anton Korobeynikov 7037826c86 First step of switch lowering refactoring: perform worklist-driven
strategy, emit JT's where possible.

llvm-svn: 35338
2007-03-25 15:07:15 +00:00
Chris Lattner 77f0479833 Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332
2007-03-25 05:00:54 +00:00
Chris Lattner 3d7efa2586 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
Chris Lattner 843e44503c Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
Chris Lattner d685514e2e switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter.  No functionality change.

llvm-svn: 35322
2007-03-25 02:14:49 +00:00
Chris Lattner 2a991268f7 don't rely on ADL
llvm-svn: 35299
2007-03-24 17:37:03 +00:00
Evan Cheng b7051f596a Adjust offset to compensate for big endian machines.
llvm-svn: 35293
2007-03-24 00:02:43 +00:00
Evan Cheng a883b58caf Make sure SEXTLOAD of the specific type is supported on the target.
llvm-svn: 35289
2007-03-23 22:13:36 +00:00
Evan Cheng e2f5f24e8e Also replace uses of SRL if that's also folded during ReduceLoadWidth().
llvm-svn: 35286
2007-03-23 20:55:21 +00:00
Evan Cheng a824e79f06 A couple of bug fixes for reducing load width xform:
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274
2007-03-23 02:16:52 +00:00
Dan Gohman dcb291faa4 Change uses of Function::front to Function::getEntryBlock for readability.
llvm-svn: 35265
2007-03-22 16:38:57 +00:00
Evan Cheng 464dc9b74c More opportunities to reduce load size.
llvm-svn: 35254
2007-03-22 01:54:19 +00:00
Evan Cheng a20815e157 Fix for PR1257. Bug in live range shortening as a result of copy coalescing
where the destination is dead.

llvm-svn: 35252
2007-03-22 01:26:05 +00:00
Dale Johannesen 0c6bb5eab7 repair x86 performance, dejagnu problems from previous change
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
Evan Cheng d63baead9b fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
llvm-svn: 35239
2007-03-21 20:14:05 +00:00
Evan Cheng 3578dd61c6 Potential spiller improvement.
llvm-svn: 35228
2007-03-20 22:22:38 +00:00
Dale Johannesen bacf4acf65 do not share old induction variables when this would result in invalid
instructions (that would have to be split later)

llvm-svn: 35227
2007-03-20 21:54:54 +00:00
Dale Johannesen d05a1a2ade maintain LiveIn when splitting blocks (register scavenging needs it)
llvm-svn: 35226
2007-03-20 21:35:06 +00:00
Jeff Cohen 1baf5c84ab Fix some VC++ warnings.
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
Lauro Ramos Venancio 971aa18867 Code clean up.
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
Evan Cheng 550cf0369c Minor bug.
llvm-svn: 35219
2007-03-20 19:32:11 +00:00
Lauro Ramos Venancio 25878b45f5 CopyToReg source operand can be a physical register.
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
Evan Cheng 0e3278e505 First cut trivial re-materialization support.
llvm-svn: 35208
2007-03-20 08:13:50 +00:00
Evan Cheng 25d00d545d Remove -reduce-joining-phys-regs options. Make it on by default.
llvm-svn: 35165
2007-03-19 18:08:26 +00:00
Evan Cheng c5e74f6404 Minor bug fix.
llvm-svn: 35153
2007-03-19 04:22:35 +00:00
Evan Cheng d8f2e4fe4c - Merge UsedBlocks info after two virtual registers are coalesced.
- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141
2007-03-18 09:05:55 +00:00
Evan Cheng 5382426577 Keep UsedBlocks info accurate.
llvm-svn: 35140
2007-03-18 09:02:31 +00:00
Evan Cheng f6f043332f Track the BB's where each virtual register is used.
llvm-svn: 35135
2007-03-17 09:29:54 +00:00
Evan Cheng 7b2a001669 Joining a live interval of a physical register with a virtual one can turn out
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134
2007-03-17 09:27:35 +00:00
Evan Cheng a2465dfc07 Use SmallSet instead of std::set.
llvm-svn: 35133
2007-03-17 08:53:30 +00:00
Evan Cheng be22235790 If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.

llvm-svn: 35132
2007-03-17 08:22:49 +00:00
Evan Cheng c5bc763f50 Turn on GEP index sinking by default.
llvm-svn: 35127
2007-03-16 18:32:30 +00:00
Evan Cheng 0a9d0cabaf Stupid bug.
llvm-svn: 35126
2007-03-16 17:50:20 +00:00
Evan Cheng 009ea54262 Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
2007-03-16 08:46:27 +00:00
Evan Cheng a2a2fd1e55 Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

llvm-svn: 35121
2007-03-16 08:42:32 +00:00
Evan Cheng 88de94a4fb Debugging output stuff.
llvm-svn: 35117
2007-03-15 21:19:28 +00:00
Evan Cheng b9e3db67fb Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
2007-03-14 22:43:40 +00:00
Evan Cheng 2874855302 Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
2007-03-13 23:25:11 +00:00
Evan Cheng b7004fd889 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
Evan Cheng df7949a8d0 If a virtual register is already marked alive in this block, that means it is
alive in one of the successor block. Do not add it to the kill list.

llvm-svn: 35041
2007-03-09 09:48:56 +00:00