Commit Graph

3325 Commits

Author SHA1 Message Date
Harlan Haskins 8d323d1506 [clang] Adopt new FileManager error-returning APIs
Update the callers of FileManager::getFile and FileManager::getDirectory to handle the new llvm::ErrorOr-returning methods.

Signed-off-by: Harlan Haskins <harlan@apple.com>
llvm-svn: 367616
2019-08-01 21:31:56 +00:00
Harlan Haskins 461f0722dd [clang] Adopt llvm::ErrorOr in FileManager methods
Previously, the FileManager would use NULL returns to signify whether a file existed, but that doesn’t cover permissions issues or anything else that might occur while trying to stat or read a file. Instead, convert getFile and getDirectory into returning llvm::ErrorOr

Signed-off-by: Harlan Haskins <harlan@apple.com>
llvm-svn: 367615
2019-08-01 21:31:49 +00:00
Serge Pavlov 3c26163d1a [Parser] Use special definition for pragma annotations
Previously pragma annotation tokens were described as any other
annotations in TokenKinds.def. This change introduces special macro
PRAGMA_ANNOTATION for the pragma descriptions. It allows implementing
checks that deal with pragma annotations only.

Differential Revision: https://reviews.llvm.org/D65405

llvm-svn: 367575
2019-08-01 15:15:10 +00:00
Sam Elliott f46d413fa0 [RISCV] Add FreeBSD targets
Reviewers: asb

Reviewed By: asb

Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste, kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D57795

Patch by James Clarke (jrtc27)

llvm-svn: 367557
2019-08-01 13:14:30 +00:00
Momchil Velikov a36d31478c [AArch64] Add support for Transactional Memory Extension (TME)
Re-commit r366322 after some fixes

TME is a future architecture technology, documented in

  https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
  https://developer.arm.com/docs/ddi0601/a

More about the future architectures:

  https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture

This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and
TCANCEL and the target feature/arch extension "tme".

It also implements TME builtin functions, defined in ACLE Q2 2019
(https://developer.arm.com/docs/101028/latest)

Differential Revision: https://reviews.llvm.org/D64416

Patch by Javed Absar and Momchil Velikov

llvm-svn: 367428
2019-07-31 12:52:17 +00:00
Sam Elliott 9e6b2e1605 [RISCV] Support 'f' Inline Assembly Constraint
Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

Reviewers: asb, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65500

llvm-svn: 367403
2019-07-31 09:45:55 +00:00
Simon Cook 7deaeee753 [RISCV] Add support for floating point registers in inlineasm
This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.

Differential Revision: https://reviews.llvm.org/D64737

llvm-svn: 367399
2019-07-31 09:12:00 +00:00
Rainer Orth b9f8ab2c7e [Driver] Define _FILE_OFFSET_BITS=64 on Solaris
make check-all currently fails on x86_64-pc-solaris2.11 when building with GCC 9:

  Undefined                       first referenced
   symbol                             in file
  _ZN11__sanitizer14internal_lseekEimi SANITIZER_TEST_OBJECTS.sanitizer_libc_test.cc.i386.o
  _ZN11__sanitizer23MapWritableFileToMemoryEPvmim SANITIZER_TEST_OBJECTS.sanitizer_libc_test.cc.i386.o
  ld: fatal: symbol referencing errors
  clang-9: error: linker command failed with exit code 1 (use -v to see invocation)
  make[3]: *** [projects/compiler-rt/lib/sanitizer_common/tests/CMakeFiles/TSanitizer-i386-Test.dir/build.make:92: projects/compiler-rt/lib/sanitizer_common/tests/Sanitizer-i386-Test] Error 1

While e.g. __sanitizer::internal_lseek is defined in sanitizer_solaris.cc, g++ 9
predefines _FILE_OFFSET_BITS=64 while clang++ currently does not.

This patch resolves this inconsistency by following the gcc lead, which allows
make check-all to finish successfully.

There's one caveat: gcc defines _LARGEFILE_SOURCE and _LARGEFILE64_SOURCE for C++ only, while clang has long been doing it for
all languages.  I'd like to keep it this way because those macros do is to make
declarations of fseek/ftello (_LARGEFILE_SOURCE) resp. the 64-bit versions
of largefile functions (*64 with _LARGEFILE64_SOURCE) visible additionally.
However, _FILE_OFFSET_BITS=64 changes all affected functions to be largefile-aware.
I'd like to restrict this to C++, just like gcc does.

To avoid a similar inconsistence with host compilers that don't predefine _FILE_OFFSET_BITS=64
(e.g. clang < 9, gcc < 9), this needs a compantion patch https://reviews.llvm.org/D64483.

Tested on x86_64-pc-solaris2.11.

Differential Revision: https://reviews.llvm.org/D64482

llvm-svn: 367305
2019-07-30 10:38:41 +00:00
Sander de Smalen 405c999d97 [AArch64] Disable __ARM_FEATURE_SVE without ACLE.
The Arm C Language Extensions for SVE document specifies that 
__ARM_FEATURE_SVE should be set when the compiler supports SVE and
implements all the extensions described in the document.

This is currently not yet the case, so the feature should be disabled
until the compiler can provide all the extensions as described.

Reviewers: c-rhodes, rengolin, rovka, ktkachov

Reviewed By: rengolin

Differential Revision: https://reviews.llvm.org/D65404

llvm-svn: 367301
2019-07-30 10:14:39 +00:00
Petr Hosek 92a2e1bbb9 Revert "[ARM] Set default alignment to 64bits"
This reverts commit r367119.

This broke several bots:

http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/26891/steps/ninja%20check%201/logs/FAIL%3A%20Clang%3A%3Aexception-alignment.cpp
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/245/consoleFull

llvm-svn: 367166
2019-07-27 01:59:23 +00:00
Simi Pallipurath 92363a3ada [ARM] Set default alignment to 64bits
The maximum alignment used by ARM arch
is 64bits, not 128.

This could cause overaligned memory
access for 128 bit neon vector that
have unpredictable behaviour.

This fixes: https://bugs.llvm.org/show_bug.cgi?id=42668

Patch by: Diogo Sampaio(diogo.sampaio@arm.com)

Differential Revision: https://reviews.llvm.org/D65000

Change-Id: I5a62b766491f15dd51e4cfe6625929db897f67e3
llvm-svn: 367119
2019-07-26 15:05:19 +00:00
Erich Keane 393094859e Remove CallingConvMethodType
This seems to be an old vestage of a previous implementation of getting
the default calling convention, and everything is now using
CXXABI/ASTContext's getDefaultCallingConvention.  Remove it, since it
isn't doing anything.

llvm-svn: 367039
2019-07-25 17:14:45 +00:00
Sjoerd Meijer a19f5a76e6 Test commit. NFC.
Removed 2 trailing whitespaces in 2 files that used to be in different
repos to test my new github monorepo workflow.

llvm-svn: 366904
2019-07-24 13:30:36 +00:00
Sander de Smalen 2b290885d9 [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list
Adds the SVE vector and predicate registers to the list of known registers.

Patch by Kerry McLaughlin.

Reviewers: erichkeane, sdesmalen, rengolin

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D64739

llvm-svn: 366878
2019-07-24 08:42:34 +00:00
Rainer Orth 2da6eea07c [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARC
Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC:

  error: 'error' diagnostics seen but not expected: 
    File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' ""
  1 error generated.

This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8
(which uses the default of 64 bits).  gcc's sparc/sparc.h has

  #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)

This patch sets SuitableAlign to match and updates the corresponding testcase.

Tested on sparcv9-sun-solaris2.11.

Differential Revision: https://reviews.llvm.org/D64487

llvm-svn: 366820
2019-07-23 16:24:00 +00:00
Sunil Srivastava f4038e75d2 Disallow most calling convention attributes on PS4
PS4 now only allows "cdecl", and its equivalent on PS4, "sysv_abi".

Differential Revision: https://reviews.llvm.org/D64780

llvm-svn: 366617
2019-07-19 21:38:34 +00:00
Alex Bradbury e078967adf [RISCV] Hard float ABI support
The RISC-V hard float calling convention requires the frontend to:

* Detect cases where, once "flattened", a struct can be passed using
int+fp or fp+fp registers under the hard float ABI and coerce to the
appropriate type(s)
* Track usage of GPRs and FPRs in order to gate the above, and to
determine when signext/zeroext attributes must be added to integer
scalars

This patch attempts to do this in compliance with the documented ABI,
and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
author of that code I've tagged you as reviewer for initial feedback on
my usage.

Note that a previous version of the ABI indicated that when passing an
int+fp struct using a GPR+FPR, the int would need to be sign or
zero-extended appropriately. GCC never did this and the ABI was changed,
which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
handle sign/zero-extension attributes.

Re-landed after backing out 366450 due to missed hunks.

Differential Revision: https://reviews.llvm.org/D60456

llvm-svn: 366480
2019-07-18 18:29:59 +00:00
Alex Bradbury 9b732fe99b Revert "[RISCV] Hard float ABI support" r366450
The commit was missing a few hunks. Will fix and recommit.

llvm-svn: 366454
2019-07-18 16:13:17 +00:00
Alex Bradbury fc3aa2ab48 [RISCV] Hard float ABI support
The RISC-V hard float calling convention requires the frontend to:

* Detect cases where, once "flattened", a struct can be passed using
int+fp or fp+fp registers under the hard float ABI and coerce to the
appropriate type(s) * Track usage of GPRs and FPRs in order to gate the
above, and to
determine when signext/zeroext attributes must be added to integer
scalars

This patch attempts to do this in compliance with the documented ABI,
and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as
author of that code I've tagged you as reviewer for initial feedback on
my usage.

Note that a previous version of the ABI indicated that when passing an
int+fp struct using a GPR+FPR, the int would need to be sign or
zero-extended appropriately. GCC never did this and the ABI was changed,
which makes life easier as ABIArgInfo::CoerceAndExpand can't currently
handle sign/zero-extension attributes.

Differential Revision: https://reviews.llvm.org/D60456

llvm-svn: 366450
2019-07-18 15:33:41 +00:00
Momchil Velikov 0e2b74a2b0 Revert [AArch64] Add support for Transactional Memory Extension (TME)
This reverts r366322 (git commit 4b8da3a503)

llvm-svn: 366355
2019-07-17 17:43:32 +00:00
Momchil Velikov 4b8da3a503 [AArch64] Add support for Transactional Memory Extension (TME)
TME is a future architecture technology, documented in

https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
https://developer.arm.com/docs/ddi0601/a

More about the future architectures:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture

This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and
TCANCEL and the target feature/arch extension "tme".

It also implements TME builtin functions, defined in ACLE Q2 2019
(https://developer.arm.com/docs/101028/latest)

Patch by Javed Absar and Momchil Velikov

Differential Revision: https://reviews.llvm.org/D64416

llvm-svn: 366322
2019-07-17 13:23:27 +00:00
Momchil Velikov e14cfe2d2e [AArch64] Consistent types and naming for AArch64 target features (NFC)
Differential Revision: https://reviews.llvm.org/D64415

Committed as obvious.

llvm-svn: 366315
2019-07-17 11:24:37 +00:00
Kyrylo Tkachov eb72138340 [AArch64] Implement __jcvt intrinsic from Armv8.3-A
The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined.

This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function.
The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used.
I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example).

make check-all didn't show any new failures.

[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

Differential Revision: https://reviews.llvm.org/D64495

llvm-svn: 366197
2019-07-16 09:27:39 +00:00
Rui Ueyama 49a3ad21d6 Fix parameter name comments using clang-tidy. NFC.
This patch applies clang-tidy's bugprone-argument-comment tool
to LLVM, clang and lld source trees. Here is how I created this
patch:

$ git clone https://github.com/llvm/llvm-project.git
$ cd llvm-project
$ mkdir build
$ cd build
$ cmake -GNinja -DCMAKE_BUILD_TYPE=Debug \
    -DLLVM_ENABLE_PROJECTS='clang;lld;clang-tools-extra' \
    -DCMAKE_EXPORT_COMPILE_COMMANDS=On -DLLVM_ENABLE_LLD=On \
    -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ ../llvm
$ ninja
$ parallel clang-tidy -checks='-*,bugprone-argument-comment' \
    -config='{CheckOptions: [{key: StrictMode, value: 1}]}' -fix \
    ::: ../llvm/lib/**/*.{cpp,h} ../clang/lib/**/*.{cpp,h} ../lld/**/*.{cpp,h}

llvm-svn: 366177
2019-07-16 04:46:31 +00:00
Nico Weber a2dcbd3643 Use a unique_ptr instead of manual memory management for LineTable
llvm-svn: 366088
2019-07-15 17:27:46 +00:00
Nico Weber 05489f0952 Use a unique_ptr instead of manual memory management for CustomDiagInfo
llvm-svn: 366085
2019-07-15 17:20:34 +00:00
Fangrui Song 6bd02a442c [PowerPC] Support -mabi=ieeelongdouble and -mabi=ibmlongdouble
gcc PowerPC supports 3 representations of long double:

* -mlong-double-64

  long double has the same representation of double but is mangled as `e`.
  In clang, this is the default on AIX, FreeBSD and Linux musl.

* -mlong-double-128

  2 possible 128-bit floating point representations:

  + -mabi=ibmlongdouble
    IBM extended double format. Mangled as `g`
    In clang, this is the default on Linux glibc.
  + -mabi=ieeelongdouble
    IEEE 754 quadruple-precision format. Mangled as `u9__ieee128` (`U10__float128` before gcc 8.2)
    This is currently unavailable.

This patch adds -mabi=ibmlongdouble and -mabi=ieeelongdouble, and thus
makes the IEEE 754 quadruple-precision long double available for
languages supported by clang.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D64283

llvm-svn: 366044
2019-07-15 07:25:11 +00:00
JF Bastien fff5dc0b17 Support __seg_fs and __seg_gs on x86
Summary:
GCC supports named address spaces macros:
  https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html

clang does as well with address spaces:
  https://clang.llvm.org/docs/LanguageExtensions.html#memory-references-to-specified-segments

Add the __seg_fs and __seg_gs macros for compatibility with GCC.

<rdar://problem/52944935>

Subscribers: jkorous, dexonsmith, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64676

llvm-svn: 366028
2019-07-14 18:33:51 +00:00
Sylvestre Ledru 21a92a8a55 This reverts commit 632a36bfcfc8273c1861f04ff6758d863c47c784.
Some targets such as Python 2.7.16 still use VERSION in
their builds. Without VERSION defined, the source code
has syntax errors.

Reverting as it will probably break many other things.

Noticed by Sterling Augustine

llvm-svn: 365992
2019-07-13 06:27:35 +00:00
Sylvestre Ledru 603580216f Remove __VERSION__
Summary:
It has been introduced in 2011 for gcc compat:
ad1a4c6e89
it is probably time to remove it


Reviewers: rnk, dexonsmith

Reviewed By: rnk

Subscribers: dschuff, aheejin, fedor.sergeev, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64062

llvm-svn: 365962
2019-07-12 21:45:08 +00:00
Ulrich Weigand b98bf60ef7 [SystemZ] Add support for new cpu architecture - arch13
This patch series adds support for the next-generation arch13
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10303.

Note: No currently available Z system supports the arch13
architecture.  Once new systems become available, the
official system name will be added as supported -march name.

llvm-svn: 365933
2019-07-12 18:14:51 +00:00
Fangrui Song c46d78d1b7 [X86][PowerPC] Support -mlong-double-128
This patch makes the driver option -mlong-double-128 available for X86
and PowerPC. The CC1 option -mlong-double-128 is available on all targets
for users to test on unsupported targets.

On PowerPC, -mlong-double-128 uses the IBM extended double format
because we don't support -mabi=ieeelongdouble yet (D64283).

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D64277

llvm-svn: 365866
2019-07-12 02:32:15 +00:00
Yaxun Liu 6add24adaf [HIP] Add GPU arch gfx1010, gfx1011, and gfx1012
Differential Revision: https://reviews.llvm.org/D64364

llvm-svn: 365799
2019-07-11 17:50:09 +00:00
Reid Kleckner 8777df5270 De-templatize non-dependent VS macro logic, NFC
These macro definitions don't depend on the template parameter, so they
don't need to be part of the template. Move them to a .cpp file.

llvm-svn: 365556
2019-07-09 20:57:28 +00:00
Stanislav Mekhanoshin 0cfd75a07d [AMDGPU] gfx908 clang target
Differential Revision: https://reviews.llvm.org/D64430

llvm-svn: 365528
2019-07-09 18:19:00 +00:00
Fangrui Song 04615341e4 [ItaniumMangle] Refactor long double/__float128 mangling and fix the mangled code
In gcc PowerPC, long double has 3 mangling schemes:

-mlong-double-64: `e`
-mlong-double-128 -mabi=ibmlongdouble: `g`
-mlong-double-128 -mabi=ieeelongdouble: `u9__ieee128` (gcc <= 8.1: `U10__float128`)

The current useFloat128ManglingForLongDouble() bisection is not suitable
when we support -mlong-double-128 in clang (D64277). Replace
useFloat128ManglingForLongDouble() with getLongDoubleMangling() and
getFloat128Mangling() to allow 3 mangling schemes.

I also deleted the `getTriple().isOSBinFormatELF()` check (the Darwin
support has gone: https://reviews.llvm.org/D50988).

For x86, change the mangled code of __float128 from `U10__float128` to `g`. `U10__float128` was wrongly copied from PowerPC.
The test will be added to `test/CodeGen/x86-long-double.cpp` in D64277.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D64276

llvm-svn: 365480
2019-07-09 13:32:26 +00:00
Fangrui Song 11cb39c5fc [X86][PPC] Support -mlong-double-64
-mlong-double-64 is supported on some ports of gcc (i386, x86_64, and ppc{32,64}).
On many other targets, there will be an error:

    error: unrecognized command line option '-mlong-double-64'

This patch makes the driver option -mlong-double-64 available for x86
and ppc. The CC1 option -mlong-double-64 is available on all targets for
users to test on unsupported targets.

LongDoubleSize is added as a VALUE_LANGOPT so that the option can be
shared with -mlong-double-128 when we support it in clang.

Also, make powerpc*-linux-musl default to use 64-bit long double. It is
currently the only supported ABI on musl and is also how people
configure powerpc*-linux-musl-gcc.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D64067

llvm-svn: 365412
2019-07-09 00:27:43 +00:00
Alex Bradbury 77d4a8f9f7 [RISCV] Specify registers used for exception handling
Implements the handling of __builtin_eh_return_regno().

Differential Revision: https://reviews.llvm.org/D63417
Patch by Edward Jones.

llvm-svn: 365305
2019-07-08 09:38:06 +00:00
Fangrui Song 1f333562de [PowerPC] Support constraint code "ww"
Summary:
"ww" and "ws" are both constraint codes for VSX vector registers that
hold scalar double data. "ww" is preferred for float while "ws" is
preferred for double.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D64119

llvm-svn: 365106
2019-07-04 04:44:42 +00:00
Simon Pilgrim a372bb21c3 Fix MSVC "signed/unsigned mismatch" warning. NFCI.
Fixes PR42426.

llvm-svn: 365019
2019-07-03 10:26:28 +00:00
Fangrui Song 7264a474b7 Change std::{lower,upper}_bound to llvm::{lower,upper}_bound or llvm::partition_point. NFC
llvm-svn: 365006
2019-07-03 08:13:17 +00:00
Yaxun Liu d325eb3b56 Fix build failure due to missing break
llvm-svn: 364380
2019-06-26 03:33:03 +00:00
Simon Tatham e8de8ba6a6 [ARM] Support inline assembler constraints for MVE.
"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.

Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60709

llvm-svn: 364331
2019-06-25 16:49:32 +00:00
Matt Arsenault fc84925208 AMDGPU: Fix target builtins for gfx10
This wasn't setting some of the features from older generations.

llvm-svn: 364123
2019-06-22 01:30:00 +00:00
Richard Smith 979ae80af7 PR42301: Abort cleanly if we encounter a huge source file rather than
crashing.

Ideally we wouldn't care about the size of a file so long as it fits in
memory, but in practice we have lots of hardocded assumptions that
unsigned can be used to index files, string literals, and so on.

llvm-svn: 364103
2019-06-21 20:46:22 +00:00
Lewis Revill af22e071ca [RISCV] Mark TLS as supported
Inform Clang that TLS is implemented by LLVM for RISC-V

Differential Revision: https://reviews.llvm.org/D57055

llvm-svn: 363776
2019-06-19 08:53:46 +00:00
Rainer Orth abccb1ad89 Clang :: Sema/wchar.c has long been failing on Solaris:
error: 'error' diagnostics expected but not seen: 
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: initializing wide char array with non-wide string literal
  error: 'error' diagnostics seen but not expected: 
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 20: array initializer must be an initializer list
    File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: array initializer must be an initializer list

It turns out the definition is wrong, as can be seen in GCC's gcc/config/sol2.h:

  /* wchar_t is called differently in <wchar.h> for 32 and 64-bit
     compilations.  This is called for by SCD 2.4.1, p. 6-83, Figure 6-65
     (32-bit) and p. 6P-10, Figure 6.38 (64-bit).  */
  
  #undef WCHAR_TYPE
  #define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int")

The following patch implements this, and at the same time corrects the wint_t
definition which is the same:

  /* Same for wint_t.  See SCD 2.4.1, p. 6-83, Figure 6-66 (32-bit).  There's
     no corresponding 64-bit definition, but this is what Solaris 8
     <iso/wchar_iso.h> uses.  */
  
  #undef WINT_TYPE
  #define WINT_TYPE (TARGET_64BIT ? "int" : "long int")

Clang :: Preprocessor/wchar_t.c and Clang :: Sema/format-strings.c need to
be adjusted to account for that.

Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11, and x86_64-pc-linux-gnu.

Differential Revision: https://reviews.llvm.org/D62944

llvm-svn: 363612
2019-06-17 20:21:25 +00:00
George Burgess IV 2c074bb39e [Targets] Move soft-float-abi filtering to `initFeatureMap`
ARM has a special target feature called soft-float-abi. This feature is
special, since we get it passed to us explicitly in the frontend, but
filter it out before it can land in any target feature strings in LLVM
IR.

__attribute__((target(""))) doesn't quite filter these features out
properly, so today, we get warnings about soft-float-abi being an
unknown feature from the backend.

This CL has us filter soft-float-abi out at a slightly different point,
so we don't end up passing these invalid features to the backend.

Differential Revision: https://reviews.llvm.org/D61750

llvm-svn: 363346
2019-06-14 00:35:17 +00:00
Stanislav Mekhanoshin cafccd7a53 [AMDGPU] gfx1011/gfx1012 clang support
Differential Revision: https://reviews.llvm.org/D63308

llvm-svn: 363345
2019-06-14 00:33:59 +00:00
Lewis Revill 5665ef3dcc [RISCV] Add inline asm constraints I, J & K for RISC-V
This allows the constraints I, J & K to be used in inline asm for
RISC-V, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Integer zero only.
K: Any 5-bit unsigned immediate.

See the GCC definitions here:
https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

Differential Revision: https://reviews.llvm.org/D54091

llvm-svn: 363055
2019-06-11 12:44:01 +00:00