Commit Graph

11 Commits

Author SHA1 Message Date
Simon Dardis f909058ad4 [mips] Sink PredicateControl further down the class hierarchy.
Previously PredicateControl in some cases was a member of <X>Inst classes
for some X (DSP, EVA) or was in more irregular place in the hierarchry
for any given instruction.

This patch moves PredicateControl down to the root so that it is consistently
available. Then correct the base class of microMIPS instructions as using
EncodingPredicates instead of the general Predicates field of Instruction.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D47526

llvm-svn: 333536
2018-05-30 12:40:53 +00:00
Simon Dardis de5ed0c58e Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the
llvm-clang-x86_64-expensive-checks-win buildbot.

Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

llvm-svn: 318207
2017-11-14 22:26:42 +00:00
Simon Dardis c3f6b2806f Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""
This reverts r310834. It didn't pacify the buildbot, FileCheck is still
crashing.

llvm-svn: 310854
2017-08-14 16:20:33 +00:00
Simon Dardis cbf55deaa1 Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win
buildbot.

Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

llvm-svn: 310834
2017-08-14 12:28:00 +00:00
Simon Dardis 45b2277a33 Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""
FileCheck is crashing on in the input file, so reverting again while
I investigate.

This reverts r308023.

llvm-svn: 308030
2017-07-14 15:08:05 +00:00
Simon Dardis b3529841db Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""
Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

The last version of this patch broke one of the expensive checks buildbots,
this version changes the failing test/MC/Mips/mt/invalid.s and other invalid
tests to write the errors to a file and run FileCheck on that, rather than
relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom.

Hopefully this will sarisfy the buildbot.

llvm-svn: 308023
2017-07-14 13:44:12 +00:00
Simon Dardis 1558ee3365 Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."
This reverts r307836, it broke one of the buildbots. Reverting
while I investigate.

llvm-svn: 307939
2017-07-13 19:27:41 +00:00
Simon Dardis e171a913d6 [mips][mt][6/7] Add support for mftr, mttr instructions.
Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

llvm-svn: 307836
2017-07-12 19:47:45 +00:00
Simon Dardis 76eb647e1e [mips][mt][5/7] Add support for fork and yield instructions.
Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35252

llvm-svn: 307808
2017-07-12 16:23:57 +00:00
Simon Dardis 2de1ddbd9c [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.
Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35251

llvm-svn: 307793
2017-07-12 14:48:27 +00:00
Simon Dardis 7323f7ac63 [mips][mt] Add missing files from last commit
llvm-svn: 307779
2017-07-12 12:33:40 +00:00