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8 Commits

Author SHA1 Message Date
Simon Dardis 5d61c8b225 [mips] Correct the definitions of the unaligned word memory operation instructions 
These instructions lacked the correct predicates, were not marked
as loads and stores and lacked the proper instruction mapping information.

In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load
EVA description.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45626

llvm-svn: 330326
 2018-04-19 13:33:51 +00:00
Simon Dardis 476ed8f26e [mips] Fix the definitions of the EVA instructions 
Correct their availability to their respective ISAs.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D44209

llvm-svn: 327403
 2018-03-13 14:39:44 +00:00
Simon Dardis 1f0fe56460 [mips] Split out ASEPredicate from InsnPredicates (NFC) 
This simplifies tagging instructions with the correct ISA and ASE, albeit making
instruction definitions a bit more verbose.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44299

llvm-svn: 327265
 2018-03-12 13:16:12 +00:00
Aleksandar Beserminji a330c208f2 [mips] Include EVA instructions in Std2MicroMips mapping tables 
This patch includes EVA instructions in the Std2MicroMips mapping
tables, which is required for direct object emission.

Differential Revision: https://reviews.llvm.org/D41771

llvm-svn: 323958
 2018-02-01 12:53:26 +00:00
Simon Dardis e661e528db [mips] MIPS32/64 itineraries 
Itineraries for some pre MIPSR6 and EVA instructions. Some pseudo expanded
instructions are marked as having no scheduling info.

Reviewers: dsanders, vkalintiris

Differential Review: http://reviews.llvm.org/D20418

llvm-svn: 272648
 2016-06-14 09:35:29 +00:00
Daniel Sanders 2e9f69d933 [mips] Range check simm9 and fix a bug this revealed. 
Summary:
The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a
12-bit offset when it is only 9-bit.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18434

llvm-svn: 265010
 2016-03-31 13:15:23 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Daniel Sanders e4e83a7bc1 [mips] Added support for various EVA ASE instructions. 
Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139

llvm-svn: 247669
 2015-09-15 10:02:16 +00:00