a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
fbee8bfe48
Removed unnecessary Mangler creation.
...
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
d1f8e07808
Allow tail duplication in more cases, relaxing the previous restriction a
...
bit. This fixes Regression/Transforms/TailDup/MergeTest.ll
llvm-svn: 30237
2006-09-10 18:17:58 +00:00
2e0dfb0b16
This code was trying too hard. By eliminating redundant edges in the CFG
...
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.
This fixes 458.sjeng on x86 with llc.
llvm-svn: 30236
2006-09-10 06:36:57 +00:00
9a22d7b60f
Replace EquivalenceClasses with a custom-built data structure. Many common
...
operations (like findProperties) should be faster, at the expense of
unionSets being slower in cases that are rare in practise.
Don't erase a dead Instruction. This fixes a memory corruption issue.
llvm-svn: 30235
2006-09-10 02:27:07 +00:00
0468987592
Implement Transforms/InstCombine/hoist_instr.ll
...
llvm-svn: 30234
2006-09-09 22:02:56 +00:00
27ff96d87a
Make inlining costs more accurate.
...
llvm-svn: 30231
2006-09-09 20:40:44 +00:00
d79dc79831
Turn div X, (Cond ? Y : 0) -> div X, Y
...
This implements select.ll::test18.
llvm-svn: 30230
2006-09-09 20:26:32 +00:00
fdb3a75942
Add cbe support for powi
...
llvm-svn: 30226
2006-09-09 06:17:12 +00:00
f0359b343a
Implement the fpowi now by lowering to a libcall
...
llvm-svn: 30225
2006-09-09 06:03:30 +00:00
e4bbb6c341
Allow targets to custom lower expanded BIT_CONVERT's
...
llvm-svn: 30217
2006-09-09 00:20:27 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
de33f66286
Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
...
in addition to immediate operands.
llvm-svn: 30205
2006-09-08 21:08:13 +00:00
b2e7316b2d
Non-allocatable physregs can be killed and dead, but don't treat them as
...
safe for later allocation. This fixes McCat/18-imp with llc-beta.
llvm-svn: 30204
2006-09-08 20:21:31 +00:00
050c64c51d
This fixes Benchmarks/Prolangs-C/unix-smail
...
llvm-svn: 30198
2006-09-08 19:11:11 +00:00
9b1a6ebf20
Fix a bunch of llc-beta failures on x86 yesterday. Don't allow selection
...
of unallocatable registers, just because an alias is allocatable. We were
picking registers like SIL just because ESI was being used.
llvm-svn: 30197
2006-09-08 19:03:30 +00:00
d11fb5d13b
implement shl and sra
...
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
6c003a7c2d
Use __USER_LABEL_PREFIX__ to get the prefix added by the current host.
...
llvm-svn: 30190
2006-09-08 17:03:56 +00:00
4443c7d60a
add the eor (xor) instruction
...
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
177405376c
Missing tab
...
llvm-svn: 30188
2006-09-08 13:06:56 +00:00
778769aafb
implement unconditional branches
...
fix select.ll
llvm-svn: 30186
2006-09-08 12:47:03 +00:00
7348403d42
Remove TEST64mr. It's same as TEST64rm since and is commutative.
...
llvm-svn: 30178
2006-09-08 06:56:55 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
c9db83306f
We actually do support object file writing, so don't return true (error)
...
llvm-svn: 30173
2006-09-08 03:42:15 +00:00
89c5d04b9b
- Identify a vector_shuffle that can be turned into an undef, e.g.
...
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
optimal code by failing to identify MOVL (move to lowest element of a
vector).
llvm-svn: 30171
2006-09-08 01:50:06 +00:00
ae92ce8798
1. Remove condition on delete.
...
2. Protect and outline createTargetAsmInfo.
3. Misc. kruft.
llvm-svn: 30169
2006-09-07 23:39:26 +00:00
0142cd129e
Untabify.
...
llvm-svn: 30168
2006-09-07 23:29:19 +00:00
b8164e6131
Use iterative do-while loop instead of recursive DFSPass calls to
...
reduce amount of stack space used at runtime.
llvm-svn: 30167
2006-09-07 23:22:37 +00:00
2785d55446
add a new value for the command line optn
...
llvm-svn: 30165
2006-09-07 22:32:28 +00:00
b9e0a9e82f
Fix a cross-build issue. The asmsyntax shouldn't be affected by the build
...
host, it should be affected by the target. Allow the command line option to
override in either case.
llvm-svn: 30164
2006-09-07 22:29:41 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
0e83541f8b
Break out target asm info into separate files.
...
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
c465046e65
Throttle back tail duplication to avoid creating really ugly sequences of code.
...
For Transforms/TailDup/if-tail-dup.ll, f.e., it produces:
_foo:
movl 8(%esp), %eax
movl 4(%esp), %ecx
testl $1, %ecx
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%eax)
LBB1_2: #cond_next
testl $2, %ecx
je LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%eax)
LBB1_4: #cond_next10
testl $4, %ecx
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%eax)
LBB1_6: #cond_next18
testl $8, %ecx
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%eax)
ret
LBB1_8: #return
ret
instead of:
_foo:
movl 4(%esp), %eax
testl $2, %eax
sete %cl
movl 8(%esp), %edx
testl $1, %eax
je LBB1_2 #cond_next
LBB1_1: #cond_true
movl $1, (%edx)
testb %cl, %cl
jne LBB1_4 #cond_next10
jmp LBB1_3 #cond_true6
LBB1_2: #cond_next
testb %cl, %cl
jne LBB1_4 #cond_next10
LBB1_3: #cond_true6
movl $1, 4(%edx)
testl $4, %eax
je LBB1_6 #cond_next18
jmp LBB1_5 #cond_true14
LBB1_4: #cond_next10
testl $4, %eax
je LBB1_6 #cond_next18
LBB1_5: #cond_true14
movl $1, 8(%edx)
testl $8, %eax
je LBB1_8 #return
jmp LBB1_7 #cond_true22
LBB1_6: #cond_next18
testl $8, %eax
je LBB1_8 #return
LBB1_7: #cond_true22
movl $1, 12(%edx)
ret
LBB1_8: #return
ret
llvm-svn: 30158
2006-09-07 21:30:15 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
1b7f09cdf7
Some notes on better load folding we could do
...
llvm-svn: 30155
2006-09-07 20:32:01 +00:00
a9411c0977
Consistency.
...
llvm-svn: 30152
2006-09-07 19:03:48 +00:00
95b3dde8bb
Fix pasto that was breaking x86 tests.
...
llvm-svn: 30151
2006-09-07 18:50:20 +00:00
721fc38342
Add new option to leave asm names alone
...
llvm-svn: 30149
2006-09-07 18:20:41 +00:00
c7abe471fe
Make the x86 asm flavor part of the subtarget info.
...
llvm-svn: 30146
2006-09-07 12:23:47 +00:00
707339a57b
Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
...
too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
2006-09-07 01:59:34 +00:00
7f3f0973e6
Clean up.
...
llvm-svn: 30140
2006-09-07 01:17:57 +00:00
4c7a3fbdea
Watch out for variable_ops instructions.
...
llvm-svn: 30135
2006-09-06 20:32:45 +00:00
ac22e54131
Variable ops instructions may ignore the last few operands for code emission.
...
llvm-svn: 30134
2006-09-06 20:24:14 +00:00
ef94ebb666
Oops - forgot to update banner.
...
llvm-svn: 30131
2006-09-06 19:21:41 +00:00
681ecbb3b3
Separate target specifc asm properties from asm printers.
...
llvm-svn: 30127
2006-09-06 18:35:33 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
abd8bcbe5e
add the orr instruction
...
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
ddfb10b5af
Only call isUse/isDef on register operands
...
llvm-svn: 30122
2006-09-05 20:32:06 +00:00
2656932979
Bugfix to work with the two-addr changes that have been made in the tree recently
...
llvm-svn: 30121
2006-09-05 20:27:32 +00:00
2cb238320d
Only call isUse/isDef on register operands
...
llvm-svn: 30118
2006-09-05 20:19:27 +00:00
Nate Begeman