Commit Graph

298397 Commits

Author SHA1 Message Date
Thomas Lively a0d25815a0 [WebAssembly] v8x16.shuffle
Summary:
Since the shuffle mask is not exposed as an operand in the native ISel
DAG, create a new WebAssembly ISD node exposing the mask. The mask is
lowered as sixteen immediate byte indices no matter what type the
original vector shuffle was operating on.

This CL depends on D51656

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51659

llvm-svn: 341718
2018-09-07 21:54:46 +00:00
Reid Kleckner 3a406e5a74 [benchmark] Fix flags used to compile benchmark library with clang-cl
`MSVC` is true for clang-cl, but `"${CMAKE_CXX_COMPILER_ID}" STREQUAL
"MSVC"` is false, so we would enable -Wall, which means -Weverything
with clang-cl, and we get tons of undesired warnings.

Use the simpler condition to fix things.

llvm-svn: 341717
2018-09-07 21:47:25 +00:00
Reid Kleckner 403959e302 [benchmark] Re-enable benchmarks on all platforms including Windows
The assertion in MCCodeView.cpp was resolved in r340878.

This reverts both r340905 and r340836, making benchmarks build by
default everywhere.

llvm-svn: 341716
2018-09-07 21:47:00 +00:00
Sanjay Patel caa4de72a2 [InstCombine][x86] add tests for possible blendv transform (PR38814); NFC
llvm-svn: 341715
2018-09-07 21:40:41 +00:00
Davide Italiano 6af9fe07b9 [Disassembler] Run ARM-specific tests only if the ARM backend is built.
<rdar://problem/44239070>

llvm-svn: 341714
2018-09-07 21:36:21 +00:00
Philip Reames cb8b3278e5 [AST] Generalize argument specific aliasing
AliasSetTracker has special case handling for memset, memcpy and memmove which pre-existed argmemonly on functions and readonly and writeonly on arguments. This patch generalizes it using the AA infrastructure to any call correctly annotated.

The motivation here is to cut down on confusion, not performance per se. For most instructions, there is a direct mapping to alias set. However, this is not guaranteed by the interface and was not in fact true for these three intrinsics *and only these three intrinsics*. I kept getting myself confused about this invariant, so I figured it would be good to clearly distinguish between a instructions and alias sets. Calls happened to be an easy target.

The nice side effect is that custom implementations of memset/memcpy/memmove - including wrappers discovered by IPO - can now be optimized the same as builts by LICM.

Note: The actual removal of the memset/memtransfer specific handling will happen in a follow on NFC patch.  It was originally part of this one, but separate for ease of review and rebase.

Differential Revision: https://reviews.llvm.org/D50730

llvm-svn: 341713
2018-09-07 21:36:11 +00:00
Reid Kleckner 06d02d0306 [codeview] Add .cv_string directive for testing purposes
The main use case for this directive is to allow assembly writers to
write their own FPO data strings without going through the .cv_fpo*
directive family.

I'm experimenting with different RPN programs to fix PR38857, and I
figured I should go ahead and make this directive permanent.

llvm-svn: 341712
2018-09-07 21:30:52 +00:00
Craig Topper fa535c027e [X86] Add codegen tests for narrow PADDUS/PSUBUS patterns for PR38691.
llvm-svn: 341711
2018-09-07 21:28:46 +00:00
Richard Smith edb9fbb78a Make -Watomic-alignment say whether the atomic operation was oversized
or misaligned.

llvm-svn: 341710
2018-09-07 21:24:27 +00:00
Alina Sbirlea f98c2c5e6d [MemorySSA] Update MemoryPhi wiring for block splitting to consider if identical edges were merged.
Summary:
Block splitting is done with either identical edges being merged, or not.
Only critical edges can be split without merging identical edges based on an option.
Teach the memoryssa updater to take this into account: for the same edge between two blocks only move one entry from the Phi in Old to the new Phi in New.

Reviewers: george.burgess.iv

Subscribers: sanjoy, jlebar, Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D51563

llvm-svn: 341709
2018-09-07 21:14:48 +00:00
Sanjay Patel c1416b60f2 [InstCombine] narrow vector select with padded condition and extracted result (PR38691)
shuf (sel (shuf NarrowCond, undef, WideMask), X, Y), undef, NarrowMask) -->
sel NarrowCond, (shuf X, undef, NarrowMask), (shuf Y, undef, NarrowMask)

The motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=38691
...is the last regression test. In that case, we're just left with the narrow select.

Note that if we do create new shuffles, they use the existing extraction identity mask, 
so there's no danger that this transform creates arbitrary shuffles.

Differential Revision: https://reviews.llvm.org/D51496

llvm-svn: 341708
2018-09-07 21:03:34 +00:00
Thomas Lively 653278f801 [WebAssembly] Change SIMD lane indices to vec_i8imm_op
Summary: To explicitly opt out of LEB encoding for these immediates.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51766

llvm-svn: 341707
2018-09-07 20:59:50 +00:00
Nick Desaulniers 287a3be379 [AArch64] Support reserving x1-7 registers.
Summary:
Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.

Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma

Reviewed By: nickdesaulniers, efriedma

Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D48580

llvm-svn: 341706
2018-09-07 20:58:57 +00:00
Craig Topper 5cbce81c91 [X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.
The generic type legalizer will scalarize vXi1 instructions getting rid of the vector entirely. Creating wider vector instructions is just going to prevent that.

llvm-svn: 341705
2018-09-07 20:56:03 +00:00
Craig Topper 39f48fdcbc [X86] Don't create X86ISD::AVG nodes from v1iX vectors.
The type legalizer will try to scalarize this and fail.

It looks like there's some other v1iX oddities out there too since we still generated some vector instructions.

llvm-svn: 341704
2018-09-07 20:56:01 +00:00
Jonathan Peyton 08f0180ba9 [OpenMP] Update copyright to 2018
Better late than never

llvm-svn: 341703
2018-09-07 20:33:35 +00:00
Fangrui Song b3b61de09a [PGO] Fix some style issue of ControlHeightReduction
Reviewers: yamauchi

Reviewed By: yamauchi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51811

llvm-svn: 341702
2018-09-07 20:23:15 +00:00
Alexandre Ganea 00b407c9cd [CMake] Fix LLVM_ENABLE_LTO option on Windows
Differential Revision: https://reviews.llvm.org/D51804

llvm-svn: 341701
2018-09-07 20:07:36 +00:00
Richard Smith 8ed7776bc4 PR38870: Add warning for zero-width unicode characters appearing in
identifiers.

llvm-svn: 341700
2018-09-07 19:25:39 +00:00
Craig Topper ecf2e2fe31 [X86] Custom emit __builtin_rdtscp so we can emit an explicit store for the out parameter
This is the clang side of D51803. The llvm intrinsic now returns two results. So we need to emit an explicit store in IR for the out parameter. This is similar to addcarry/subborrow/rdrand/rdseed.

Differential Revision: https://reviews.llvm.org/D51805

llvm-svn: 341699
2018-09-07 19:14:24 +00:00
Craig Topper 4863313b35 [X86] Modify the the rdtscp intrinsic to return values instead of taking a pointer argument
Similar to what was recently done for addcarry/subborrow and has been done for rdrand/rdseed for a while. It's better to use two results and an explicit store in IR when the store isn't part of the semantics of the instruction. This allows store->load forwarding to happen in the middle end. Or the store to be removed if its never loaded.

Differential Revision: https://reviews.llvm.org/D51803

llvm-svn: 341698
2018-09-07 19:14:15 +00:00
Alex Lorenz 49c2add9fb warn_stdlibcxx_not_found: suggest '-stdlib=libc++' instead of '-std'
Addresses first post-commit feedback for r335081 from Nico

llvm-svn: 341697
2018-09-07 18:59:45 +00:00
Jason Molenda 25a1525e7e Add the Disassembler unit test dir.
llvm-svn: 341696
2018-09-07 18:51:10 +00:00
Reid Kleckner ee0e8bab2a [codeview] Improve readobj FPO dumper and pdbutil register names
The improved dumping helps me investigate PR38857.

llvm-svn: 341695
2018-09-07 18:48:27 +00:00
Jonathan Peyton a2f6eff488 [OpenMP] Change hint parameter type for critical to uint32_t
Add atomic hint flags to the enum.
The hint parameter type was changed to uint32_t in __kmpc_critical_with_hint()

Patch by Olga Malysheva

Differential Revision: https://reviews.llvm.org/D51235

llvm-svn: 341694
2018-09-07 18:46:40 +00:00
Jonathan Peyton 2ff302d5d7 [OpenMP] Synchronization hint constants added to headers
ident flags reserved for atomic hints.
This patch adds omp_sync_hint_t to omp.h and omp_sync_hint_kind to omp_lib.h.
For better maintainability the list of macros for ident flags was replaced with
a enum. The new KMP_IDENT_ATOMIC_HINT_MASK was added to the enum to
support possible future atomic hints.

Also fix omp_lib.h.var to be under 72 chars again after 5.0 OpenMP Memory commit

Patch by Olga Malysheva

Differential Revision: https://reviews.llvm.org/D51233

llvm-svn: 341693
2018-09-07 18:45:13 +00:00
Hiroshi Yamauchi 06650941a2 [PGO][CHR] Build/warning fix
llvm-svn: 341692
2018-09-07 18:44:53 +00:00
Ana Pazos b2ed11a086 [RISCV] Fix crash in decoding instruction with unknown floating point rounding mode
Summary:
Instead of crashing in printFRMArg, decode and warn about invalid instruction.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51705

llvm-svn: 341691
2018-09-07 18:43:43 +00:00
Jim Ingham 4911d36aa6 NFC: Move Searcher::Depth into lldb-enumerations as SearchDepth.
In a subsequent commit, I will need to expose the search depth
to the SB API's, so I'm moving this define into lldb-enumerations
where it will get added to the lldb module.

llvm-svn: 341690
2018-09-07 18:43:04 +00:00
Alexandre Ganea 960324471b [Error] Reintroduce type validation in createFileError()
This prevents from using ErrorSuccess as an argument to createFileError().

Differential Revision: https://reviews.llvm.org/D51490

llvm-svn: 341689
2018-09-07 18:32:59 +00:00
Fangrui Song 91c95a35c1 [llvm-dwp] Clean up tests X86/*.test
llvm-svn: 341688
2018-09-07 18:29:20 +00:00
Jonathan Peyton 92ca61884b [OpenMP] Initial implementation of OMP 5.0 Memory Management routines
Implemented omp_alloc, omp_free, omp_{set,get}_default_allocator entries,
and OMP_ALLOCATOR environment variable.

Added support for HBW memory on Linux if libmemkind.so library is accessible
(dynamic library only, no support for static libraries).
Only used stable API (hbwmalloc) of the memkind library
though we may consider using experimental API in future.

The ICV def-allocator-var is implemented per implicit task similar to
place-partition-var.  In the absence of a requested allocator, the uses the
default allocator.

Predefined allocators (the only ones currently available) are made similar
for C and Fortran, - pointers (long integers) with values 1 to 8.

Patch by Andrey Churbanov

Differential Revision: https://reviews.llvm.org/D51232

llvm-svn: 341687
2018-09-07 18:25:49 +00:00
Ana Pazos b97d18945b [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassembling
Summary:
RISCVDisassembler should check number of bytes available before reading them.
Crash noticed when enabling -DLLVM_USE_SANITIZER=Address.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language.

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51708

llvm-svn: 341686
2018-09-07 18:23:19 +00:00
Davide Italiano f06ffeee21 [Scalar] Commit the correct patch, forgot `git add`.
<rdar://problem/44229924>

llvm-svn: 341685
2018-09-07 18:22:27 +00:00
JF Bastien 7e2dd2d2fa NFC: remove magic bool in LoopIdiomRecognize
Use an enum class instead.

llvm-svn: 341684
2018-09-07 18:17:59 +00:00
Jim Ingham effe60fdbd Add input files to the "prepare swig bindings" step.
This build phase had no inputs, so you always had to manually
delete LLDBWrapPython.cpp to get it to rebuild.  Add the correct
inputs.

llvm-svn: 341683
2018-09-07 18:10:26 +00:00
Davide Italiano 5ccc9df843 [Scalar] Fix undefined behaviour when converting double to long.
This showed up in an Ubsan build of lldb (inside the CFAbsoluteTime
data formatter). As we only care about the bit pattern, we just
round to the nearest double, and truncate to a size that fits
in ulonglong_t.

<rdar://problem/44229924>

llvm-svn: 341682
2018-09-07 18:03:43 +00:00
Hiroshi Yamauchi 5fb509b763 [PGO][CHR] Small cleanup.
Summary:
Do away with demangling. It wasn't really necessary.
Declared some local functions to be static.

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51740

llvm-svn: 341681
2018-09-07 18:00:58 +00:00
Kristina Brooks d8bdf16cfe [Bindings][Go] Fixed go.test failure due to C-API argument type mismatch.
go.test was failing previously with error,
Command Output (stderr):
dibuilder.go:301: cannot use C.uint(t.Encoding) (type C.uint) as type
C.LLVMDWARFTypeEncoding in argument to func literal
This patch fixes the argument type.

Patch by Chirag (Chirag Patel)

Differential Revision: https://reviews.llvm.org/D51721

llvm-svn: 341680
2018-09-07 17:33:43 +00:00
Matthias Braun e2dc692919 utils/abtest: Refactor and add bisection method
- Refactor/rewrite most of the code. Also make sure it passes
  pycodestyle/pyflakes now
- Add a new mode that performs bisection on the search space. This
  should be faster in the common case where there is only a small number
  of files or functions actually leading to failure.
  The previous sequential behavior can still be accessed via `--seq`.

llvm-svn: 341679
2018-09-07 17:08:44 +00:00
Craig Topper 52a61fc2ac [X86] Modify addcarry/subborrow builtins to emit an 2 result and intrinsic and an store instruction.
This is the clang side of D51769. The llvm intrinsics now return two results instead of using an out parameter.

Differential Revision: https://reviews.llvm.org/D51771

llvm-svn: 341678
2018-09-07 16:58:57 +00:00
Craig Topper 72964ae99e [X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument.
We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address.

Differential Revision: https://reviews.llvm.org/D51769

llvm-svn: 341677
2018-09-07 16:58:39 +00:00
Craig Topper 51e11788a4 [X86] Use regular expressions to make test immune to register allocation changes.
llvm-svn: 341676
2018-09-07 16:58:36 +00:00
Craig Topper 313d09af51 [X86] Teach X86DAGToDAGISel::foldLoadStoreIntoMemOperand to handle loads in operand 1 of commutable operations.
Previously we only handled loads in operand 0, but nothing guarantees the load will be operand 0 for commutable operations.

Differential Revision: https://reviews.llvm.org/D51768

llvm-svn: 341675
2018-09-07 16:27:55 +00:00
Craig Topper 040c2b0acf [InstCombine] Fold (min/max ~X, Y) -> ~(max/min X, ~Y) when Y is freely invertible
If the ~X wasn't able to simplify above the max/min, we might be able to simplify it by moving it below the max/min.

I had to modify the ~(min/max ~X, Y) transform to prevent getting stuck in a loop when we saw the new ~(max/min X, ~Y) before the ~Y had been folded away to remove the new not.

Differential Revision: https://reviews.llvm.org/D51398

llvm-svn: 341674
2018-09-07 16:19:50 +00:00
Anna Thomas 110df11a1a [LV] Fix code gen for conditionally executed loads and stores
Fix a latent bug in loop vectorizer which generates incorrect code for
memory accesses that are executed conditionally. As pointed in review,
this bug definitely affects uniform loads and may affect conditional
stores that should have turned into scatters as well).

The code gen for conditionally executed uniform loads on architectures
that support masked gather instructions is broken.

Without this patch, we were unconditionally executing the *conditional*
load in the vectorized version.

This patch does the following:
1. Uniform conditional loads on architectures with gather support will
   have correct code generated. In particular, the cost model
   (setCostBasedWideningDecision) is fixed.
2. For the recipes which are handled after the widening decision is set,
   we use the isScalarWithPredication(I, VF) form which is added in the
   patch.

3. Fix the vectorization cost model for scalarization
   (getMemInstScalarizationCost): implement and use isPredicatedInst to
   identify *all* predicated instructions, not just scalar+predicated. So,
   now the cost for scalarization will be increased for maskedloads/stores
   and gather/scatter operations. In short, we should be choosing the
   gather/scatter in place of scalarization on archs where it is
   profitable.
4. We needed to weaken the assert in useEmulatedMaskMemRefHack.

Reviewers: Ayal, hsaito, mkuper

Differential Revision: https://reviews.llvm.org/D51313

llvm-svn: 341673
2018-09-07 15:53:48 +00:00
Tom Stellard a6749135df MachO: Change getString16() back to inline function
This was accidentally changed in r341670.

llvm-svn: 341672
2018-09-07 15:51:52 +00:00
Marshall Clow 226c14a5fa [asan] Update a vector's storage annotation during destruction. Reviewed as https://reviews.llvm.org/D50101. Thanks to bobsayshilol (Ben) for the patch.
llvm-svn: 341671
2018-09-07 15:47:59 +00:00
Tom Stellard 493f3bad3c MachO: Fix out-of-bounds memory access in getString16
Summary:
This fixes the following tests when gcc is compiled with gcc8:

lld :: mach-o/do-not-emit-unwind-fde-arm64.yaml
lld :: mach-o/eh-frame-relocs-arm64.yaml

llvm.org/PR38096

Reviewers: lhames, kledzik, javed.absar

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D51547

llvm-svn: 341670
2018-09-07 15:42:01 +00:00
Aditya Kumar 801394a3d7 Hot cold splitting pass
Find cold blocks based on profile information (or optionally with static analysis).
Forward propagate profile information to all cold-blocks.
Outline a cold region.
Set calling conv and prof hint for the callsite of the outlined function.

Worked in collaboration with: Sebastian Pop <s.pop@samsung.com>
Differential Revision: https://reviews.llvm.org/D50658

llvm-svn: 341669
2018-09-07 15:03:49 +00:00