Commit Graph

286821 Commits

Author SHA1 Message Date
Zinovy Nis a093b160dc [clang-tidy] One more fix compilation for ParentVirtualCallCheck.cpp: find_if predicate
llvm-svn: 329454
2018-04-06 21:00:18 +00:00
Rafael Espindola b4d3dfefb7 Avoid some temporary allocations.
Some system libraries have a lot of versioned symbols. When linking
scylla this brings the number of malloc calls from 49154 to 37944.

llvm-svn: 329453
2018-04-06 20:53:06 +00:00
Zinovy Nis 7e9745dd4c [clang-tidy] Fix compilation for ParentVirtualCallCheck.cpp
llvm-svn: 329452
2018-04-06 20:39:23 +00:00
Mandeep Singh Grang 1b0e2f2a20 [TableGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: stoklund, kparzysz, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45144

llvm-svn: 329451
2018-04-06 20:18:05 +00:00
Matt Davis 13b8331054 [StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic.
Summary:
The 'strong' StackProtector heuristic takes into consideration call instructions.
Certain intrinsics, such as lifetime.start, can cause the
StackProtector to protect functions that do not need to be protected.

Specifically, a volatile variable, (not optimized away), but belonging to a stack
allocation will encourage a llvm.lifetime.start to be inserted during
compilation. Because that intrinsic is a 'call' the strong StackProtector
will see that the alloca'd variable is being passed to a call instruction, and
insert a stack protector. In this case the intrinsic isn't really lowered to a
call. This can cause unnecessary stack checking, at the cost of additional
(wasted) CPU cycles.

In the future we should rely on TargetTransformInfo::isLoweredToCall, but as of
now that routine considers all intrinsics as not being lowerable. That needs
to be corrected, and such a change is on my list of things to get moving on.

As a side note, the updated stack-protector-dbginfo.ll test always seems to
pass.  I never see the dbg.declare/dbg.value reaching the
StackProtector::HasAddressTaken, but I don't see any code excluding dbg
intrinsic calls either, so I think it's the safest thing to do.

Reviewers: void, timshen

Reviewed By: timshen

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45331

llvm-svn: 329450
2018-04-06 20:14:13 +00:00
Richard Smith eea7062c3a Don't assume constructors return void.
Should fix ARM buildbot.

llvm-svn: 329449
2018-04-06 20:06:02 +00:00
Zinovy Nis 95ea1b05fd [clang-tidy] Check if grand-..parent's virtual method was called instead of overridden parent's.
class A {...int virtual foo() {...}...}; 
class B: public A {...int foo() override {...}...}; 
class C: public B {...int foo() override {... A::foo()...}};
                                              ^^^^^^^^ warning: qualified name A::foo refers to a member overridden in subclass; did you mean 'B'? [bugprone-parent-virtual-call] 

Differential Revision: https://reviews.llvm.org/D44295

llvm-svn: 329448
2018-04-06 20:02:50 +00:00
Alex Lorenz c884b7187c Revert r329442 "Generate Libclang invocation reproducers using a new
-cc1gen-reproducer driver option"

The tests are failing on some bots

llvm-svn: 329447
2018-04-06 19:45:29 +00:00
Michael Kruse 9b67e569c6 [doc] Overhaul doc on preparing IR for processing by Polly.
The previously documented method did not work (anymore).

Suggested-by: Philip Pfaffe <philip.pfaffe@gmail.com>
llvm-svn: 329446
2018-04-06 19:24:18 +00:00
George Karpenkov dbddadd52f Revert "[analyzer] Remove an unused variable"
This reverts commit 2fa3e3edc4ed6547cc4ce46a8c79d1891a5b3b36.

Removed the wrong variable.

llvm-svn: 329445
2018-04-06 19:14:05 +00:00
George Karpenkov 32befa554b [analyzer] Remove an unused variable
llvm-svn: 329444
2018-04-06 19:03:43 +00:00
Geoff Berry 5bf4a5eafa [EarlyCSE] Add debug counter for debugging mis-optimizations. NFC.
Reviewers: reames, spatel, davide, dberlin

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D45162

llvm-svn: 329443
2018-04-06 18:47:33 +00:00
Alex Lorenz 1e720916fa Generate Libclang invocation reproducers using a new -cc1gen-reproducer
driver option

This commit is a follow up to the previous work that recorded Libclang invocations
into temporary files: r319702.

It adds a new -cc1 mode to clang: -cc1gen-reproducer. The goal of this mode is to generate
Clang reproducer files for Libclang tool invocation. The JSON format in the invocation
files is not really intended to be stable, so Libclang and Clang should be of the same version
when generating reproducers.
The new mode emits the information about the temporary files and Libclang-specific information
to stdout using JSON.

rdar://35322614

Differential Revision: https://reviews.llvm.org/D40983

llvm-svn: 329442
2018-04-06 18:30:14 +00:00
Sameer AbuAsal 181501a6b9 [RISCV] Update MC compression tests
Summary:
This patch updates MC tests related to compression in RISCV to
insure they work correctly with automatic compression and relaxation
enabled. This is the first part of a series of patches to implement
automatic compression for RISCV.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: shiva0217, efriedma, llvm-commits, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng

Differential Revision: https://reviews.llvm.org/D43328

llvm-svn: 329441
2018-04-06 18:27:45 +00:00
Dmitry Preobrazhensky ae31223ba7 [AMDGPU][MC][GFX9] Added s_call_b64
See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843

Differential Revision: https://reviews.llvm.org/D45268

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329440
2018-04-06 18:24:49 +00:00
Krzysztof Parzyszek b7e54e8482 [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions
The compiler is generating packet with the following instructions,
which causes an undefined register assert in the verifier.

  $r0 = IMPLICIT_DEF
  $r1 = IMPLICIT_DEF
  S2_storerd_io killed $r29, 0, killed %d0

The problem is that the packetizer is not saving the IMPLICIT_DEF
instructions, which are needed when checking if it is legal to
add the store instruction. The fix is to add the IMPLICIT_DEF
instructions to the CurrentPacketMIs structure.

Patch by Brendon Cahoon.

llvm-svn: 329439
2018-04-06 18:19:22 +00:00
Matt Morehouse fcc97b29c1 [libFuzzer] Print a correct error message when a directory can't be
opened.

Summary:
Currently if the directory cannot be opened for a reason other than
non-existence (e.g. too many open file descriptors) the error message
printed is incredibly confusing.

Patch By: Alex Gaynor

Reviewers: kcc, morehouse

Reviewed By: morehouse

Subscribers: delcypher, llvm-commits, Sanitizers

Differential Revision: https://reviews.llvm.org/D45322

llvm-svn: 329438
2018-04-06 18:15:24 +00:00
Krzysztof Parzyszek aca8f32713 [Hexagon] Prevent a stall across zero-latency instructions in a packet
Packetizer keeps two zero-latency bound instrctions in the same packet ignoring
the stalls on the later instruction. This should not be the case if there is no
data dependence.

Patch by Sumanth Gundapaneni.

llvm-svn: 329437
2018-04-06 18:13:11 +00:00
Krzysztof Parzyszek 269740a88e [Hexagon] Remove duplicated code, NFC
llvm-svn: 329436
2018-04-06 18:10:13 +00:00
Mandeep Singh Grang e92f0cfe34 [CodeGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, rnk, MatzeB, RKSimon

Reviewed By: rnk

Subscribers: JDevlieghere, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45133

llvm-svn: 329435
2018-04-06 18:08:42 +00:00
Krzysztof Parzyszek ed04f02432 [Hexagon] Handle subregisters when calculating iteration count in HW loops
llvm-svn: 329434
2018-04-06 17:51:57 +00:00
Jan Vesely 93af966747 fmod: Port from amd_builtins
Uses only denormal path for fp32.
Passes CTS on carrizo and turks.

v2: whitespace fix

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewer: Aaron Watry <awatry@gmail.com>
llvm-svn: 329433
2018-04-06 17:43:08 +00:00
Simon Pilgrim 1c50cb2077 Cleanup Reduction helpers by using ArrayRef(NoneType) constructor. NFCI.
Pointed out by @abataev on D45366.

llvm-svn: 329431
2018-04-06 17:25:06 +00:00
Dmitry Preobrazhensky 306b1a0119 [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844

Differential Revision: https://reviews.llvm.org/D45313

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329430
2018-04-06 17:25:00 +00:00
Sanjay Patel a9ca709011 [InstCombine] limit nsz: -(X - Y) --> Y - X to hasOneUse()
As noted in the post-commit discussion for r329350, we shouldn't
generally assume that fsub is the same cost as fneg.

llvm-svn: 329429
2018-04-06 17:24:08 +00:00
George Burgess IV e0c2c49a15 [clang-tidy] Sort includes; NFC
llvm-svn: 329428
2018-04-06 17:22:36 +00:00
Simon Pilgrim 389dc7f0c8 Add additional tests from D45336
llvm-svn: 329427
2018-04-06 17:18:44 +00:00
Davide Italiano fccc58a99d [lldb-server] Set a more generous timeout when testing gdbremote.
One of our downstream bot is struggling under load,  but this
value should be enough for everyone.

llvm-svn: 329426
2018-04-06 17:17:20 +00:00
Simon Pilgrim 1e6659c1f0 Add additional tests from D45366
llvm-svn: 329425
2018-04-06 17:15:56 +00:00
Craig Topper c50570fb4f [X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB.
llvm-svn: 329424
2018-04-06 17:12:18 +00:00
Jan Kratochvil 7ea906459a Revert "Cleanup DWARFCompileUnit and DWARFUnit in preparation for adding DWARFTypeUnit"
The reverted commit changed DWARFUnit from https://reviews.llvm.org/D40466 and
https://reviews.llvm.org/D42892 that was prepared for DWARFPartialUnit and
made from it a superclass for DWARFTypeUnit.  DWARFUnit's intention was:
	DWARFUnit->DWARFSomeNameUnit->DWARFCompileUnit
	DWARFUnit->DWARFSomeNameUnit->DWARFTypeUnit
	DWARFUnit->DWARFPartialUnit

Discussed at: https://reviews.llvm.org/D45170

This reverts commit r329305.

llvm-svn: 329423
2018-04-06 17:11:13 +00:00
Simon Dardis a1b7447dfd [compiler-rt][dfsan][mips] UnXPASS a consistently passing test
llvm-svn: 329422
2018-04-06 17:03:36 +00:00
Simon Pilgrim a74f4ae404 Strip trailing whitespace. NFCI.
llvm-svn: 329421
2018-04-06 17:01:54 +00:00
Yaxun Liu 8391387f7b [HIP] define __CUDA_ARCH_=1 for amdgcn targets
Differential Revision: https://reviews.llvm.org/D45277

llvm-svn: 329420
2018-04-06 16:43:42 +00:00
Dmitry Preobrazhensky f20aff565d [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*
See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840

Differential Revision: https://reviews.llvm.org/D45250

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329419
2018-04-06 16:35:11 +00:00
Sanjay Patel a6823f0e67 [InstCombine] add test for fsub+fneg with extra use; NFC
llvm-svn: 329418
2018-04-06 16:30:52 +00:00
Craig Topper b9d298ecf2 [X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model.
We can get this right through WriteALU and friends now.

llvm-svn: 329417
2018-04-06 16:29:31 +00:00
Craig Topper f0d042619b [X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.

Apparently we were inconsistent about whether the store has latency or not thus the test changes.

I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.

Reviewers: RKSimon, andreadb

Reviewed By: andreadb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45351

llvm-svn: 329416
2018-04-06 16:16:48 +00:00
Craig Topper f131b60049 [X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.
Even those the address was calculated for the load, its calculated again for the store.

llvm-svn: 329415
2018-04-06 16:16:46 +00:00
Craig Topper 22d25a08ae [X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.

llvm-svn: 329414
2018-04-06 16:16:43 +00:00
Simon Pilgrim 61f704e4bd [CostModel][X86] Regenerate bit count cost tests with update_analyze_test_checks.py
llvm-svn: 329413
2018-04-06 16:14:27 +00:00
Sanjay Patel bafdf97632 [InstCombine] add potential calloc tests and regenerate checks; NFC
D45344 is proposing to remove the use restriction that made the calloc
transform safe, but it doesn't currently address the problematic example 
given inD16337. Add a test to make sure that doesn't break.

llvm-svn: 329412
2018-04-06 16:06:08 +00:00
Alexey Bataev e290ec02c7 [OPENMP, NVPTX] Fix codegen for the teams reduction.
Added NUW flags for all the add|mul|sub operations + replaced sdiv by udiv
as we operate on unsigned values only (addresses, converted to integers)

llvm-svn: 329411
2018-04-06 16:03:36 +00:00
Simon Pilgrim 63ae5579e7 [CostModel][X86] Regenerate vector shuffle cost tests with update_analyze_test_checks.py
llvm-svn: 329410
2018-04-06 16:00:28 +00:00
Mircea Trofin aa3fea6cb0 [GlobalOpt] Fix support for casts in ctors.
Summary:
Fixing an issue where initializations of globals where constructors use
casts were silently translated to 0-initialization.

Reviewers: davidxl, evgeny777

Reviewed By: evgeny777

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45198

llvm-svn: 329409
2018-04-06 15:54:47 +00:00
Dmitry Preobrazhensky 59399ae4cc [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839

Differential Revision: https://reviews.llvm.org/D45249

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329408
2018-04-06 15:48:39 +00:00
Simon Pilgrim d55ad63bfe [CostModel][X86] Regenerate bswap/bitreverse cost tests with update_analyze_test_checks.py
llvm-svn: 329407
2018-04-06 15:46:26 +00:00
Pete Couperus b7b6e1da6c [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.
Add disassembler support for instructions which writeback STATUS32.
https://reviews.llvm.org/D45148

Patch by Yan Luo! (Yan.Luo2@synopsys.com)

llvm-svn: 329404
2018-04-06 15:43:11 +00:00
Andrea Di Biagio 85b8138bc6 [llvm-mca] Do not separate iterations with a newline in the timeline view.
Also, update a few tests to minimize the diff in D45369.
No functional change intended.

llvm-svn: 329403
2018-04-06 15:30:02 +00:00
Simon Pilgrim 74402acb00 [CostModel][X86] Regenerate integer extension/truncation cost tests with update_analyze_test_checks.py
llvm-svn: 329402
2018-04-06 15:28:26 +00:00