Commit Graph

14784 Commits

Author SHA1 Message Date
Jim Grosbach 712f3670fd ARM vmov assembly parsing for the lane index operand.
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
Michael J. Spencer bfa067862c llvm-objdump: Add static symbol table dumping.
llvm-svn: 142404
2011-10-18 19:32:17 +00:00
Jim Grosbach 611450071c ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
Owen Anderson 40ec1da2ab Another failing encoding.
llvm-svn: 142388
2011-10-18 18:23:03 +00:00
Jim Grosbach 32b83a4e16 Fix NEON mul encoding tests. Wrong file contents previously.
llvm-svn: 142387
2011-10-18 18:14:55 +00:00
Jim Grosbach c8eff0327a ARM vqdmulh assembly parsing for the lane index operand.
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
Jim Grosbach d1bc6da657 Remove duplicate test.
llvm-svn: 142383
2011-10-18 18:05:50 +00:00
Jim Grosbach b3ecff77cd Tidy up formatting.
llvm-svn: 142382
2011-10-18 18:05:16 +00:00
Jim Grosbach e6fbca3a61 ARM vmul assembly parsing for the lane index operand.
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
Jim Grosbach f416cb16c0 Tidy up.
llvm-svn: 142380
2011-10-18 18:01:09 +00:00
Owen Anderson c91064551a Add a few more testcases.
llvm-svn: 142379
2011-10-18 17:57:31 +00:00
Owen Anderson 2a498c1107 Add several FIXME cases for ARM encodings.
llvm-svn: 142377
2011-10-18 17:50:22 +00:00
Bob Wilson 9258b76d8d Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>

llvm-svn: 142371
2011-10-18 17:34:51 +00:00
Bob Wilson 681561901d Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS.
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

llvm-svn: 142370
2011-10-18 17:34:47 +00:00
Jim Grosbach 8206790ab0 Tests for 142365.
llvm-svn: 142368
2011-10-18 17:23:34 +00:00
Jim Grosbach 95135982cd Tidy up formatting.
llvm-svn: 142367
2011-10-18 17:22:53 +00:00
Jim Grosbach e4454e0de2 ARM assembly parsing and encoding for VMOV.i64.
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
Justin Holewinski 1fb5bb126e PTX: Fix disabling of MAD instruction selection
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
Chad Rosier 0ffe593a16 Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916

llvm-svn: 142337
2011-10-18 05:28:00 +00:00
Jim Grosbach 8211c051ca ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
Michael J. Spencer 81c80ddb0c Revert "llvm-objdump: Add static symbol table dumping."
This reverts commit 0c30d4e4f5f9110c5a67bd0ca84444dc58697596.

llvm-svn: 142320
2011-10-18 00:17:04 +00:00
Michael J. Spencer 6b22ef8af2 llvm-objdump: Add static symbol table dumping.
llvm-svn: 142319
2011-10-17 23:55:22 +00:00
Jim Grosbach 26bfc9e5da Enable a few more NEON immediate tests.
llvm-svn: 142313
2011-10-17 23:50:19 +00:00
Jim Grosbach cda32ae372 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
Nick Lewycky 40f8f2ff24 Add support for a new extension to the .file directive:
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
2011-10-17 23:05:28 +00:00
Dan Gohman a7107f992e Teach the ARC optimizer about the !clang.arc.copy_on_escape metadata
tag on objc_retainBlock calls, which indicates that they may be
optimized away. rdar://10211286.

llvm-svn: 142298
2011-10-17 22:53:25 +00:00
Jim Grosbach 741cd73aab ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
2011-10-17 22:26:03 +00:00
Lang Hames e7594abd87 Fixed quoting on default data layout option.
llvm-svn: 142286
2011-10-17 21:54:43 +00:00
Bill Wendling c68c8cb8d4 Add support for the Objective-C personality function to the instruction
combining of the landingpad instruction. The ObjC personality function acts
almost identically to the C++ personality function. In particular, it uses
"null" as a "catch-all" value.

llvm-svn: 142256
2011-10-17 21:20:24 +00:00
Nadav Rotem d2c72d6d03 Add CHECKs and document PR11158.
llvm-svn: 142240
2011-10-17 20:23:23 +00:00
Nadav Rotem 28e4f67f26 stabalize tests by specifying the exact sse level
llvm-svn: 142229
2011-10-17 19:45:38 +00:00
Dan Gohman 1736c14b85 Suppress partial retain+release elimination when there's a
possibility that it will span multiple CFG diamonds/triangles which
could have different controlling predicates.  rdar://10282956

llvm-svn: 142222
2011-10-17 18:48:25 +00:00
Bill Wendling 63a4ea1859 Correct over-zealous removal of hack.
Some code want to check that *any* call within a function has the 'returns
twice' attribute, not just that the current function has one.

llvm-svn: 142221
2011-10-17 18:43:40 +00:00
Bill Wendling 42cf65fe51 Temporarily XFAIL waiting for a fix.
llvm-svn: 142215
2011-10-17 18:25:32 +00:00
Michael J. Spencer 4e25c02487 llvm-objdump: Add -s, which prints the contents of each section.
llvm-svn: 142199
2011-10-17 17:13:22 +00:00
Michael J. Spencer b4f19a5d86 llvm-objdump: Add tests.
llvm-svn: 142198
2011-10-17 17:13:05 +00:00
Hal Finkel 9dda3e0d13 use FileCheck and not grep in new tests
llvm-svn: 142189
2011-10-17 16:01:41 +00:00
Nadav Rotem 83d1a93cf4 Clean the triple, add check lines.
llvm-svn: 142183
2011-10-17 07:07:51 +00:00
Nadav Rotem 89c282e96f Previously v2i32 vectors were legalized to v4i32. Now, they are legalized to
v2i64. These tests do not check MMX nor zmoving into them.

llvm-svn: 142182
2011-10-17 06:59:01 +00:00
Hal Finkel 7ccb391d21 Test case for CanLowerReturn fix (r141981)
llvm-svn: 142172
2011-10-17 04:03:59 +00:00
Hal Finkel ad677b64db Add PPC 440 scheduler and some associated tests (new files)
llvm-svn: 142171
2011-10-17 04:03:55 +00:00
Chandler Carruth 3e8aa65bc2 Add a routine to swap branch instruction operands, and update any
profile metadata at the same time. Use it to preserve metadata attached
to a branch when re-writing it in InstCombine.

Add metadata to the canonicalize_branch InstCombine test, and check that
it is tranformed correctly.

Reviewed by Nick Lewycky!

llvm-svn: 142168
2011-10-17 01:11:57 +00:00
Nadav Rotem 053a7358d6 Add tripple and stabalize a few more tests.
llvm-svn: 142158
2011-10-16 21:20:54 +00:00
Nadav Rotem a6b6566db6 Add triple to tests.
llvm-svn: 142154
2011-10-16 20:53:20 +00:00
Nadav Rotem 9513104d2a fix a typo in the test
llvm-svn: 142153
2011-10-16 20:43:41 +00:00
Nadav Rotem 486ff59a9f Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
2011-10-16 20:31:33 +00:00
Nick Lewycky 84baea77ea Oops! Fix testcase.
llvm-svn: 142151
2011-10-16 20:20:15 +00:00
Nick Lewycky 0a7e9ccf04 When looking for dependencies on the src pointer, scan the src pointer. Scanning
on the memcpy call will pull up other unrelated stuff. Fixes PR11142.

llvm-svn: 142150
2011-10-16 20:13:32 +00:00
Nadav Rotem 2130a07687 Remove the the test which checks the saving of a vector of booleans into memory.
The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.

llvm-svn: 142149
2011-10-16 19:06:06 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions.
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Nadav Rotem bc25b6eb67 Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.

llvm-svn: 142130
2011-10-16 10:02:06 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection.
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper 0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
Chris Lattner a3a0681083 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
2011-10-16 04:47:35 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
NAKAMURA Takumi 4f539312df test/Makefile: Inspect $(PROJ_OBJ_ROOT)/tools/clang/Makefile instead of $(PROJ_SRC_ROOT)/tools/clang for "check-all".
llvm-svn: 142100
2011-10-16 02:54:14 +00:00
Craig Topper 27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Nico Weber 3a46b375e2 Let this test pass even if 'int' is somewhere in its directory path.
On my machine, grep matched:

  ; ModuleID = '/Volumes/MacintoshHD2/src/chrome-git/src/third_party/llvm/test/Linker/2011-08-18-unique-debug-type.ll'
  !9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]

Explicitly filter out the ModuleID line.

llvm-svn: 142077
2011-10-15 18:07:16 +00:00
Andrew Trick fd4ca0f4ac Fix SCEVExpander assert during LSR: "argument of incompatible type".
Just because we're dealing with a GEP doesn't mean we can assert the
SCEV has a pointer type. The fix is simply to ignore the SCEV pointer
type, which we really didn't need.
Fixes PR11138 webkit crash.

llvm-svn: 142058
2011-10-15 06:19:55 +00:00
Eli Friedman 74d1da5a05 Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129.
llvm-svn: 142022
2011-10-14 23:58:49 +00:00
Owen Anderson 220f2643fa Update test for disabling of code/data marker labels in ELF.
llvm-svn: 142003
2011-10-14 21:12:55 +00:00
Torok Edwin 3e3ed6d21b OCaml bindings: add some missing functions and testcases.
The C bindings exposed some APIs that weren't covered by the OCaml bindings

llvm-svn: 141997
2011-10-14 20:38:33 +00:00
Torok Edwin 90e6edf7c4 OCaml bindings: fix infinite recursion on string_of_lltype
llvm-svn: 141994
2011-10-14 20:38:14 +00:00
Jakob Stoklund Olesen 06b6ccfe90 Update live-in lists when splitting critical edges.
Fixes PR10814. Patch by Jan Sjödin!

llvm-svn: 141960
2011-10-14 17:25:46 +00:00
Craig Topper 965de2c197 Add X86 ANDN instruction. Including instruction selection.
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
Craig Topper 3657fe4b17 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
llvm-svn: 141939
2011-10-14 03:21:46 +00:00
Jakob Stoklund Olesen 7fb5632e73 Add value numbers when spilling dead defs.
When spilling around an instruction with a dead def, remember to add a
value number for the def.

The missing value number wouldn't normally create problems since there
would be an incoming live range as well.  However, due to another bug
we could spill a dead V_SET0 instruction which doesn't read any values.

The missing value number caused an empty live range to be created which
is dangerous since it doesn't interfere with anything.

This fixes part of PR11125.

llvm-svn: 141923
2011-10-14 00:34:31 +00:00
Michael J. Spencer 834bd602e6 ELF: Fix the section that relocations apply to. Add test to verify. Patch by Danil Malyshev!
llvm-svn: 141901
2011-10-13 22:30:10 +00:00
Michael J. Spencer 51862b3890 llvm-object: Add inline relocation information to disassembly.
llvm-svn: 141897
2011-10-13 22:17:18 +00:00
Andrew Trick 870c1a3f15 Reapply r141870, SCEV expansion of post-inc.
Speculatively reapply to see if this test case still crashes on
linux. I may have fixed it in my last checkin.

llvm-svn: 141895
2011-10-13 21:55:29 +00:00
Andrew Trick 41c253c35c Revert r141870. The test case crashes on linux with data corruption. A deeper issue was exposed.
llvm-svn: 141873
2011-10-13 17:58:24 +00:00
Andrew Trick e15d6e14e3 LSR: Reuse the post-inc expansion of expressions.
This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.

llvm-svn: 141870
2011-10-13 17:31:47 +00:00
Benjamin Kramer f07d898ae1 Force CPU type on test so it doesn't accidentally emit movbe instead of bswap on Intel Atom CPUs.
llvm-svn: 141863
2011-10-13 14:27:54 +00:00
Kalle Raiskila 3815de8d50 Mark 'branch indirect' instruction as an indirect branch.
Not having it confused assembly printing of jumptables.

llvm-svn: 141862
2011-10-13 11:40:03 +00:00
Bill Wendling 25f6d3e321 More closely follow libgcc, which has code after the `ret' instruction to
release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859
2011-10-13 08:24:19 +00:00
Bill Wendling 063f55ffdd Revert r141854 because it was causing failures:
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
2011-10-13 07:48:07 +00:00
Bill Wendling 22a690e3db Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.
llvm-svn: 141856
2011-10-13 07:42:32 +00:00
Craig Topper 8cc9388073 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
llvm-svn: 141854
2011-10-13 07:09:14 +00:00
Jakob Stoklund Olesen 068dc91de9 Also inflate register classes around inline asm.
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

llvm-svn: 141836
2011-10-12 23:37:40 +00:00
Bill Wendling 3e5409df77 We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830
2011-10-12 23:03:40 +00:00
Lang Hames 850f7b3cdc Removed colons from some target datalayout strings in test, since they don't match the required format.
llvm-svn: 141825
2011-10-12 22:24:17 +00:00
Kevin Enderby e7c0c499b8 Finish supporting cpp #file/line comments in assembler for error messages. So
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895

llvm-svn: 141814
2011-10-12 21:38:39 +00:00
Jim Grosbach 54a20ed0f1 Thumb2 assembly parsing and encoding for LDC/STC.
llvm-svn: 141811
2011-10-12 20:54:17 +00:00
Jim Grosbach 84cf2b8c98 ARM encoding tests for STC.
llvm-svn: 141787
2011-10-12 17:36:13 +00:00
Jim Grosbach 483995875f ARM parsing and encoding for the <option> form of LDC/STC instructions.
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
Jakob Stoklund Olesen 39c31a77b8 Fix -widen-vmovs liveness issues.
When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746
2011-10-12 00:06:23 +00:00
Bob Wilson 2d3ea9b2f2 Make this test more specific. There are 3 stats that matched "machine-licm".
llvm-svn: 141741
2011-10-11 23:34:31 +00:00
Eric Christopher 6647b83087 Add a new wrapper node for a DILexicalBlock that encapsulates it and a
file. Since it should only be used when necessary propagate it through
the backend code generation and tweak testcases accordingly.

This helps with code like in clang's test/CodeGen/debug-info-line.c where
we have multiple #line directives within a single lexical block and want
to generate only a single block that contains each file change.

Part of rdar://10246360

llvm-svn: 141729
2011-10-11 22:59:11 +00:00
Jim Grosbach 9398141c48 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
2011-10-11 21:55:36 +00:00
Bill Wendling 265328baf6 Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
Cameron Zwarich 1a761dcfbd Fix PR11106 by correcting a typo that has been in the code for over a year. This
would have never worked, since the element type of a vector type is never a
vector type. Also fix the conditional to be more direct in checking whether
EltTy is a vector type.

llvm-svn: 141713
2011-10-11 21:26:40 +00:00
Jim Grosbach 8c799c9826 Update test for r141704.
llvm-svn: 141705
2011-10-11 20:18:50 +00:00
Devang Patel 453d401a51 Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
2011-10-11 18:09:58 +00:00
Nadav Rotem 3283793c9a Add support for legalization of vector SHL/SRA/SRL instructions
llvm-svn: 141667
2011-10-11 14:36:35 +00:00
Nick Lewycky 3e01bd3b60 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
2011-10-11 06:58:11 +00:00
Craig Topper 603cc851f8 Test case for X86 LZCNT instruction selection.
llvm-svn: 141652
2011-10-11 06:47:01 +00:00
Craig Topper 271064e873 Add X86 LZCNT instruction. Including instruction selection support.
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
Cameron Zwarich ab3a9b3baf Add a test for PR10565.
llvm-svn: 141647
2011-10-11 06:10:37 +00:00
Cameron Zwarich d7515ccc47 Remove a lot of the fancy scalar replacement code for dealing with llvm-gcc's
lowering of NEON code. It provides little-to-no benefit now and only introduces
additional complexity.

llvm-svn: 141646
2011-10-11 06:10:30 +00:00
Bill Wendling 288ff0ec82 Test simplification that Ana Pazos noticed.
llvm-svn: 141644
2011-10-11 04:43:15 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
Nick Lewycky 29e7b315ac Also create a shndx even if there are no symbols. This lets us test
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641
2011-10-11 03:54:50 +00:00
NAKAMURA Takumi ba38717f34 test/CodeGen/X86/movbe.ll: Give explicit -mtriple=x86_64-linux, to unbreak win32 hosts.
llvm-svn: 141640
2011-10-11 03:41:03 +00:00
Andrew Trick f9201c572e Move replaceCongruentIVs into SCEVExapander and bias toward "expanded"
IVs.

Indvars previously chose randomly between congruent IVs. Now it will
bias the decision toward IVs that SCEVExpander likes to create. This
was not done to fix any problem, it's just a welcome side effect of
factoring code.

llvm-svn: 141633
2011-10-11 02:28:51 +00:00
Akira Hatanaka 8782734bcc Test cases for 64-bit load and store instructions.
llvm-svn: 141631
2011-10-11 01:52:31 +00:00
Lang Hames 44c78f809b Added a testcase for r141599, rdar://problem/10063881.
llvm-svn: 141628
2011-10-11 01:32:10 +00:00
Bill Wendling 9449b8b9d2 Add testcase for PR11107.
llvm-svn: 141607
2011-10-11 00:26:57 +00:00
Devang Patel 478d5bc0d0 Revert r141569 and r141576.
llvm-svn: 141594
2011-10-10 23:18:02 +00:00
Bill Wendling a7d697e4a6 Reapply r141365 now that PR11107 is fixed.
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
Eli Friedman 8ec0897db6 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
Nick Lewycky fcf8462583 Add support for dumping section headers to llvm-objdump. This uses the same
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.

llvm-svn: 141579
2011-10-10 21:21:34 +00:00
Devang Patel 2689f95875 If loop header is also loop exiting block then it may not be safe to hoist instructions.
llvm-svn: 141576
2011-10-10 20:32:03 +00:00
Nadav Rotem 814598563f Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
instruction set has no 64-bit SRA support.

llvm-svn: 141570
2011-10-10 19:31:45 +00:00
Devang Patel e554d5995b Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
2011-10-10 19:09:20 +00:00
Benjamin Kramer 42c0330a79 X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen b253f490c3 Insert dummy ED table entries for pseudo-instructions.
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
2011-10-10 18:30:16 +00:00
Bill Wendling 47aac51043 Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
2011-10-10 18:27:30 +00:00
Benjamin Kramer e7ae31cc25 XFAIL tblgen tests on leak checkers.
llvm-svn: 141533
2011-10-10 13:09:59 +00:00
Bill Wendling ea662bb32f When getting the number of bits necessary for addressing mode
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
2011-10-10 07:24:23 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen 729abd360e Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen b81dcdef7b Add missing test case for r141410.
llvm-svn: 141498
2011-10-08 18:06:54 +00:00
Andrew Trick ce0cb3a101 Unit test for LSR phi reuse in r141442.
llvm-svn: 141472
2011-10-08 02:34:51 +00:00
Michael J. Spencer ba4a362276 llvm-objdump: Add relocation and archive support.
llvm-svn: 141451
2011-10-08 00:18:30 +00:00
Jim Grosbach c87d60a58c Enable ARM mode VDUP(scalar) tests.
llvm-svn: 141447
2011-10-07 23:57:03 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar).
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
David Greene 33f619971f Remove Multidefs
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

llvm-svn: 141378
2011-10-07 18:25:05 +00:00
Evan Cheng 74db300f37 High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
llvm-svn: 141371
2011-10-07 17:21:44 +00:00
Bob Wilson 8decdc472f Reenable tail calls for iOS 5.0 and later.
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
Bob Wilson bc1589945d Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
Anton Korobeynikov 318d6bae80 Peephole optimization for ABS on ARM.
Patch by Ana Pazos!

llvm-svn: 141365
2011-10-07 16:15:08 +00:00
Duncan Sands c52af46484 Teach GVN to also propagate switch cases. For example, in this code
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.

llvm-svn: 141360
2011-10-07 08:29:06 +00:00
Craig Topper d9cfddc5cd Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
Jim Grosbach 0947102623 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
llvm-svn: 141321
2011-10-06 22:04:05 +00:00
Jim Grosbach 4887469138 Fix and clean up tests. Un-XFAIL.
llvm-svn: 141318
2011-10-06 21:32:50 +00:00
Jim Grosbach ceb4c7523f Fix and clean up tests. Un-XFAIL.
llvm-svn: 141316
2011-10-06 21:28:30 +00:00
David Greene 74842740c0 Make Test More Thorough
Check that all ADD patters are processed.

Add a SUB test.

llvm-svn: 141314
2011-10-06 21:20:44 +00:00
Peter Collingbourne 7f7f2e9b76 s/tblgen/llvm-tblgen/g in a few missed places, including the tests
llvm-svn: 141294
2011-10-06 13:39:59 +00:00
Torok Edwin d43a5d76f4 ocaml bindings: add llvm_ipo based on IPO.h
llvm-svn: 141284
2011-10-06 12:12:27 +00:00
Torok Edwin ba1460adb6 add more tests for the OCaml bindings
llvm-svn: 141283
2011-10-06 12:12:12 +00:00
Craig Topper 23eb468b1f Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
Cameron Zwarich 87aa18378e Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247
2011-10-05 23:38:50 +00:00
David Greene 9bc27ec40f Update Test for Multidefs
Update the MultiPat.td test to create some defs via multidefs.

llvm-svn: 141235
2011-10-05 22:42:48 +00:00
David Greene 52a9cb8063 Add a Multidef Test
Add a simple test for multidefs.

llvm-svn: 141234
2011-10-05 22:42:47 +00:00
Eli Friedman 3e3aecbc2c PR11061: Make simplifylibcalls fold strcmp("", x) correctly.
While I'm here, fix the related issue with strncmp, add some actual tests for strcmp and strncmp, and start using StringRef::compare for constant folding instead of using strcmp/strncmp so that the optimized IR isn't dependent on the host's implementation of strcmp.

llvm-svn: 141227
2011-10-05 22:27:16 +00:00
Jim Grosbach 8f9acfac89 Revert 141203. InstCombine is looping on unit tests.
llvm-svn: 141209
2011-10-05 20:44:29 +00:00
Rafael Espindola 79d0c4f4b0 Check for the returns_twice attribute in callsFunctionThatReturnsTwice. This
fixes PR11038, but there are still some cleanups to be done.

llvm-svn: 141204
2011-10-05 20:05:13 +00:00
Jim Grosbach e37e030137 Update InstCombine worklist after instruction transform is complete.
When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.

rdar://10238555

llvm-svn: 141203
2011-10-05 20:05:00 +00:00