0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
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llvm-svn: 141135
2011-10-04 23:26:17 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
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llvm-svn: 140943
2011-10-01 09:30:42 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
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llvm-svn: 140939
2011-10-01 08:58:29 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
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and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
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llvm-svn: 140824
2011-09-29 23:50:42 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
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This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
05dec8b122
Tidy up. Formatting.
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llvm-svn: 139024
2011-09-02 18:46:15 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
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Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
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It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
36a3abc671
Add support for the R and Q constraints.
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llvm-svn: 137217
2011-08-10 16:26:42 +00:00
faff512536
Emitting ARM build attributes and values as ULEB, rather than char.
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llvm-svn: 137115
2011-08-09 09:50:10 +00:00
2aedba6c5e
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
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llvm-svn: 136141
2011-07-26 20:54:26 +00:00
61faa55b74
Separate MCInstPrinter registration from AsmPrinter registration.
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llvm-svn: 135974
2011-07-25 21:20:24 +00:00
a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
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llvm-svn: 135636
2011-07-20 23:34:39 +00:00
204c128f66
Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
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llvm-svn: 134734
2011-07-08 20:39:19 +00:00
4af8647e17
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
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llvm-svn: 134732
2011-07-08 20:32:21 +00:00
dbfb29d6c0
Use ARMPseudoExpand for ARM tail calls.
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llvm-svn: 134719
2011-07-08 18:50:22 +00:00
2dfe8e3ccd
Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
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TableGen'erated MC lowering pseudo-expansion.
llvm-svn: 134712
2011-07-08 18:15:12 +00:00
95dee40343
Use TableGen'erated pseudo lowering for ARM.
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Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
llvm-svn: 134705
2011-07-08 17:40:42 +00:00
148220306f
The VMLA instruction and its friends are not actually fused; they're plain old
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multiply-accumulate instructions with separate rounding steps.
llvm-svn: 134609
2011-07-07 08:28:52 +00:00
ab37af9af3
createMCInstPrinter doesn't need TargetMachine anymore.
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llvm-svn: 134525
2011-07-06 19:45:42 +00:00
e9cc901814
Refact ARM Thumb1 tMOVr instruction family.
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Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
llvm-svn: 134204
2011-06-30 23:38:17 +00:00
b98ab91e39
Thumb1 register to register MOV instruction is predicable.
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Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
llvm-svn: 134197
2011-06-30 22:10:46 +00:00
353da73186
Pseudo-ize the t2LDMIA_RET instruction.
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It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.
llvm-svn: 134173
2011-06-30 18:25:42 +00:00
417671a7b1
Pseudo-ize the Thumb tPOP_RET instruction.
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It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.
llvm-svn: 134172
2011-06-30 17:34:04 +00:00
a8a8067dec
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
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Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
llvm-svn: 134114
2011-06-29 23:25:04 +00:00
d00e8ad803
Implement the 'M' output modifier for arm inline asm. This is fairly
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register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
llvm-svn: 132242
2011-05-28 01:40:44 +00:00
d23bfb8a7a
Make size computation less brittle.
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llvm-svn: 132222
2011-05-27 22:05:41 +00:00
33a73c7755
Reorganize these slightly according to operand type.
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llvm-svn: 132128
2011-05-26 18:22:26 +00:00
26ddb12118
Mark tBX as an indirect branch rather than a return.
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llvm-svn: 132107
2011-05-26 03:41:12 +00:00
a946f476d3
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
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llvm-svn: 132086
2011-05-25 21:53:50 +00:00
8c5e4192e6
Implement the 'm' modifier. Note that it only works for memory operands.
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Part of rdar://9119939
llvm-svn: 132081
2011-05-25 20:51:58 +00:00
3088e0a179
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
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fixes <rdar://problem/9495913>
llvm-svn: 132042
2011-05-25 04:45:27 +00:00
deaf994ff0
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
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reflect their actual meaning and match the ARM instructions.
llvm-svn: 132039
2011-05-25 04:45:14 +00:00
1b724948e9
Implement the arm 'L' asm modifier.
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Part of rdar://9119939
llvm-svn: 132024
2011-05-24 23:27:13 +00:00
b1dda56ac2
Implement the immediate part of the 'B' modifier.
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Part of rdar://9119939
llvm-svn: 132023
2011-05-24 23:15:43 +00:00
d4562566b4
Add more unimplemented asm modifiers and some documentation of what they
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do.
Part of rdar://9119939.
llvm-svn: 132015
2011-05-24 22:27:43 +00:00
7617883ce3
Add support for the arm 'y' asm modifier.
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Fixes part of rdar://9444657
llvm-svn: 132011
2011-05-24 22:10:34 +00:00
bc90690b24
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
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in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
llvm-svn: 131894
2011-05-23 01:57:17 +00:00
652bfdb1ab
adds some attributes to attribute section when cpu is "xscale"
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(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
e90c1cb221
sets bit 0 of the function address of thumb function in .symtab
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("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
39ecf816c5
Do not emit location expression size twice.
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llvm-svn: 130854
2011-05-04 19:00:57 +00:00
3e021533cd
Teach dwarf writer to handle complex address expression for .debug_loc entries.
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This fixes clang generated blocks' variables' debug info.
Radar 9279956.
llvm-svn: 130373
2011-04-28 02:22:40 +00:00
e3745fdcf3
Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
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llvm-svn: 130326
2011-04-27 20:29:27 +00:00
cae2fbd6fc
Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
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llvm-svn: 130178
2011-04-26 00:12:46 +00:00
3c39ec2933
Add asserts.
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llvm-svn: 129995
2011-04-22 16:44:29 +00:00
94ad6ac13c
Fix DWARF description of Q registers.
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llvm-svn: 129952
2011-04-21 23:22:35 +00:00
3712c14be9
Fix DWARF description of S registers.
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llvm-svn: 129947
2011-04-21 22:48:26 +00:00
Owen Anderson