Commit Graph

4 Commits

Author SHA1 Message Date
Alex Bradbury 3ff2022bb9 [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits
These immediates can be materialised with just an lui, rather than an lui+addi 
pair.

llvm-svn: 330293
2018-04-18 20:34:23 +00:00
Alex Bradbury 099c720426 Revert "[RISCV] implement li pseudo instruction"
Reverts rL330224, while issues with the C extension and missed common
subexpression elimination opportunities are addressed. Neither of these issues
are visible in current RISC-V backend unit tests, which clearly need
expanding.

llvm-svn: 330281
2018-04-18 19:02:31 +00:00
Alex Bradbury 480b7bc906 [RISCV] implement li pseudo instruction
The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering
and is similar to the expansion performed by the GNU Assembler.

Differential Revision: https://reviews.llvm.org/D41949
Patch by Mario Werner.

llvm-svn: 330224
2018-04-17 21:56:40 +00:00
Alex Bradbury 76c29ee815 [RISCV] Add codegen for RV32F arithmetic and conversion operations
Currently, only a soft floating point ABI is supported.

llvm-svn: 327976
2018-03-20 12:45:35 +00:00