5d4c134a94
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
...
partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
llvm-svn: 104149
2010-05-19 20:36:22 +00:00
738e920edf
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
...
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
e11cdf8cc8
TwoAddressInstructionPass doesn't really know how to merge live intervals when
...
lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
llvm-svn: 104146
2010-05-19 20:08:00 +00:00
59a61fd7cc
llvmc: report an error if a child process segfaults.
...
llvm-svn: 104145
2010-05-19 19:24:32 +00:00
6a1bfd282b
When expanding a vector_shuffle, the element type may not be legal and may
...
need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
llvm-svn: 104141
2010-05-19 18:48:32 +00:00
52e37becf6
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
...
llvm-svn: 104122
2010-05-19 17:20:58 +00:00
d2f78e755f
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
...
prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
llvm-svn: 104120
2010-05-19 15:26:43 +00:00
b243dfb085
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
...
CALL64pcrel32, for the same reason.
llvm-svn: 104116
2010-05-19 08:07:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
b7704fee4c
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
...
llvm-svn: 104114
2010-05-19 07:26:50 +00:00
4f6c7c6d94
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
...
llvm-svn: 104112
2010-05-19 06:20:44 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
...
llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
...
avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
...
llvm-svn: 104102
2010-05-19 01:52:25 +00:00
744c96dd48
Add a comment explaining why this code uses Append mode.
...
llvm-svn: 104095
2010-05-19 01:21:34 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
...
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
...
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
beebef4137
Add a comment.
...
llvm-svn: 104089
2010-05-18 23:55:57 +00:00
50f8f2c23d
Fix the predicate which checks for non-sensical formulae which have
...
constants in registers which partially cancel out their immediate fields.
llvm-svn: 104088
2010-05-18 23:48:08 +00:00
4cf99b5303
Factor out the code for recomputing an LSRUse's Regs set after some
...
of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
llvm-svn: 104087
2010-05-18 23:42:37 +00:00
055c01d9dc
Fix a crash when debugging the coalescer. DebugValue instructions are not
...
in the coalescer's instruction map.
llvm-svn: 104086
2010-05-18 23:19:42 +00:00
a4eca05174
Factor out code for estimating search space complexity into a helper
...
function.
llvm-svn: 104082
2010-05-18 22:51:59 +00:00
63e9015248
Add some more debug output.
...
llvm-svn: 104080
2010-05-18 22:41:32 +00:00
f1c7b1b42f
Factor out the code for deleting a formula from an LSRUse into
...
a helper function.
llvm-svn: 104079
2010-05-18 22:39:15 +00:00
8aca7ef903
Make some debug output more informative.
...
llvm-svn: 104078
2010-05-18 22:37:37 +00:00
06ab08f795
Print an error message in Formula::print if the HasBaseReg flag
...
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
llvm-svn: 104077
2010-05-18 22:35:55 +00:00
248c41d108
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
...
confusion with LSRInstance's RegUses member.
llvm-svn: 104076
2010-05-18 22:33:00 +00:00
430b6e40ab
Remember to update VirtRegLastUse when spilling without killing before a call.
...
llvm-svn: 104074
2010-05-18 22:20:09 +00:00
f8bf663873
Teach mode load folding and unfolding code about CMP32ri8 and friends.
...
llvm-svn: 104068
2010-05-18 21:54:15 +00:00
4ed63f8687
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
...
specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
887dd1cd31
When converting a test to a cmp to fold a load, use the cmp that has an
...
8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
9f46539e07
make mcinstlower remove all but the first operand to CALL64pcrel32.
...
The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
...
llvm-svn: 104060
2010-05-18 21:31:17 +00:00
feedc90c57
Implement EmitTBSSSymbol for MachOStreamer.
...
Fixes build failure as well.
llvm-svn: 104059
2010-05-18 21:26:41 +00:00
5c87be766d
Make EmitTBSSSymbol take a section argument so that we can find it later.
...
Fix up callers and users.
llvm-svn: 104057
2010-05-18 21:16:04 +00:00
663543b4d7
Properly handle multiple definitions of a virtual register in the same
...
instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
llvm-svn: 104056
2010-05-18 21:10:50 +00:00
45b3f702ab
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
...
llvm-svn: 104051
2010-05-18 20:07:47 +00:00
e7fc64a5c9
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
...
llvm-svn: 104050
2010-05-18 20:03:28 +00:00
7bcc9e9450
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
...
CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
llvm-svn: 104039
2010-05-18 18:09:20 +00:00
53e0631516
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
...
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
llvm-svn: 104038
2010-05-18 17:51:35 +00:00
4843178d6b
Teach the machine code verifier to use getSubRegisterRegClass().
...
The old approach was wrong. It had an off-by-one error.
llvm-svn: 104034
2010-05-18 17:31:12 +00:00
d5563f420a
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
...
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
llvm-svn: 104033
2010-05-18 17:28:24 +00:00
f16c12d7a1
MC/Mach-O: Remove some FIXMEs.
...
llvm-svn: 104032
2010-05-18 17:28:20 +00:00
39617bb08a
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
...
llvm-svn: 104031
2010-05-18 17:28:17 +00:00
a4820fcc78
MC/X86: Implement custom lowering to make sure we match things like
...
X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
llvm-svn: 104030
2010-05-18 17:22:24 +00:00
62bc96a1a5
llc (et al): Add support for --show-encoding and --show-inst.
...
llvm-svn: 104029
2010-05-18 17:22:19 +00:00
dea5310433
Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream.
...
Update the comment.
llvm-svn: 104021
2010-05-18 15:25:14 +00:00
ab7be75e3f
Simplify MCContext::(Next|Get)Instance
...
- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.
llvm-svn: 104020
2010-05-18 12:15:34 +00:00
48f0de96d6
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
...
llvm-svn: 104004
2010-05-18 00:03:40 +00:00
93d8844699
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
...
too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
llvm-svn: 103995
2010-05-17 23:29:23 +00:00
1e4f55200d
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
...
llvm-svn: 103994
2010-05-17 23:24:12 +00:00
02d3368831
- Set the "HasCalls" flag after instruction selection is finished.
...
- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00
0510b48fd9
Added support in MC for Directional Local Labels.
...
llvm-svn: 103989
2010-05-17 23:08:19 +00:00
9635b3da6b
More data/parsing support for tls directives. Add a few more testcases
...
and cleanup comments as well.
llvm-svn: 103985
2010-05-17 22:53:55 +00:00
f2c9a96f3c
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
...
llvm-svn: 103984
2010-05-17 22:09:49 +00:00
cd04ed3533
vmov of immediates are trivially re-materializable.
...
llvm-svn: 103982
2010-05-17 21:54:50 +00:00
bb166bed40
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
...
llvm-svn: 103981
2010-05-17 21:54:30 +00:00
ce5e1bb326
MC: Add dyn_cast support to MCSection.
...
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.
llvm-svn: 103980
2010-05-17 21:54:26 +00:00
b7b796cc11
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
...
- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
llvm-svn: 103979
2010-05-17 21:19:59 +00:00
585792738b
Pull the UsedInInstr.test() calls into calcSpillCost() and remember aliases.
...
This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.
llvm-svn: 103975
2010-05-17 21:02:08 +00:00
bf79238599
Add some section and constant support for darwin TLS.
...
llvm-svn: 103974
2010-05-17 21:02:07 +00:00
29c463862e
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
...
llvm-svn: 103971
2010-05-17 20:57:12 +00:00
c601801a7e
Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests.
...
Obvious in retrospect but not fun to debug.
llvm-svn: 103969
2010-05-17 20:31:13 +00:00
0211a96989
MC/Mach-O: Fix some differences in symbol flag handling.
...
- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
llvm-svn: 103964
2010-05-17 20:12:31 +00:00
70563bbba5
Remove debug option. Add comment on spill order determinism.
...
llvm-svn: 103961
2010-05-17 20:01:22 +00:00
3d98b996ff
Turn on -neon-reg-sequence by default.
...
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
llvm-svn: 103960
2010-05-17 19:51:20 +00:00
9b4a824217
llvm-mc: Support reassignment of variables in one special case, when the
...
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
llvm-svn: 103950
2010-05-17 17:46:23 +00:00
176a9c4272
Avoid allocating the same physreg to multiple virtregs in one instruction.
...
While that approach works wonders for register pressure, it tends to break
everything.
This should unbreak the arm-linux builder and fix a number of miscompilations.
llvm-svn: 103946
2010-05-17 17:18:59 +00:00
f5e8c86424
Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map.
...
llvm-svn: 103940
2010-05-17 15:30:37 +00:00
6649cdaa23
Extract spill cost calculation to a new method, and use definePhysReg() to clear
...
out aliases when allocating. Clean up allocVirtReg().
Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.
llvm-svn: 103939
2010-05-17 15:30:32 +00:00
188855abef
Remove unused member variable.
...
llvm-svn: 103936
2010-05-17 09:47:55 +00:00
7d22a81b61
Only use clairvoyance when defining a register, and then only if it has one use.
...
This makes allocation independent on the ordering of use-def chains.
llvm-svn: 103935
2010-05-17 04:50:57 +00:00
f915d14955
Eliminate a hash table probe when killing virtual registers.
...
llvm-svn: 103934
2010-05-17 03:26:09 +00:00
edd3d9db13
Execute virtreg kills immediately instead of after processing all uses.
...
This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.
llvm-svn: 103933
2010-05-17 03:26:06 +00:00
e07a408afc
Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
...
llvm-svn: 103931
2010-05-17 02:49:21 +00:00
1069a09691
Now that we don't keep live registers across calls, there is not reason to go
...
through the very long list of call-clobbered registers. We just assume all
registers are clobbered.
llvm-svn: 103930
2010-05-17 02:49:18 +00:00
397068de06
Boldly attempt consistent capitalization. Functional changes unintended.
...
llvm-svn: 103929
2010-05-17 02:49:15 +00:00
68b1bbe66a
Assume that we'll handle mangling the symbols earlier and just put the
...
symbol to the file as we have it. Simplifies out tbss handling.
llvm-svn: 103928
2010-05-17 02:13:02 +00:00
8044c989d1
Spill and kill all virtual registers across a call.
...
Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.
llvm-svn: 103927
2010-05-17 02:07:32 +00:00
d2ef1fbc82
Reduce hashtable probes by using DenseMap::insert() for lookup.
...
llvm-svn: 103926
2010-05-17 02:07:29 +00:00
fb43e065a4
Make MBB a class member instead of passing it around everywhere.
...
llvm-svn: 103925
2010-05-17 02:07:22 +00:00
166a7993ba
Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
...
llvm-svn: 103922
2010-05-17 01:47:47 +00:00
5a2809cbd8
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
...
llvm-svn: 103917
2010-05-17 01:11:46 +00:00
2ef974ee0e
Revert 103911; it broke a test that expects bitconvert
...
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
llvm-svn: 103914
2010-05-16 20:19:04 +00:00
fc1492d71b
Make x86-64 64-bit bitconvert work when SSE is not available.
...
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
llvm-svn: 103911
2010-05-16 18:22:38 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
8f35fabbc1
Add support for thiscall calling convention.
...
Patch by Charles Davis and Steven Watanabe!
llvm-svn: 103902
2010-05-16 09:08:45 +00:00
4c719c4515
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
...
llvm-svn: 103901
2010-05-16 08:54:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
...
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
...
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
bb4656c05e
Improve assertion messages.
...
llvm-svn: 103882
2010-05-15 18:38:02 +00:00
1bf28a128b
Some cheap DAG combine goodness for multiplication with a particular constant.
...
This can be extended later on to handle more "complex" constants.
llvm-svn: 103881
2010-05-15 18:16:59 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
9e01b615a4
improve portability to systems that don't have round, patch by
...
Evzen Muller!
llvm-svn: 103877
2010-05-15 17:11:55 +00:00
93cd0f1c89
improve portability to systems that don't have powf/modf (e.g. solaris 9)
...
patch by Evzen Muller!
llvm-svn: 103876
2010-05-15 17:10:24 +00:00
75142e6bfc
Fix an GCC warning that seems to have actually caught a bug (!!!) in
...
a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.
llvm-svn: 103869
2010-05-15 10:23:23 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
...
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
84ce290822
Calculate liveness on the fly for local registers.
...
When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.
This makes the fast allocator independent of incoming kill flags.
llvm-svn: 103866
2010-05-15 06:09:08 +00:00
b35818eb25
Teach the always inliner to release its inline cost estimates, like the basic
...
inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?
llvm-svn: 103858
2010-05-15 04:26:25 +00:00
002a45eb64
Clean up, no functional change.
...
llvm-svn: 103857
2010-05-15 03:41:58 +00:00
3d214cdfaf
v4i64 and v8i64 are only synthesizable when NEON is available.
...
llvm-svn: 103855
2010-05-15 02:20:21 +00:00
4cad68eb34
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
...
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
2010-05-15 02:18:07 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
...
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
e26e56e72b
A partial re-def instruction may be a copy.
...
llvm-svn: 103850
2010-05-15 01:35:44 +00:00
8c2d062ea6
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
...
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-14 23:21:14 +00:00
cb78e5558b
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
...
llvm-svn: 103833
2010-05-14 22:54:52 +00:00
88fb253562
Fast ISel trivially coalesces away no-op casts, so check for this when
...
setting kill flags.
llvm-svn: 103832
2010-05-14 22:53:18 +00:00
089e9421d2
Don't bother spilling before a return
...
llvm-svn: 103831
2010-05-14 22:40:43 +00:00
cdef6bc8de
RegAllocLocal can count copies too
...
llvm-svn: 103830
2010-05-14 22:40:40 +00:00
0160e55893
SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
...
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)
llvm-svn: 103829
2010-05-14 22:17:42 +00:00
b16013936b
Track allocatable instead of reserved regs, and never take an unallocatable hint.
...
llvm-svn: 103828
2010-05-14 22:02:56 +00:00
2f277c866d
Don't set kill flags for instructions which the scheduler has cloned.
...
llvm-svn: 103827
2010-05-14 22:01:14 +00:00
062a97f0f6
BR is a barrier.
...
llvm-svn: 103826
2010-05-14 22:00:27 +00:00
1713d95874
Several tail call tests apparently rely upon this being "adjusts stack" instead
...
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.
llvm-svn: 103824
2010-05-14 21:58:35 +00:00
e68b814c8c
Avoid scanning the long tail of physreg operands on calls
...
llvm-svn: 103823
2010-05-14 21:55:52 +00:00
36debf8046
Do not forget to mark prcessed arguments.
...
llvm-svn: 103822
2010-05-14 21:55:50 +00:00
6c038e33e9
Count coalesced copies
...
llvm-svn: 103821
2010-05-14 21:55:50 +00:00
33af4fcdea
Allow virtreg redefines when verifying for RegAllocFast
...
llvm-svn: 103820
2010-05-14 21:55:44 +00:00
e9ac7ad68c
This should happen if there are no calls, not if it just doesn't adjust the
...
stack.
llvm-svn: 103813
2010-05-14 21:38:44 +00:00
db4bc54c4f
Revert r103804. The comment is correct.
...
llvm-svn: 103808
2010-05-14 21:28:24 +00:00
866b74ba8b
Remove trailing whitespace
...
llvm-svn: 103807
2010-05-14 21:20:46 +00:00
d772bdeb7e
80 column and trailing whitespace cleanup
...
llvm-svn: 103806
2010-05-14 21:19:48 +00:00
25749ad5c2
add cmd line option to leave dbgvalues in during post-RA sceduling. Useful
...
while debugging what's mishandled about them in the post-RA pass.
llvm-svn: 103805
2010-05-14 21:18:04 +00:00
7bf4bae5dc
Fix comment.
...
llvm-svn: 103804
2010-05-14 21:17:29 +00:00
95f6ebcb37
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
...
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
llvm-svn: 103802
2010-05-14 21:14:32 +00:00
35dd005d22
Lowering of atomic instructions can result in operands being
...
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.
llvm-svn: 103799
2010-05-14 21:01:44 +00:00
e0a94bfe9f
Add support to preserve type info for the variables that are removed by the optimizer.
...
llvm-svn: 103798
2010-05-14 21:01:35 +00:00
670492c8ee
When verifying two-address instructions, check the following:
...
- Kill is implicit when use and def registers are identical.
- Only virtual registers can differ.
Add a -verify-fast-regalloc to run the verifier before the fast allocator.
llvm-svn: 103797
2010-05-14 20:28:32 +00:00
7bc111f5a9
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
...
argument, like "int $4", to not get an Assertion error.
llvm-svn: 103791
2010-05-14 19:16:02 +00:00
cfa7d02d6e
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
...
llvm-svn: 103790
2010-05-14 18:54:59 +00:00
2493ddfe42
MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be
...
used to replace a normal relocation, not a reference to a GOT entry.
llvm-svn: 103789
2010-05-14 18:53:40 +00:00
4d5c1061e3
Simplify the handling of physreg defs and uses in RegAllocFast.
...
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.
llvm-svn: 103784
2010-05-14 18:03:25 +00:00
30e3db2ba3
Set isTerminator on TRAP instructions.
...
llvm-svn: 103778
2010-05-14 16:46:02 +00:00
c56ca22616
Don't use isBarrier for the PowerPC sync instruction. isBarrier is for
...
control barriers, not memory ordering barriers.
llvm-svn: 103777
2010-05-14 16:42:16 +00:00
02d9947e60
Add mayLoad and mayStore flags to instructions which missed them.
...
llvm-svn: 103776
2010-05-14 16:34:55 +00:00
148e876ac2
XFAIL the test I added with vg_leak, apparently it is the first and only llc
...
-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we
need to sort out the ownership model for the various MC objects.
llvm-svn: 103769
2010-05-14 07:47:51 +00:00
3439ed6324
Inline Asm: Ensure buffer is newline terminated to match how the text is printed.
...
- This is a hack, but I can't decide the best place to handle this. Chris?
llvm-svn: 103765
2010-05-14 04:31:50 +00:00
ceb5a7ada2
Enable opportunistic coalescing
...
llvm-svn: 103764
2010-05-14 04:30:51 +00:00
cd67c21407
Added a QQQQ register file to model 4-consecutive Q registers.
...
llvm-svn: 103760
2010-05-14 02:13:41 +00:00
9fb6bb07ca
Add AsmParser support for darwin tbss directive.
...
Nothing uses this yet.
llvm-svn: 103757
2010-05-14 01:50:28 +00:00
bc81885ff7
Fix a couple of typos.
...
llvm-svn: 103756
2010-05-14 01:38:54 +00:00
4bce748aa2
MC: Switch to completely lazy layout.
...
- The eliminates the last major algorithmic problem with MC.
llvm-svn: 103754
2010-05-14 00:51:14 +00:00
9abade1017
MC: Extend MCAsmLayout to explicitly track which fragments have been layed out, and enforce several invariants to LayoutFragment to ensure we only do layout in a sensible order.
...
llvm-svn: 103753
2010-05-14 00:37:21 +00:00
3eedc26e18
MC: Implicitly assign section addresses when the previous fragment is layed out.
...
llvm-svn: 103752
2010-05-14 00:37:17 +00:00
8f9d2266e6
MC: Switch MCFragment to storing the layout order index, not its index in the file.
...
llvm-svn: 103751
2010-05-14 00:37:14 +00:00
a99a23b061
MC: Change LayoutSection() to only do the section initializiation.
...
Also, elimminate MCAsmLayout::set*, which are no longer needed.
llvm-svn: 103750
2010-05-14 00:37:11 +00:00
ca21cc8b13
Fix comments.
...
llvm-svn: 103749
2010-05-14 00:21:45 +00:00
68c235bd4d
Trust kill flags from isel and later passes.
...
llvm-svn: 103748
2010-05-14 00:02:23 +00:00
41f8dc897e
Fix an embarrassing runtime regression for RegAllocFast.
...
This loop is quadratic in the capacity for a DenseMap:
while(!map.empty())
map.erase(map.begin());
Instead we now do a normal begin() - end() iteration followed by map.clear().
That also has the nice sideeffect of shrinking the map capacity on demand.
llvm-svn: 103747
2010-05-14 00:02:20 +00:00
670a4104a9
Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
...
llvm-svn: 103746
2010-05-13 23:55:47 +00:00
1ae94b9394
Implement a correct ui64->f32 conversion. The old
...
one was subject to double rounding in extreme cases.
llvm-svn: 103744
2010-05-13 23:50:42 +00:00
d74a564feb
Clean up RegAllocFast debug output
...
llvm-svn: 103739
2010-05-13 20:43:17 +00:00
b9f6ac094a
MC: Move Layout{Fragment,Section} into MCAsmLayout, and add LayoutFile().
...
llvm-svn: 103738
2010-05-13 20:40:12 +00:00
c90f51c00b
Teach MachineLICM and MachineSink how to clear kill flags conservatively
...
when they move instructions.
llvm-svn: 103737
2010-05-13 20:34:42 +00:00
2ca1bd119e
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
...
llvm-svn: 103731
2010-05-13 20:02:08 +00:00
208dc08c2b
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
...
Do not use those for Thumb1 functions.
llvm-svn: 103730
2010-05-13 19:58:24 +00:00
82135e5a2f
CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936.
...
Patch by Dimitry Andric!
llvm-svn: 103727
2010-05-13 19:34:06 +00:00
7767d2747b
Add a utility function for conservatively clearing kill flags, and make
...
use of it in MachineCSE.
llvm-svn: 103726
2010-05-13 19:24:00 +00:00
5b510c1474
An Instruction has a trivial kill only if its use is in the same
...
basic block.
llvm-svn: 103725
2010-05-13 19:19:32 +00:00
454ea716a3
MC: Factor out MCAssembler::ComputeFragmentSize.
...
llvm-svn: 103724
2010-05-13 18:35:06 +00:00
484c6fc825
MC: Add section layout order indices to MCSectionData.
...
llvm-svn: 103715
2010-05-13 15:17:26 +00:00
aa8bd69886
MC: Move ordinal calculation, to make sure fragments synthesized for layout get assigned ordinals properly.
...
llvm-svn: 103711
2010-05-13 08:43:37 +00:00
e73353c720
MC: Create dummy fragments to avoid ever having empty sections, which simplifies layout.
...
llvm-svn: 103710
2010-05-13 08:43:34 +00:00
e8845ef4db
MC: Add MCAsmLayout::FragmentReplaced() helper function.
...
llvm-svn: 103709
2010-05-13 08:43:31 +00:00
449df9698f
Properly set thread-local flag on globals during cpp emission
...
llvm-svn: 103702
2010-05-13 07:41:57 +00:00
2b3cbac0ee
Remove heinous tabs.
...
llvm-svn: 103700
2010-05-13 06:45:13 +00:00
d3c6dfe853
Replace the core comparison login in merge functions. We can now merge
...
vector<>::push_back() in:
int foo(vector<int> &a, vector<unsigned> &b) {
a.push_back(10);
b.push_back(11);
}
to two calls to the same push_back function, or fold away the two copies of
push_back() in:
struct T { int; };
struct S { char; };
vector<T*> t;
vector<S*> s;
void f(T *x) { t.push_back(x); }
void g(S *x) { s.push_back(x); }
but leave f() and g() separate, since they refer to two different global
variables.
llvm-svn: 103698
2010-05-13 05:48:45 +00:00
5a93253fc8
Fix -Asserts warning.
...
llvm-svn: 103697
2010-05-13 03:50:50 +00:00
d83889bd87
MC: Eliminate MCSectionData::{,Address,File}Size, which can now be computed by
...
utility functions.
llvm-svn: 103695
2010-05-13 03:19:50 +00:00
a58dc0ffdb
Fix -Asserts warning.
...
llvm-svn: 103694
2010-05-13 03:19:36 +00:00
c7c53ea715
MC: Switch to using explicit MCAlignFragments with OnlyAlignAddress bit instead
...
of manually doing padding/editing layout in LayoutSection().
- This probably seems like six-of-one and half-dozen of another, but there
is a method to my madness.
llvm-svn: 103693
2010-05-13 02:34:14 +00:00
9de7cfe3f4
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
...
llvm-svn: 103692
2010-05-13 01:12:06 +00:00
a6780da661
MC: Add MCAlignFragment::OnlyAlignAddress bit. This is a bit of magic that says the align fragment shouldn't contribute to the logical section size, it is will be used for cleaning up the code to handle section alignment.
...
llvm-svn: 103690
2010-05-13 01:10:26 +00:00
4dac59dcb7
MC: Add MCSectionData::AddressSize, which is the size of the address space consumed by the section. This can differ from both the section logical size, and the section size on disk (although the current code handles this without making an explicit distinction).
...
llvm-svn: 103689
2010-05-13 01:10:22 +00:00
0ba2e2a568
Take allocation hints from copy instructions to/from physregs.
...
This causes way more identity copies to be generated, ripe for coalescing.
llvm-svn: 103686
2010-05-13 00:19:43 +00:00
680b74941f
More asserts around physreg uses
...
llvm-svn: 103685
2010-05-13 00:19:39 +00:00
2f736c9577
Expand VMOVQQ into a pair of VMOVQ.
...
llvm-svn: 103684
2010-05-13 00:17:02 +00:00
79efd71962
Mark some pattern-less instructions as neverHasSideEffects.
...
llvm-svn: 103683
2010-05-13 00:16:46 +00:00
8cb4728a15
fix rdar://7965971 and a fixme: use ParseIdentifier in
...
ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.
llvm-svn: 103682
2010-05-13 00:10:34 +00:00
9efef006cf
reapply r103668 with a fix. Never make "minor syntax changes"
...
after testing before committing.
llvm-svn: 103681
2010-05-13 00:02:47 +00:00
4aab8b5425
If REG_SEQUENCE source is livein, copy it first. Also, update livevariables information when a copy is introduced.
...
llvm-svn: 103680
2010-05-13 00:00:35 +00:00
ecf0166012
Do not attempt copy coalescing if the source and dest sub-register indices do not match.
...
llvm-svn: 103679
2010-05-12 23:59:42 +00:00
e354235512
revert r103668 for now, it is apparently breaking things.
...
llvm-svn: 103677
2010-05-12 23:40:59 +00:00
a6df4650fd
moffset forms of moves are x86-32 only, make the parser
...
lower them to the correct x86-64 instructions since we
don't have a clean way to handle this in td files yet.
rdar://7947184
llvm-svn: 103668
2010-05-12 23:13:36 +00:00
7c1f56f29a
Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
...
llvm-svn: 103667
2010-05-12 23:13:12 +00:00
b76df22a2e
MC: Move MCAlignFragment::EmitNops value out of the constructor.
...
llvm-svn: 103665
2010-05-12 22:56:23 +00:00
4405ffc688
MC: Eliminate MCZeroFillFragment, it is no longer needed.
...
llvm-svn: 103664
2010-05-12 22:51:38 +00:00
7cd309f7dc
MC: Explicitly check that only virtual fragments appear in virtual sections.
...
llvm-svn: 103663
2010-05-12 22:51:35 +00:00
597eb48168
MC: Switch MCFillFragment to storing total fill size instead of a count. This allows using ValueSize==0 to represent a virtual fill.
...
llvm-svn: 103662
2010-05-12 22:51:32 +00:00
51402b79e4
MC: Drop support for alignment in ZeroFill fragment, we can just use
...
MCAlignFragments for this.
llvm-svn: 103661
2010-05-12 22:51:27 +00:00
e132b0a92c
fix the encoding of the obscure "moffset" forms of moves, i386
...
part first. rdar://7947184
llvm-svn: 103660
2010-05-12 22:48:24 +00:00
c63aa1e8ab
Clear CachedFunctionInfo upon Pass::releaseMemory. Because ValueMap will abort
...
on RAUW of functions, this is a correctness issue instead of a mere memory
usage problem.
No testcase until the new MergeFunctions can land.
llvm-svn: 103653
2010-05-12 21:48:15 +00:00
7d73564b82
Simplify.
...
llvm-svn: 103651
2010-05-12 21:47:55 +00:00
a7cc32a7b6
MC: Factor out MCAssembler::LayoutFragment
...
llvm-svn: 103649
2010-05-12 21:35:25 +00:00
2abec791f1
MC: Tweak section layout to not relying on accumulating address value.
...
llvm-svn: 103648
2010-05-12 21:35:22 +00:00
5aa20d6c26
Remove a dead fixme.
...
llvm-svn: 103642
2010-05-12 20:20:22 +00:00
955a0e71e9
Make sure to add kill flags to the last use of a virtreg when it is redefined.
...
The X86 floating point stack pass and others depend on good kill flags.
llvm-svn: 103635
2010-05-12 18:46:03 +00:00
a11479eb49
MC: Simplify LayoutSection to just take the index of the section to layout.
...
llvm-svn: 103627
2010-05-12 17:56:47 +00:00
e02c1f6834
MC: Track section layout order explicitly, and use to simplify.
...
llvm-svn: 103616
2010-05-12 15:42:59 +00:00
d2de49ddda
stylistic change to MCSectionCOFF::PrintSwitchToSection COMDAT handling
...
Made a stylistic changed to the code/comments related to the unsupported COMDAT selection type IMAGE_COMDAT_SELECT_LARGEST based on from Anton Korobeynikov.
llvm-svn: 103590
2010-05-12 07:36:03 +00:00
2576db727b
Remove unused variable. Tweak a comment while there.
...
llvm-svn: 103586
2010-05-12 07:11:33 +00:00
b69c7b76f1
Add support for movi32 of global values to the new (MC) asm printer.
...
llvm-svn: 103576
2010-05-12 05:16:34 +00:00
76a07580ad
updated support for the COFF .linkonce
...
Now, the .linkonce directive is emitted as part of MCSectionCOFF::PrintSwitchToSection instead of AsmPrinter::EmitLinkage since it is an attribute of the section the symbol was placed into not the symbol itself.
llvm-svn: 103568
2010-05-12 04:26:09 +00:00
a2ff4fc96a
vst instructions are modeled as this:
...
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
= VSTxx <addr>, v1025, v1026
The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
= VSTxx <addr>, v1024:5, v1024:6
The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.
As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.
Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.
llvm-svn: 103540
2010-05-12 01:42:50 +00:00
d593448643
Teach local regalloc about virtual registers with sub-indices.
...
llvm-svn: 103539
2010-05-12 01:29:36 +00:00
0c6ebc7d95
Code clean up.
...
llvm-svn: 103538
2010-05-12 01:27:49 +00:00
059379a9d7
MC/X86: Extend suffix matching hack to match 'q' suffix.
...
llvm-svn: 103535
2010-05-12 00:54:20 +00:00
ba2f4c3884
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
...
be diced into atoms, and adjust getAtom() to take this into account.
- This fixes relocations to symbols in fixed size literal sections, for
example.
llvm-svn: 103532
2010-05-12 00:38:17 +00:00
f98a355f9b
Avoid scoping issues, fix buildbots
...
llvm-svn: 103530
2010-05-12 00:11:19 +00:00
1a1b51ff59
Add initial kill flag support to FastISel.
...
llvm-svn: 103529
2010-05-11 23:54:07 +00:00
69b8f42400
Make Clang happy.
...
llvm-svn: 103528
2010-05-11 23:53:13 +00:00
53ce0e12d8
MC/Mach-O/x86_64: Fix PCrel adjustment for x86_64, which was using the fixup
...
offset instead of the fixup address as intended.
llvm-svn: 103527
2010-05-11 23:53:11 +00:00
7c6f0e3827
MC/Mach-O: As Kevin pointed out, 'Address' is really an offset -- rename to clarify.
...
llvm-svn: 103526
2010-05-11 23:53:07 +00:00
795baa1972
MC/Mach-O: Fix a crash on invalid.
...
llvm-svn: 103525
2010-05-11 23:53:05 +00:00
11f1ba1535
Store the Dirty bit in the LiveReg structure instead of a bit vector.
...
llvm-svn: 103522
2010-05-11 23:24:47 +00:00
132668102e
Keep track of the last place a live virtreg was used.
...
This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.
llvm-svn: 103521
2010-05-11 23:24:45 +00:00
afd2b8bbb7
Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't
...
create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.
llvm-svn: 103519
2010-05-11 21:59:14 +00:00
44e865f487
Avoid breaking vstd when reg_sequence is not used.
...
llvm-svn: 103513
2010-05-11 21:07:36 +00:00
f25be99109
Silence warning
...
llvm-svn: 103508
2010-05-11 20:51:04 +00:00
508f661fbe
Simplify this logic of creating a default Features object.
...
llvm-svn: 103507
2010-05-11 20:46:04 +00:00
3f0241e0f9
Simplify the tracking of used physregs to a bulk bitor followed by a transitive
...
closure after allocating all blocks.
Add a few more test cases for -regalloc=fast.
llvm-svn: 103500
2010-05-11 20:30:28 +00:00
e7630be7c5
Revert r103493, materializing functions in the regular PassManager.
...
It works in simple cases, but it isn't a general solution.
llvm-svn: 103499
2010-05-11 20:30:00 +00:00
6c5e4355bb
I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it
...
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.
llvm-svn: 103495
2010-05-11 20:16:09 +00:00
860d669da2
Teach the regular pass manager how to materialize functions as needed.
...
llvm-svn: 103493
2010-05-11 19:58:43 +00:00
4cfccb801c
Remove the "WantsWholeFile" concept, as it's no longer needed. CBE
...
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.
llvm-svn: 103492
2010-05-11 19:57:55 +00:00
9132c59d43
Trim #includes and forward declarations.
...
llvm-svn: 103489
2010-05-11 19:11:43 +00:00
f1b3029a54
Mostly rewrite RegAllocFast.
...
Sorry for the big change. The path leading up to this patch had some TableGen
changes that I didn't want to commit before I knew they were useful. They
weren't, and this version does not need them.
The fast register allocator now does no liveness calculations. Instead it relies
on kill flags provided by isel. (Currently those kill flags are also ignored due
to isel bugs). The allocation algorithm is supposed to work with any subset of
valid kill flags. More kill flags simply means fewer spills inserted.
Registers are allocated from a working set that contains no aliases. That means
most allocations can be done directly without expensive alias checks. When the
working set runs out of registers we do the full alias check to find new free
registers.
llvm-svn: 103488
2010-05-11 18:54:45 +00:00
bb919dfb6b
Implement a bunch more TargetSelectionDAGInfo infrastructure.
...
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.
llvm-svn: 103481
2010-05-11 17:31:57 +00:00
3937e28da0
MC/Mach-O x86_64: Switch to using fragment atom symbol.
...
- This eliminates getAtomForAddress() (which was a linear search) and
simplifies getAtom().
- This also fixes some correctness problems where local labels at the same
address as non-local labels could be assigned to the wrong atom.
llvm-svn: 103480
2010-05-11 17:22:50 +00:00
4df9d9ce11
Remove the TargetLowering::getSubtarget() virtual function, which
...
was unused. TargetMachine::getSubtarget() is used instead.
llvm-svn: 103474
2010-05-11 16:21:03 +00:00
9dd3ef8d01
Make SPU backend not assert on jump tables.
...
llvm-svn: 103466
2010-05-11 11:00:02 +00:00
2fa5a7e7e4
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
...
llvm-svn: 103459
2010-05-11 07:26:32 +00:00
6739a89117
Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
...
llvm-svn: 103457
2010-05-11 06:17:44 +00:00
ea31737fef
Don't create a StringRef with a NULL value.
...
llvm-svn: 103455
2010-05-11 01:33:39 +00:00
e276c18385
Model some vst3 and vst4 with reg_sequence.
...
llvm-svn: 103453
2010-05-11 01:19:40 +00:00
a12c1ff25a
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
...
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.
Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.
llvm-svn: 103451
2010-05-11 00:30:02 +00:00
1ef0660836
It's not safe eliminate copies where src and dst have different sub-register indices.
...
llvm-svn: 103450
2010-05-11 00:20:03 +00:00
b58b6f9a85
Ensure REG_SEQUENCE source operands are unique.
...
llvm-svn: 103449
2010-05-11 00:04:31 +00:00
75778984f9
MC/Mach-O: Fix another mismatch with .weak_definition, we shouldn't use a
...
scattered relocation entry with a .weak_definition.
llvm-svn: 103443
2010-05-10 23:15:20 +00:00
7de3106a89
MC/Mach-O: Factor out doesSymbolRequireExternRelocation.
...
llvm-svn: 103442
2010-05-10 23:15:13 +00:00
ffb9f18dfe
Indentation.
...
llvm-svn: 103441
2010-05-10 23:08:19 +00:00
1a0df9a80e
Enable multiple Compile Units in one module.
...
This means now 'llvm-ld a.bc b.bc' will preserve debug info appropriately.
llvm-svn: 103439
2010-05-10 22:49:55 +00:00
aadb2cac49
MC/Mach-O: Explicitly track atoms, as represented by their defining symbol, for each fragment (not yet used).
...
llvm-svn: 103438
2010-05-10 22:45:09 +00:00
630063aa0d
Model some vld3 instructions with REG_SEQUENCE.
...
llvm-svn: 103437
2010-05-10 21:26:24 +00:00
d6908dc4a2
It's not safe to propagate implicit_def that defines part of a register.
...
llvm-svn: 103436
2010-05-10 21:25:30 +00:00
9d55b23425
Clear RegSequences vector after eliminating REG_SEQUENCE instructions.
...
llvm-svn: 103435
2010-05-10 21:24:55 +00:00
42dbe4943f
simplify more.
...
llvm-svn: 103431
2010-05-10 20:59:18 +00:00
609de0068a
Simplify by using startswith instead of substr.
...
llvm-svn: 103430
2010-05-10 20:58:42 +00:00
58aff8fb57
fix PR7105 by enumerating MDNodes on all @llvm.foo
...
function calls, not just recognized intrinsics.
llvm-svn: 103428
2010-05-10 20:53:17 +00:00
103d4b43e9
Fix PR6875:
...
This includes a patch by Roman Divacky to fix the initial crash.
Move the actual addition of passes from *PassManager::add to
*PassManager::addImpl. That way, when adding printer passes we won't
recurse infinitely.
Finally, check to make sure that we are actually adding a FunctionPass
to a FunctionPassManager before doing a print before or after it.
Immutable passes are strange in this way because they aren't
FunctionPasses yet they can be and are added to the FunctionPassManager.
llvm-svn: 103425
2010-05-10 20:24:27 +00:00
dac182450b
Add new configure option, --disable-timestamps, intended to turn off anything which would mess up binary/object comparisons. Currently:
...
- Disables 'Built on ...' in 'foo --version'.
- Disables timestamps from being embedded into .dir files.
llvm-svn: 103423
2010-05-10 20:11:56 +00:00
bf2fb95b7c
Fix whitespace in debug output to be consistent.
...
llvm-svn: 103422
2010-05-10 20:07:44 +00:00
02947a4551
Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869.
...
llvm-svn: 103419
2010-05-10 19:03:57 +00:00
c2ae5f546f
Model vld2 / vst2 with reg_sequence.
...
llvm-svn: 103411
2010-05-10 17:34:18 +00:00
faef5d0281
Re-defined valno is always valno even for partial re-def's.
...
llvm-svn: 103410
2010-05-10 17:33:49 +00:00
01fcdaa7f5
Fix PR7096. When a block containing multiple defs is tail duplicated, the
...
SSAUpdater for the value from the first def may see uses of undefined values,
because the later defs will not have been updated yet.
llvm-svn: 103407
2010-05-10 17:14:26 +00:00
92ea401d8f
Fix encoding of 'sf' and 'sfh' instructions.
...
llvm-svn: 103399
2010-05-10 08:13:49 +00:00
e4d6670f6b
Add an assertion to catch attempts to access off the end of the array.
...
Based on a patch by Javier Martinez.
llvm-svn: 103391
2010-05-10 04:54:28 +00:00
b19c598843
updated handling dllexport in X86AsmPrinter
...
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform
llvm-svn: 103377
2010-05-09 08:40:06 +00:00
2760216c89
made COFF target dllexport logic apply to all subtargets
...
llvm-svn: 103373
2010-05-09 05:52:28 +00:00
da7d01404d
test commit, added a comment to MCSectionCOFF::PrintSwitchToSection function
...
llvm-svn: 103372
2010-05-09 05:49:00 +00:00
84d4618659
make simplifycfg insert an llvm.trap before the 'unreachable' it introduces
...
when it detects undefined behavior. llvm.trap generally codegens into some
thing really small (e.g. a 2 byte ud2 instruction on x86) and debugging this
sort of thing is "nontrivial". For example, we now compile:
void foo() { *(int*)0 = 42; }
into:
_foo:
pushl %ebp
movl %esp, %ebp
ud2
Some may even claim that this is a security hole, though that seems dubious
to me. This addresses rdar://7958343 - Optimizing away null dereference
potentially allows arbitrary code execution
llvm-svn: 103356
2010-05-08 22:15:59 +00:00
02b0df5338
Teach instcombine to transform a bitcast/(zext|trunc)/bitcast sequence
...
with a vector input and output into a shuffle vector. This sort of
sequence happens when the input code stores with one type and reloads
with another type and then SROA promotes to i96 integers, which make
everyone sad.
This fixes rdar://7896024
llvm-svn: 103354
2010-05-08 21:50:26 +00:00
5a62d6e578
Fix PR7052, patch by Jakub Staszak!
...
llvm-svn: 103347
2010-05-08 20:01:44 +00:00
72afa956db
break coff symbol definition stuff out into proper MCStreamer callbacks,
...
patch by Nathan Jeffords!
llvm-svn: 103346
2010-05-08 19:54:22 +00:00
401d4c9341
Run interrupt routines as part of report_fatal_error, since we are failing
...
ungracefully.
llvm-svn: 103334
2010-05-08 02:10:36 +00:00
68272566c6
Add llvm::sys::RunInterruptHandlers(), which runs the registered SIGINT cleanup
...
stuff.
llvm-svn: 103333
2010-05-08 02:10:34 +00:00
d0800241d2
When pruning candidate formulae out of an LSRUse, update the
...
LSRUse's Regs set after all pruning is done, rather than trying
to do it on the fly, which can produce an incomplete result.
This fixes a case where heuristic pruning was stripping all
formulae from a use, which led the solver to enter an infinite
loop.
Also, add a few asserts to diagnose this kind of situation.
llvm-svn: 103328
2010-05-07 23:36:59 +00:00
0625af2a88
Instead of just verifying compile unit, verify entire type, variable, namespace etc..
...
llvm-svn: 103327
2010-05-07 23:33:41 +00:00
cbe7a8508a
Remove DIGlobal.
...
llvm-svn: 103325
2010-05-07 23:19:07 +00:00
54c59312b1
Add DINameSpace::Verify().
...
llvm-svn: 103318
2010-05-07 23:04:32 +00:00
7de01ec2c9
SDDbgValues are apparently not being legalized. Fix a symptom of the problem,
...
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.
llvm-svn: 103310
2010-05-07 22:19:08 +00:00
2fb68300a0
Minimally fix this code to not abort on mdnodes with integer data
...
wider than 64 bits.
llvm-svn: 103309
2010-05-07 22:15:24 +00:00
2ae3397536
Verify variable directly.
...
llvm-svn: 103305
2010-05-07 22:04:20 +00:00
028449325b
add COFF support for COMDAT sections, patch by Nathan Jeffords!
...
llvm-svn: 103304
2010-05-07 21:49:09 +00:00
8d6a2b7428
Verify entire type descriptor not just tag.
...
llvm-svn: 103303
2010-05-07 21:45:47 +00:00
51bed9c870
Fix i386 relocations to Weak Definitions. The relocation entries should be
...
external and the item to be relocated should not have the address of the
symbol added in.
llvm-svn: 103302
2010-05-07 21:44:23 +00:00
2c4d69d7ad
Verify compile unit also.
...
llvm-svn: 103300
2010-05-07 21:42:24 +00:00
51c1695a0a
Fix PR 7087, and probably other things, by extending
...
getConstantFP to accept the two supported long double
target types. This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.
llvm-svn: 103299
2010-05-07 21:35:53 +00:00
32cc43c242
Wrap const MDNode * inside DIDescriptor.
...
llvm-svn: 103295
2010-05-07 20:54:48 +00:00
2a41cad900
Clean up the conditional for handling of sign_extend_inreg based on
...
whether the extract instructions are available.
rdar://7956878
llvm-svn: 103277
2010-05-07 18:34:55 +00:00
4423abd734
Use overloaded operators instead of DIDescriptor::getNode()
...
llvm-svn: 103276
2010-05-07 18:19:32 +00:00
cfa8e9d45f
Avoid DIDescriptor::getNode(). Use overloaded operators instead.
...
llvm-svn: 103272
2010-05-07 18:11:54 +00:00
b3c5c4611c
Testing svn access with a note added to documentation.
...
llvm-svn: 103271
2010-05-07 18:06:28 +00:00
58a0bd48ad
Update CMake build.
...
llvm-svn: 103269
2010-05-07 17:29:48 +00:00
87cffa9498
switch MCSectionCOFF from a syntactic to semantic representation,
...
patch by Peter Housel!
llvm-svn: 103267
2010-05-07 17:17:41 +00:00
d90773ebe0
Update CMake build.
...
llvm-svn: 103266
2010-05-07 17:13:20 +00:00
50689f0bb9
Add some words to this output to indicate what the numbers mean.
...
llvm-svn: 103264
2010-05-07 16:39:27 +00:00
fb64b5dff4
Add a simple module-level debug info printer. It just sets up a
...
DebugInfoFinder and iterates over all the contents calling print.
llvm-svn: 103262
2010-05-07 16:22:32 +00:00
6c30e879f8
Fix the new print functions to call print instead of dump.
...
llvm-svn: 103261
2010-05-07 16:17:22 +00:00
5d5b8b1b8c
Add an LLVM IR version of code sinking. This uses the same simple algorithm
...
as MachineSink, but it isn't constrained by MachineInstr-level details.
llvm-svn: 103257
2010-05-07 15:40:13 +00:00
4bbcf644da
Convert the DebugInfo classes dump() methods into print(raw_ostream &)
...
methods, and add dump functions implemented in terms of the print.
llvm-svn: 103254
2010-05-07 15:30:29 +00:00
86eb22976f
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
...
llvm-svn: 103235
2010-05-07 02:04:02 +00:00
04d47e8efa
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
...
llvm-svn: 103234
2010-05-07 01:54:08 +00:00
45f530db39
Revert r103133 and add testcase from PR7066.
...
llvm-svn: 103233
2010-05-07 01:45:38 +00:00
90c600d6d2
When rematerializing, use the debug location of the original
...
instruction, rather than a location near where the new instruction
is being inserted.
llvm-svn: 103232
2010-05-07 01:28:10 +00:00
e6d40166a8
Transfer debug location information from PHI nodes to resulting
...
lowered copies.
llvm-svn: 103228
2010-05-07 01:10:20 +00:00
e7dff14d5d
Print debug information for SDNodes.
...
llvm-svn: 103227
2010-05-07 01:09:21 +00:00
7421ae48bf
Disable the new unknown-location code for now. It causes a major
...
increase in the debug line info section, and it's causing
regressions in a gdb testsuite.
llvm-svn: 103226
2010-05-07 01:08:53 +00:00
ddc93c7e04
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
...
llvm-svn: 103218
2010-05-07 00:24:52 +00:00
21aa523c28
MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand.
...
- This fixes "leal 0, %eax", for example.
llvm-svn: 103205
2010-05-06 22:39:14 +00:00
348dc9b15a
fix rdar://7947167 - llvm-mc doesn't match movsq
...
llvm-svn: 103199
2010-05-06 21:48:14 +00:00
e7e1cf9fbd
Eliminated the classification of control registers into %ecr_
...
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
llvm-svn: 103196
2010-05-06 20:59:00 +00:00
358b29c855
MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since
...
we don't currently support relaxing them.
llvm-svn: 103195
2010-05-06 20:34:01 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
...
doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
...
llvm-svn: 103193
2010-05-06 19:06:44 +00:00
f0ac19a6d5
80 col violation.
...
llvm-svn: 103185
2010-05-06 16:33:12 +00:00
f765e1f34a
Add a missing break statement to fix unintentional fall-through
...
(replacing the previous patch for the same issue).
llvm-svn: 103183
2010-05-06 16:05:26 +00:00
5e3cccb1e4
Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com>
...
llvm-svn: 103181
2010-05-06 15:32:49 +00:00
94231eec1f
Fix "warning: extra ';' inside a struct or union" when building llvm with clang
...
llvm-svn: 103179
2010-05-06 14:57:47 +00:00
b0ceb764b8
Revert r103137, fix for $ in labels. It looks like we can't actually handle this
...
at the token level. Consider the following horrible test case:
a = 1
.globl $a
movl ($a), %eax
movl $a, %eax
movl $$a, %eax
llvm-svn: 103178
2010-05-06 14:46:38 +00:00
31cdcd46d6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
...
llvm-svn: 103172
2010-05-06 06:36:08 +00:00
c0255bac1d
Fixes a coalescer bug that caused llc to crash on 2009-11-30-LiveVariablesBug.ll
...
with the fix in 103157.
%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.
llvm-svn: 103170
2010-05-06 06:23:31 +00:00
77c71811f5
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
...
llvm-svn: 103163
2010-05-06 05:08:57 +00:00
9feb1bb117
Revert r103156 since it was breaking the build bots.
...
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
llvm-svn: 103159
2010-05-06 02:29:06 +00:00
d351116be0
Handle the case where open(2) or close(2) is interrupted by a signal when
...
automatic syscall restarting is disabled.
Also, fix the build on systems which don't define EWOULDBLOCK.
llvm-svn: 103158
2010-05-06 02:06:20 +00:00
8fd7b510d6
Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.
...
llvm-svn: 103157
2010-05-06 01:54:03 +00:00
8f99a1c6b4
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
...
llvm-svn: 103156
2010-05-06 01:52:03 +00:00
9d768f4445
Cosmetic changes.
...
llvm-svn: 103155
2010-05-06 01:34:11 +00:00
718ff448df
storeRegToStackSlot has forgotten about QPR_8 register class.
...
llvm-svn: 103154
2010-05-06 01:32:54 +00:00
ef969f3539
Handle EWOULDBLOCK as EAGAIN. And add a comment explaining why
...
EAGAIN and EWOULDBLOCK are used here.
Also, handle the case where a write call is interrupted after
some data has already been written.
llvm-svn: 103153
2010-05-06 01:27:36 +00:00
47d04e3e41
Update LabelsBeforeInsn also, when creating unknown-position labels.
...
llvm-svn: 103145
2010-05-06 00:29:41 +00:00
35096e82c5
Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed.
...
Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.
llvm-svn: 103140
2010-05-06 00:05:37 +00:00
a7c717d8d4
In bottom-up mode, defer the materialization of local constant values.
...
llvm-svn: 103139
2010-05-06 00:02:14 +00:00
ffcb590b0f
Add an "IsBottomUp" member function to FastISel, which will be used to
...
support a new bottom-up mode.
llvm-svn: 103138
2010-05-05 23:58:35 +00:00
482fa218d4
fix rdar://7946934 - in some limited cases, the assembler should
...
allow $ at the start of a symbol name.
llvm-svn: 103137
2010-05-05 23:51:28 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
50849c63e4
Emit debug info for MachineInstrs with unknown debug locations, instead
...
of just letting them inherit the debug locations of adjacent instructions.
Debug info should aim to be either accurate or absent.
llvm-svn: 103135
2010-05-05 23:41:32 +00:00
1b6f698e85
Fix PR6520. An earlyclobber physreg must not be allocated to anything else.
...
llvm-svn: 103133
2010-05-05 23:07:41 +00:00
4cd930f417
Fixed a sign-extension bug in the X86 disassembler
...
that was causing PC-relative branch targets to be
evaluated incorrectly. Also added support for
checking operand values to the llvm-mc tester.
llvm-svn: 103128
2010-05-05 22:47:27 +00:00
92b21cad5d
Use getValue() for PHINodes when direct NodeMap access does not work.
...
llvm-svn: 103126
2010-05-05 22:29:00 +00:00
61908f6b6c
Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.
...
llvm-svn: 103124
2010-05-05 22:15:40 +00:00
f62cd20b62
No-ops emitted for scheduling don't correspond with anything in the
...
user's source, so don't arbitrarily assign them a debug location.
llvm-svn: 103121
2010-05-05 20:58:01 +00:00
92d999001c
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
...
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
llvm-svn: 103119
2010-05-05 20:44:35 +00:00
0c8b29bcdb
Use the right version of "append" to combine two SmallVectors.
...
This fixes the compile-time regressions seen in last night's tests.
llvm-svn: 103118
2010-05-05 20:44:15 +00:00
f3a53baf00
MC/Mach-O: Mark absolute variable's appropriately, and add Mach-O support for
...
writing them.
- <rdar://problem/7885351> integrated assembler broken for i386 objc code
llvm-svn: 103112
2010-05-05 19:01:05 +00:00
deb7ba9cc0
MC: Reject attempts to define a variable symbol.
...
llvm-svn: 103111
2010-05-05 19:01:00 +00:00
8557426958
MC: Make setVariableValue check the redefinition condition a bit more strongly.
...
llvm-svn: 103110
2010-05-05 19:00:56 +00:00
4b6abd8c2b
Move REG_SEQUENCE removal to 2addr pass.
...
llvm-svn: 103109
2010-05-05 18:45:40 +00:00
d7f69cb7ef
Implement rdar://7415680 - Twine integer support lacks greatness
...
Microoptimize Twine's with unsigned and int to not pin their value to
the stack. This saves stack space in common cases and allows mem2reg
in the caller. A simple example is:
void foo(const Twine &);
void bar(int x) {
foo("xyz: " + Twine(x));
}
Before:
__Z3bari:
subq $40, %rsp
movl %edi, 36(%rsp)
leaq L_.str3(%rip), %rax
leaq 36(%rsp), %rcx
leaq 8(%rsp), %rdi
movq %rax, 8(%rsp)
movq %rcx, 16(%rsp)
movb $3, 24(%rsp)
movb $7, 25(%rsp)
callq __Z3fooRKN4llvm5TwineE
addq $40, %rsp
ret
After:
__Z3bari:
subq $24, %rsp
leaq L_.str3(%rip), %rax
movq %rax, (%rsp)
movslq %edi, %rax
movq %rax, 8(%rsp)
movb $3, 16(%rsp)
movb $7, 17(%rsp)
leaq (%rsp), %rdi
callq __Z3fooRKN4llvm5TwineE
addq $24, %rsp
ret
It saves 16 bytes of stack and one instruction in this case.
llvm-svn: 103107
2010-05-05 18:40:33 +00:00
d85631e700
Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.
...
llvm-svn: 103104
2010-05-05 18:28:36 +00:00
5ab29366b5
Trim include.
...
llvm-svn: 103103
2010-05-05 18:27:57 +00:00
38d9a6f805
Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
...
80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
llvm-svn: 103102
2010-05-05 18:27:40 +00:00
7a989da0af
MC: Rename MCSymbol::{g,s}etValue -> MCSymbol::{g,s}etVariableValue.
...
llvm-svn: 103095
2010-05-05 17:41:00 +00:00
027fa5f31c
MC/Mach-O/x86_64: Relocations in debug sections should use local relocations
...
when possible.
- <rdar://problem/7934873>
llvm-svn: 103092
2010-05-05 17:22:39 +00:00
ce84a2558c
Try again if write(2) reports an recoverable error.
...
This should fix mysteriously crashing boost regression tests when stderr is
managed by bjam (PR7043).
llvm-svn: 103085
2010-05-05 15:17:47 +00:00
4e7e4e6b60
Revert 102941, we're going to do this via attr and can just
...
hack the code to turn it off when debugging.
llvm-svn: 103083
2010-05-05 07:35:59 +00:00
d1b38e317d
Combine the implementations of the core part of the SSAUpdater and
...
MachineSSAUpdater to avoid duplicating all the code.
llvm-svn: 103060
2010-05-04 23:18:19 +00:00
a00830df31
Update comment.
...
llvm-svn: 103057
2010-05-04 22:13:03 +00:00
8e6b40a881
With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.
...
llvm-svn: 103047
2010-05-04 20:39:49 +00:00
a3a7b0099c
Do not pre-allocate for registers which form a REG_SEQUENCE.
...
llvm-svn: 103041
2010-05-04 20:38:12 +00:00
4c908f4181
Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
...
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
PHI elimination now does more than phi elimination. It is really a de-SSA pass.
llvm-svn: 103039
2010-05-04 20:26:52 +00:00
a2fda8b648
Defer adding critical edges to the "toSplit" list until after checking for
...
indirect branches in all the predecessors. This avoids unnecessarily
splitting edges in cases where load PRE is not possible anyway.
Thanks to Jakub Staszak for pointing this out.
llvm-svn: 103034
2010-05-04 20:03:21 +00:00
0185047b3f
"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
...
Patch by Kalle Raiskila!
llvm-svn: 103021
2010-05-04 17:58:46 +00:00
c3e0bafc6d
MC/X86: Chris pointed that 'as' isn't consistent in accepting the long form of
...
instructions which have no direct register usage.
Darwin 'as' accepts:
add $0, (%rax)
but rejects
mov $0, (%rax)
for example.
Given that, only accept suffix matches which match exactly one form. We still
need to emit nice diagnostics for failures...
llvm-svn: 103015
2010-05-04 17:31:02 +00:00
a5c0cc329e
Rename variables for consistency.
...
llvm-svn: 103013
2010-05-04 17:12:26 +00:00
9b816a1bb3
MC/X86: Add "support" for matching ATT style mnemonic prefixes.
...
- The idea is that when a match fails, we just try to match each of +'b', +'w',
+'l'. If exactly one matches, we assume this is a mnemonic prefix and accept
it. If all match, we assume it is width generic, and take the 'l' form.
- This would be a horrible hack, if it weren't so simple. Therefore it is an
elegant solution! Chris gets the credit for this particular elegant
solution. :)
- Next step to making this more robust is to have the X86 matcher generate the
mnemonic prefix information. Ideally we would also compute up-front exactly
which mnemonic to attempt to match, but this may require more custom code in
the matcher than is really worth it.
llvm-svn: 103012
2010-05-04 16:12:42 +00:00
8815f38312
Fix a problem exposed by my previous commit and noticed by a release-asserts
...
buildbot: the debugging and non-debugging versions of getFunction were not
functionally equivalent: the non-debugging version wrongly assumed that if a
metadata operand was not metadata, then it had a non-null containing function.
This is not true, since the operand might be a global value, constant etc.
llvm-svn: 103008
2010-05-04 14:25:42 +00:00
c2928c6ef5
Fix a variant of PR6112 found by thinking about it: when doing
...
RAUW of a global variable with a local variable in function F,
if function local metadata M in function G was using the global
then M would become function-local to both F and G, which is not
allowed. See the testcase for an example. Fixed by detecting
this situation and zapping the metadata operand when it occurs.
llvm-svn: 103007
2010-05-04 12:43:36 +00:00
4c0f838637
fix operand indexes when outputting InvokeInsts
...
llvm-svn: 103003
2010-05-04 09:23:54 +00:00
075e9b5d66
Set DW_AT_APPLE_omit_frame_ptr in endFunction() where MachineFunction is available all the time.
...
llvm-svn: 103001
2010-05-04 06:15:30 +00:00
70a3b12193
Use the SCEVAddRecExpr::getPostIncExpr utility function instead
...
of doing the same thing manually.
llvm-svn: 102997
2010-05-04 01:12:27 +00:00
5f18c547da
Fix a copy+pasto.
...
llvm-svn: 102996
2010-05-04 01:11:15 +00:00
801b8ea42a
Do not ignore debug loc attached with llvm.dbg.declare while collecting debug info used by a module.
...
llvm-svn: 102995
2010-05-04 01:05:02 +00:00
55869af998
Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489
...
llvm-svn: 102993
2010-05-04 00:58:39 +00:00
8f0037097f
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
...
changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
llvm-svn: 102991
2010-05-04 00:42:46 +00:00
ce0c1e11ce
llvm-mc: Fix case were we would skip a line in the .s file after an instruction
...
match failure.
Also, fixes a few memory leak FIXMEs.
llvm-svn: 102986
2010-05-04 00:33:07 +00:00
f869d9adf2
Teach scheduler about REG_SEQUENCE.
...
llvm-svn: 102984
2010-05-04 00:22:40 +00:00
0e79c864c3
Re-enable isel kill flags, now that the local allocator is ignoring them.
...
llvm-svn: 102981
2010-05-04 00:12:15 +00:00
30e637c9bc
rdar://7937137 - dbg values not being handled in thumb1 version of
...
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.
llvm-svn: 102980
2010-05-04 00:11:37 +00:00
b944b39887
Remove preexisting kill flags in RegAllocLocal, just like LiveVariables does.
...
This should make it possible to start producing kill flags in isel without
breaking stuff.
llvm-svn: 102976
2010-05-03 23:49:20 +00:00
626b5d8e0c
Factor out FastISel's code for materializing constants and other values
...
in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.
llvm-svn: 102975
2010-05-03 23:36:34 +00:00
81bfca7bde
Implement builtin_return_address(x) and builtin_frame_address(x)
...
on PPC for x!=0. 7624113.
llvm-svn: 102972
2010-05-03 22:59:34 +00:00
a2414ea190
Remove the API compatibility layer which converted add, sub, and mul
...
to fadd, fsub, and fmul, when used with a floating-point type. LLVM
has supported the new instructions since 2.6, so it's time to get
on board.
llvm-svn: 102971
2010-05-03 22:44:19 +00:00
f4e4e84115
Check that subregisters don't have independent values in RemoveCopyByCommutingDef().
...
This fixes PR6941.
llvm-svn: 102970
2010-05-03 22:40:32 +00:00
1e679cbfff
Reword a comment slightly.
...
llvm-svn: 102966
2010-05-03 22:18:49 +00:00
1d2ded75e2
Use getConstant instead of getIntegerSCEV. The two are basically the
...
same, now that getConstant has overloads consistent with ConstantInt::get.
llvm-svn: 102965
2010-05-03 22:09:21 +00:00
c936b56871
Print basic block numbers in live interval debug output. Since the rest of the
...
debug output is showing machine instructions, the IR-level basic block names
aren't very meaningful, and because multiple machine basic blocks may be
derived from one IR-level BB, they're also not unique.
llvm-svn: 102960
2010-05-03 21:38:11 +00:00
ab09a2cded
Fix function prototype mismatch in LLVMUnionType(). Fixes PR7019.
...
llvm-svn: 102959
2010-05-03 21:36:51 +00:00
6f2f8d0798
Changed llvm-mc to use the same suffixes with floating point compare
...
instructions as the Mac OS X darwin assembler. Some of which like 'fcoml'
assembled to different opcodes. While some of the suffixes were just different.
llvm-svn: 102958
2010-05-03 21:31:40 +00:00
e3a1726034
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
...
mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
llvm-svn: 102952
2010-05-03 21:03:31 +00:00
1a51d4cec9
Fixed the encoding of the x86 push instructions. Using a 32-bit immediate value
...
caused the a pushl instruction to be incorrectly encoding using only two bytes
of immediate, causing the following 2 instruction bytes to be part of the 32-bit
immediate value. Also fixed the one byte form of push to be used when the
immediate would fit in a signed extended byte. Lastly changed the names to not
include the 32 of PUSH32 since they actually push the size of the stack pointer.
llvm-svn: 102951
2010-05-03 20:45:05 +00:00
267700c5aa
Silence warnings about -1 being converted to an unsigned value.
...
Also, pass true for isSigned even when creating constants for unsigned
comparisons, because the point is to create an all-ones constant,
rather than UINT64_MAX, even for integers wider than 64 bits.
llvm-svn: 102946
2010-05-03 20:23:47 +00:00
937a5b75f9
Add an option, defaulting to off, to disable the sse domain crossing opts.
...
llvm-svn: 102941
2010-05-03 19:54:02 +00:00
9f5200a122
Check for side effects before splitting loop.
...
Patch by Jakub Staszak!
llvm-svn: 102928
2010-05-03 18:06:58 +00:00
b5025c72eb
Use isTrueWhenEqual and isFalseWhenEqual instead of assuming that
...
SimplifyICmpOperands will simplify such cases to EQ or NE. This makes
the correcntess of the code independent on SimplifyICmpOperands doing
certain simplifications.
llvm-svn: 102927
2010-05-03 18:00:24 +00:00
d18dc2c876
In ScalarEvolution::print, don't bother printing out the SCEVs for
...
comparison instructions, since they aren't interesting, despite having
integer result types.
llvm-svn: 102925
2010-05-03 17:03:23 +00:00
df564cacaf
In SimplifyICmpOperands, avoid needlessly swapping the operands in the
...
case where both are addrecs in unrelated loops.
llvm-svn: 102924
2010-05-03 17:00:11 +00:00
81585c18e1
Factor out the new <= and >= analysis code into SimplifyICmpOperands.
...
llvm-svn: 102922
2010-05-03 16:35:17 +00:00
2ad68de4aa
Fix a bug which prevented tail merging of return instructions in
...
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.
The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.
Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.
And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.
llvm-svn: 102907
2010-05-03 14:35:47 +00:00
73c8145505
Add a README entry.
...
llvm-svn: 102906
2010-05-03 14:31:00 +00:00
211427bda9
Remove the -enable-sjlj-eh option, which doesn't do anything.
...
Remove the -enable-eh option which is only used by the JIT,
and replace it with -jit-enable-eh.
llvm-svn: 102865
2010-05-02 15:36:26 +00:00
2094488d81
fix some inconsistent line endings, patch by Jakub Staszak!
...
llvm-svn: 102852
2010-05-01 17:36:49 +00:00
b49a622fe9
revert r102831. We already delete dead readonly calls in
...
other places, killing a valid transformation is not the right
answer.
llvm-svn: 102850
2010-05-01 17:19:38 +00:00
1ebb395cee
Don't count debug info as instructions. This was
...
preventing the emission of the NOP on Darwin for a
function with no actual code. From timberwolfmc
with TEST=optllcdbg.
llvm-svn: 102843
2010-05-01 16:41:11 +00:00
f4b87f191b
Added a variant of InlineCostAnalyzer::getInlineCost() that takes the called function as an explicit argument, for use when inlining function pointers.
...
llvm-svn: 102841
2010-05-01 15:47:41 +00:00
737718d4f4
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
...
when needed. This fixes PR7001
llvm-svn: 102838
2010-05-01 12:52:34 +00:00
319d71f44f
Do folding for indirect branches, where possible
...
llvm-svn: 102836
2010-05-01 12:28:21 +00:00
ebbdfef2fc
Implement indirect branches on MSP430
...
llvm-svn: 102835
2010-05-01 12:04:32 +00:00
Jakob Stoklund Olesen