d9225cee20
Don't special-case stdout in llvm::WriteBitcodeToFile; just consider
...
it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.
llvm-svn: 104878
2010-05-27 20:06:51 +00:00
f162eace49
Teach instCombine to remove malloc+free if malloc's only uses are comparisons
...
to null. Patch by Matti Niemenmaa.
llvm-svn: 104871
2010-05-27 19:09:06 +00:00
b68dfb45f5
hook ISD::STACKADDR to an intrinsic
...
llvm-svn: 104869
2010-05-27 18:52:11 +00:00
dc53f1cb5c
FastISel doesn't yet handle callee-pop functions.
...
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
llvm-svn: 104866
2010-05-27 18:43:40 +00:00
5cde219fb1
add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH
...
to update the jmpbuf in the presence of VLAs.
llvm-svn: 104862
2010-05-27 18:23:48 +00:00
54b07ad2cd
Merge basic binops SSE 1 & 2 instruction classes. This is a step towards refactoring
...
common code between SSE versions.
llvm-svn: 104860
2010-05-27 18:17:40 +00:00
c36b1f35f0
Add basic error checking to MemoryBuffer::getSTDIN.
...
llvm-svn: 104855
2010-05-27 17:31:51 +00:00
ece4bf5148
Use the return value of getMagicNumber instead of using a
...
separate canRead() call.
llvm-svn: 104853
2010-05-27 17:18:38 +00:00
78d1e84521
Don't bother clearing the Magic string when the magic number
...
can't be read, since it isn't cleared on other error paths.
llvm-svn: 104852
2010-05-27 17:14:10 +00:00
16f4bd8140
Don't bother checking canRead() before calling getMagicNumber();
...
getMagicNumber() does its own error checking.
llvm-svn: 104851
2010-05-27 17:12:23 +00:00
5e6b71ce34
inlined function's arguments need a label to mark the start point because they are not directly attached to current function.
...
llvm-svn: 104848
2010-05-27 16:47:30 +00:00
8e99e50d08
Support for nested functions/classes in debug output. Radar 7424645.
...
llvm-svn: 104841
2010-05-27 16:16:54 +00:00
eaddfac539
Rearrange conditionals so we don't get caught with the correct type as wrong.
...
llvm-svn: 104793
2010-05-27 00:52:31 +00:00
6b9a9fe207
Simplify. Eliminate unneeded debug_loc entry.
...
llvm-svn: 104785
2010-05-26 23:55:23 +00:00
d67defdfe2
Avoid counting InlineAsm as a call - it prevents loop unrolling.
...
PR7026
Patch by Pekka Jääskeläinen!
llvm-svn: 104780
2010-05-26 22:40:28 +00:00
084bcb1322
Fix Lint printing warnings multiple times. Remove the ErrorStr
...
option from lintModule, which was an artifact from being
based on Verifier code.
llvm-svn: 104765
2010-05-26 22:28:53 +00:00
c0b69020cd
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
...
to be matched.
llvm-svn: 104757
2010-05-26 22:21:28 +00:00
a20a5cd24f
Reinstate checking of stackrestore, with checking for both Read
...
and Write, and add a comment explaining this.
llvm-svn: 104756
2010-05-26 22:21:25 +00:00
4f6da9e3a8
Give SubRegIndex names to all ARM subregisters. This will be required by
...
TableGen shortly.
llvm-svn: 104754
2010-05-26 22:15:03 +00:00
996bc42a26
Stackrestore is not a load.
...
llvm-svn: 104752
2010-05-26 22:00:10 +00:00
ddee3cb163
Add FIXME comment to remove this.
...
llvm-svn: 104749
2010-05-26 21:53:50 +00:00
c96c6db59d
Remove a TODO which isn't practical.
...
llvm-svn: 104748
2010-05-26 21:50:41 +00:00
b33dfbcba4
MC: Add TargetMachine support for setting the value of MCRelaxAll with
...
-filetype=obj.
llvm-svn: 104747
2010-05-26 21:48:55 +00:00
d1d7ed63ff
Add StringRef::compare_numeric and use it to sort TableGen register records.
...
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
llvm-svn: 104745
2010-05-26 21:47:28 +00:00
1249adf160
Implement checking of the tail keyword.
...
llvm-svn: 104744
2010-05-26 21:46:36 +00:00
acc32a5c19
There is no need to force an line number entry (using previous location) for a temp label at unknown location.
...
llvm-svn: 104740
2010-05-26 21:23:46 +00:00
27311269cb
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
...
usual suspects that could "return twice".
llvm-svn: 104737
2010-05-26 20:39:00 +00:00
b889fc987e
MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments.
...
llvm-svn: 104736
2010-05-26 20:37:03 +00:00
9d40ef162b
MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment.
...
llvm-svn: 104735
2010-05-26 20:37:00 +00:00
c98892fdaa
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
...
ISD::. No functional change.
llvm-svn: 104734
2010-05-26 20:22:18 +00:00
1b08572a66
Update debug info when live-in reg is copied into a vreg.
...
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
70e34983e8
Fix the x86 move to/from segment register instructions.
...
llvm-svn: 104731
2010-05-26 20:10:45 +00:00
0c3bfd3fb0
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
...
more than just the stack slot coloring algorithm.
llvm-svn: 104722
2010-05-26 19:46:12 +00:00
002d54ddc9
Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().
...
llvm-svn: 104720
2010-05-26 19:37:24 +00:00
52c2738324
Eliminate the use of PriorityQueue and just use a std::vector,
...
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
llvm-svn: 104718
2010-05-26 18:52:00 +00:00
1e5d0b0456
Delete an unused function.
...
llvm-svn: 104716
2010-05-26 18:34:12 +00:00
7c8bd0fc98
MC: Change RelaxInstruction to only take the input and output instructions.
...
llvm-svn: 104713
2010-05-26 18:15:06 +00:00
338674a323
Fix a typo in a comment that Gabor noticed.
...
llvm-svn: 104711
2010-05-26 18:03:53 +00:00
388ff9b1a2
MC: Eliminate an unnecessary copy.
...
llvm-svn: 104709
2010-05-26 17:50:16 +00:00
a19838e107
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
...
before encoding.
llvm-svn: 104707
2010-05-26 17:45:29 +00:00
95fcc96752
Remove dead code.
...
llvm-svn: 104706
2010-05-26 17:42:50 +00:00
5a5e0bc3b5
Do not construct location list backword!
...
llvm-svn: 104705
2010-05-26 17:29:32 +00:00
7de379467e
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104704
2010-05-26 17:27:12 +00:00
b34440a6a8
MC: Eliminate MCAsmFixup, replace with MCFixup.
...
llvm-svn: 104699
2010-05-26 15:18:56 +00:00
353a91ff76
MC: Use accessors for access to MCAsmFixup.
...
llvm-svn: 104697
2010-05-26 15:18:31 +00:00
3627af5da4
MC: Change MCInst::dump_pretty to not include a trailing newline.
...
llvm-svn: 104696
2010-05-26 15:18:13 +00:00
6877119ef3
Kill unneeded SExt.
...
llvm-svn: 104692
2010-05-26 09:45:04 +00:00
730a977e02
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
...
llvm-svn: 104691
2010-05-26 08:10:02 +00:00
870e5759e7
MC: Eliminate MCFragment vtable, which was unnecessary.
...
llvm-svn: 104689
2010-05-26 06:50:57 +00:00
c4376b9b1b
Coding style change (Adding 1 missing space.)
...
llvm-svn: 104670
2010-05-26 04:46:50 +00:00
0568ca0ddc
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
llvm-svn: 104667
2010-05-26 03:21:39 +00:00
e805ea9e39
Temporarily revert r104655 as it's breaking the bots.
...
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
a6897ecbb5
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
...
llvm-svn: 104661
2010-05-26 01:22:21 +00:00
50eec620f4
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
...
This reverts commit 104654.
llvm-svn: 104660
2010-05-26 01:21:14 +00:00
7c00576a62
Change push_all to a non-virtual function and implement it in the
...
base class, since all the implementations are the same.
llvm-svn: 104659
2010-05-26 01:10:55 +00:00
3701b3928e
Trim #include.
...
llvm-svn: 104657
2010-05-26 00:55:59 +00:00
c5222d6c38
Dale and Evan suggested putting the "check for setjmp" much earlier in the
...
machine code generation. That's a good idea, so I made it so.
llvm-svn: 104655
2010-05-26 00:32:40 +00:00
0b0274524c
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
llvm-svn: 104654
2010-05-26 00:28:19 +00:00
b6e0bc9457
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
llvm-svn: 104653
2010-05-26 00:25:05 +00:00
e22abfa823
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
llvm-svn: 104652
2010-05-26 00:02:28 +00:00
e7b64dcc1e
Start adding mach-o tls reloc support.
...
llvm-svn: 104651
2010-05-26 00:02:12 +00:00
66c939a2ca
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
...
llvm-svn: 104650
2010-05-25 23:43:18 +00:00
9fc11706e3
First cut at supporting .debug_loc section.
...
This is used to track variable information.
llvm-svn: 104649
2010-05-25 23:40:22 +00:00
9439084cea
Properly promote operands when optimizing a single-character memcmp.
...
llvm-svn: 104648
2010-05-25 22:53:43 +00:00
388f638511
Constify function.
...
llvm-svn: 104646
2010-05-25 22:02:22 +00:00
ce3269b815
Do one map lookup instead of two.
...
llvm-svn: 104645
2010-05-25 21:59:42 +00:00
a4abd035ea
Fix a missing newline in debug output.
...
llvm-svn: 104644
2010-05-25 21:50:35 +00:00
f3925438e5
Move the verbose asm output up a bit so it can be used in the special cases
...
as well.
llvm-svn: 104642
2010-05-25 21:49:43 +00:00
b04ef0cfbc
Okay, bear with me here...
...
If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
llvm-svn: 104640
2010-05-25 21:44:26 +00:00
19a4b843cc
Add support for initialized global data for darwin tls. Update comments
...
and testcases accordingly.
llvm-svn: 104635
2010-05-25 21:28:50 +00:00
492d4f409a
Changed the encoding of X86 floating point stack operations where both operands
...
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
llvm-svn: 104634
2010-05-25 20:52:34 +00:00
3311eb50d7
Separate unrelated cases that once shared a numeric value
...
llvm-svn: 104629
2010-05-25 19:49:40 +00:00
1ad0d5e25b
Print symbolic SubRegIndex names on machine operands.
...
llvm-svn: 104628
2010-05-25 19:49:38 +00:00
673e7e0f37
Remove NumberHack entirely.
...
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
llvm-svn: 104627
2010-05-25 19:49:33 +00:00
0e767d7364
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
...
llvm-svn: 104626
2010-05-25 19:49:32 +00:00
60fe2cdc4f
Fix another variant of PR 7191. Also add a testcase
...
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
llvm-svn: 104624
2010-05-25 18:47:23 +00:00
4a5b2c597b
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
...
llvm-svn: 104622
2010-05-25 18:40:53 +00:00
c798965e63
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
llvm-svn: 104621
2010-05-25 18:16:58 +00:00
ff384ad981
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
...
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
llvm-svn: 104619
2010-05-25 17:50:03 +00:00
f6562d35ac
Make sure aeskeygenassist uses an unsigned immediate field.
...
Fixes rdar://8017638
llvm-svn: 104617
2010-05-25 17:33:22 +00:00
3b59e0601e
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
...
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
llvm-svn: 104615
2010-05-25 17:21:04 +00:00
36caaf1c59
Use enums instead of literals for SystemZ subregisters
...
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
396c8802b2
Use enums instead of literals for X86 subregisters.
...
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
llvm-svn: 104611
2010-05-25 17:04:16 +00:00
a6714e8a43
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
...
llvm-svn: 104588
2010-05-25 10:23:52 +00:00
2da5aa1b60
Add support to MOVimm32 using movt/movw for ARM JIT
...
llvm-svn: 104587
2010-05-25 08:42:45 +00:00
4f48499d2c
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
llvm-svn: 104583
2010-05-25 04:51:47 +00:00
debbbe3fd9
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
llvm-svn: 104582
2010-05-25 04:43:08 +00:00
26fdebcae9
Clean up indentation.
...
llvm-svn: 104580
2010-05-25 03:36:52 +00:00
adff18518a
Disable invalid coalescer assertion.
...
llvm-svn: 104574
2010-05-25 00:15:18 +00:00
70affbd988
Use enums instead of literals in the ARM backend.
...
llvm-svn: 104573
2010-05-25 00:15:15 +00:00
0b7488e8d5
Print out the name of the function during SSC.
...
llvm-svn: 104572
2010-05-24 23:16:04 +00:00
fdb25de17e
Switch SubRegSet to using symbolic SubRegIndices
...
llvm-svn: 104571
2010-05-24 23:03:18 +00:00
91b2b8540c
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
...
version of t2MVN already allowed that, but not the register versions.
llvm-svn: 104570
2010-05-24 22:41:19 +00:00
1181a19318
Lose the dummies
...
llvm-svn: 104564
2010-05-24 21:47:01 +00:00
edab242488
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
...
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
llvm-svn: 104563
2010-05-24 21:46:58 +00:00
1b79babdec
Avoid adding duplicate function live-in's.
...
llvm-svn: 104560
2010-05-24 21:33:37 +00:00
79b6a0f140
Fix an mmx movd encoding.
...
llvm-svn: 104552
2010-05-24 20:51:08 +00:00
dc71cc794b
MC/X86: Add aliases for CMOVcc variants.
...
llvm-svn: 104549
2010-05-24 20:32:23 +00:00
722bff2c7d
Clean up some extra whitespace.
...
llvm-svn: 104544
2010-05-24 20:08:34 +00:00
3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
51b37e0bd8
Do not emit line number entries for unknown debug values.
...
This fixes recent regression in store.exp from gdb testsuite.
llvm-svn: 104524
2010-05-24 18:26:49 +00:00
755d45be43
LR is in GPR, not tGPR even in Thumb1 mode.
...
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
ff2d118733
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
...
never used.
llvm-svn: 104517
2010-05-24 17:55:38 +00:00
8a57aeca2a
Use SubRegIndex in SystemZ.
...
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
llvm-svn: 104515
2010-05-24 17:43:01 +00:00
5d56769fb6
SubRegIndex'ize Mips
...
llvm-svn: 104514
2010-05-24 17:42:58 +00:00
fd6f16fab9
SubRegIndex'ize MSP430
...
llvm-svn: 104513
2010-05-24 17:42:55 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
9340ea59e1
Rename X86 subregister indices to something shorter.
...
Use the tablegen-produced enums.
llvm-svn: 104493
2010-05-24 14:48:17 +00:00
1c69646e99
Add the SubRegIndex TableGen class.
...
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
llvm-svn: 104492
2010-05-24 14:48:12 +00:00
c5327226e4
Encode the Caml frametable by following what the comment says: the number of descriptors
...
is first emitted, and StackOffsets are emitted in 16 bits.
llvm-svn: 104488
2010-05-24 12:24:11 +00:00
6738a2e39e
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104467
2010-05-23 18:36:38 +00:00
8271d1bb4a
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
...
llvm-svn: 104466
2010-05-23 18:36:34 +00:00
3ff1a06de6
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
...
llvm-svn: 104463
2010-05-23 17:44:06 +00:00
49f40e8c32
VDUP doesn't support vectors with 64-bit elements.
...
llvm-svn: 104455
2010-05-23 05:42:31 +00:00
b52fcd6304
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
...
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
llvm-svn: 104453
2010-05-22 21:02:33 +00:00
346782c12c
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
...
llvm-svn: 104452
2010-05-22 21:02:29 +00:00
d459e29a0a
MC/X86: Add alias for setz, setnz, jz, jnz.
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llvm-svn: 104435
2010-05-22 06:37:33 +00:00
168ced94d8
Implement @llvm.returnaddress. rdar://8015977.
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llvm-svn: 104421
2010-05-22 01:47:14 +00:00
bd9485db63
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
llvm-svn: 104419
2010-05-22 01:06:18 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
6fdea1bda8
Add full bss data support for darwin tls variables.
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llvm-svn: 104414
2010-05-22 00:10:22 +00:00
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
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llvm-svn: 104412
2010-05-22 00:04:14 +00:00
61438fe064
Clean up extra whitespace.
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llvm-svn: 104410
2010-05-21 23:53:55 +00:00
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
4dc833c607
add a note
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llvm-svn: 104404
2010-05-21 23:16:21 +00:00
09d47031b1
Expand on comment.
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llvm-svn: 104396
2010-05-21 23:03:53 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
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llvm-svn: 104394
2010-05-21 23:01:38 +00:00
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
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llvm-svn: 104385
2010-05-21 21:22:19 +00:00
3dca28d0e2
Fix section attribute name.
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llvm-svn: 104381
2010-05-21 21:08:52 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
7d7f604321
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
llvm-svn: 104372
2010-05-21 20:02:01 +00:00
1782aae355
Simplify
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llvm-svn: 104338
2010-05-21 18:49:09 +00:00
2b78565842
Previous commit message should refer to 104308.
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llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
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llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
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llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
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llvm-svn: 104326
2010-05-21 17:49:07 +00:00
a81e1cab04
constify accessor.
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llvm-svn: 104325
2010-05-21 17:47:50 +00:00
b4e1687270
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
llvm-svn: 104323
2010-05-21 17:36:32 +00:00
8e8e090301
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
llvm-svn: 104322
2010-05-21 16:42:30 +00:00
a648c6a757
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
llvm-svn: 104321
2010-05-21 16:36:13 +00:00
1f3801062d
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
llvm-svn: 104320
2010-05-21 16:32:16 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
ec9d6faef0
Add support for parsing the ELF .type assembler directive.
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llvm-svn: 104316
2010-05-21 11:36:59 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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llvm-svn: 104307
2010-05-21 00:43:17 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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llvm-svn: 104306
2010-05-21 00:42:32 +00:00
fbd6c45e06
Simplify.
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llvm-svn: 104302
2010-05-21 00:10:20 +00:00
c120ffe3f6
Fix __crashreport_info__ declaration.
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llvm-svn: 104300
2010-05-20 23:50:19 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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llvm-svn: 104293
2010-05-20 23:26:43 +00:00
9b48b856ea
DominatorTree.getNode can return null for unreachable blocks.
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llvm-svn: 104290
2010-05-20 22:46:54 +00:00
86110fa2bb
Minor code cleanups.
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llvm-svn: 104287
2010-05-20 22:25:20 +00:00
3a48292204
Print a space after the colon.
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llvm-svn: 104279
2010-05-20 21:11:37 +00:00
6295f2ebb8
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
a4ca28a3ae
Add comments.
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llvm-svn: 104276
2010-05-20 20:52:00 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
0adee9b362
Rename variable. add comment.
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llvm-svn: 104274
2010-05-20 20:35:24 +00:00
927bcaadda
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
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llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
4c4043cf34
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
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Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
llvm-svn: 104269
2010-05-20 20:05:31 +00:00
8ec018cedf
Add some comments.
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llvm-svn: 104268
2010-05-20 20:00:41 +00:00
8ce95cc3c5
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
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llvm-svn: 104267
2010-05-20 20:00:25 +00:00
490c8ab76d
Refactor.
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llvm-svn: 104265
2010-05-20 19:57:06 +00:00
141791c6d1
Grammar fix. This is a test commit.
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llvm-svn: 104264
2010-05-20 19:45:09 +00:00
ab5fb7f559
Minor code cleanups.
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llvm-svn: 104263
2010-05-20 19:44:23 +00:00
ee2fea3cd7
When canonicalizing icmp operand order to put the loop invariant
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operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
llvm-svn: 104262
2010-05-20 19:26:52 +00:00
3e69aa0399
llvmc: Make segfault detection work on Win32.
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llvm-svn: 104261
2010-05-20 19:23:47 +00:00
fdf9874ba7
Set Changed to true when canonicalizing ICmp operand order; even though
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it isn't a very interesting change, it's a change nonetheless.
llvm-svn: 104260
2010-05-20 19:16:03 +00:00
5954994bba
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
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This fixes the remaining issue with pr7167.
llvm-svn: 104257
2010-05-20 18:39:53 +00:00
63d4f68df4
Remove dbg_value workaround and associated command line option
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llvm-svn: 104254
2010-05-20 18:34:01 +00:00
098a47931c
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
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have a pattern and it had an invalid encoding.
llvm-svn: 104244
2010-05-20 18:05:01 +00:00
d7d6638e3e
The PPC MFCR instruction implicitly uses all 8 of the CR
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registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
llvm-svn: 104238
2010-05-20 17:48:26 +00:00
e2ff7f3a7d
Strip llvm.dbg.lv also.
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llvm-svn: 104236
2010-05-20 16:49:22 +00:00
981563d0ba
Rename a variable to avoid shadowing.
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llvm-svn: 104234
2010-05-20 16:41:11 +00:00
e1c53f29d3
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
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llvm-svn: 104233
2010-05-20 16:36:41 +00:00
6b733fc189
Minor code simplification.
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llvm-svn: 104232
2010-05-20 16:23:28 +00:00
29790edb93
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
llvm-svn: 104231
2010-05-20 16:16:00 +00:00
5238275478
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
llvm-svn: 104228
2010-05-20 15:42:55 +00:00
80a9608442
Move the code for deleting BaseRegs and LSRUses into helper functions,
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and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
llvm-svn: 104225
2010-05-20 15:17:54 +00:00
7c3e230cd1
Reduce string trashing.
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llvm-svn: 104223
2010-05-20 14:14:22 +00:00
bdd062dae0
Add a hybrid bottom up scheduler that reduce register usage while avoiding
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pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
llvm-svn: 104216
2010-05-20 06:13:19 +00:00
c53cc4f8bf
Fix typo in comment.
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llvm-svn: 104209
2010-05-20 03:30:09 +00:00
1e19eab963
Define the x86 pause instruction.
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llvm-svn: 104204
2010-05-20 01:35:50 +00:00
a3b7570a3a
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
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doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
llvm-svn: 104203
2010-05-20 01:23:41 +00:00
27e7ffc7d4
Partial code for emitting thread local bss data.
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llvm-svn: 104197
2010-05-20 00:49:07 +00:00
20fab456da
Teach LSR how to cope better with unrolled loops on targets where
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the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
llvm-svn: 104186
2010-05-19 23:43:12 +00:00
42603958fb
Optimize away insertelement of an undef value. This shows up in
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test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar 7998853.
llvm-svn: 104185
2010-05-19 23:42:58 +00:00
7cbfa4462f
fix rdar://7986634 - match instruction opcodes case insensitively.
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llvm-svn: 104183
2010-05-19 23:34:33 +00:00
f98511473e
Enable preserving debug information through post-RA scheduling
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llvm-svn: 104175
2010-05-19 22:57:47 +00:00
604560c5fe
Fix the post-RA instruction scheduler to handle instructions referenced by
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more than one dbg_value instruction. rdar://7759363
llvm-svn: 104174
2010-05-19 22:57:06 +00:00
70e506e18a
Code clean up.
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llvm-svn: 104173
2010-05-19 22:42:23 +00:00
a08130864e
Revert r104165.
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llvm-svn: 104172
2010-05-19 21:58:28 +00:00
e0eddb21f5
Add support for partial redefs to the fast register allocator.
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A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
llvm-svn: 104167
2010-05-19 21:36:05 +00:00
0fe341e2e2
There is no need to maintain InsnsBeginScopeSet separately.
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llvm-svn: 104165
2010-05-19 21:26:53 +00:00
Dan Gohman