Commit Graph

3 Commits

Author SHA1 Message Date
Sanjay Patel c882208367 [DAGCombiner] improve throughput of shift+logic+shift
The motivating case for this is a long way from here:
https://bugs.llvm.org/show_bug.cgi?id=43146
...but I think this is where we have to start.

We need to canonicalize/optimize sequences of shift and logic to ease
pattern matching for things like bswap and improve perf in general.
But without the artificial limit of '!LegalTypes' (early combining),
there are a lot of test diffs, and not all are good.

In the minimal tests added for this proposal, x86 should have better
throughput in all cases. AArch64 is neutral for scalar tests because
it can fold shifts into bitwise logic ops.

There are 3 shift opcodes and 3 logic opcodes for a total of 9 possible patterns:
https://rise4fun.com/Alive/VlI
https://rise4fun.com/Alive/n1m
https://rise4fun.com/Alive/1Vn

Differential Revision: https://reviews.llvm.org/D67021

llvm-svn: 370617
2019-09-01 18:38:15 +00:00
Sanjay Patel 11704d0f51 [AArch64][x86] increase value type coverage in tests; NFC
This goes with D67021.

llvm-svn: 370590
2019-08-31 15:49:16 +00:00
Sanjay Patel 82847b50e9 [AArch64] add tests for shift-logic-shift; NFC
llvm-svn: 370528
2019-08-30 20:48:43 +00:00