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Author SHA1 Message Date
Petar Jovanovic daf5169398 [mips] Add support for Global INValidate ASE 
This includes

  Instructions: ginvi, ginvt,

  Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv

  Attribute: ginv

  .MIPS.abiflags: GINV (0x20000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D46268

llvm-svn: 332624
 2018-05-17 16:30:32 +00:00
Simon Dardis 65b0492f0d [mips] Correct the predicates of sign extension instructions 
And eliminatw the duplication of those instructions for microMIPS32r6.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46117

llvm-svn: 331526
 2018-05-04 15:00:54 +00:00
Simon Dardis 694fde215e Revert "[mips] Correct the predicates of sign extension instructions" 
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.

llvm-svn: 331348
 2018-05-02 12:35:29 +00:00
Simon Dardis 7a36495bf7 [mips] Correct the predicates of sign extension instructions 
And eliminate the duplication of those instructions for microMIPS32r6.

llvm-svn: 331346
 2018-05-02 12:25:33 +00:00
Simon Dardis 4529aac2de [mips] Begin reworking instruction predicates for ISAs/encodings (1/N) 
The MIPS backend has inconsistent usage of instruction predicates
for assembly and code generation. The issue arises from supporting three
encodings, two (MIPS and microMIPS) of which have a near 1:1 instruction
mapping across ISA revisions and a third encoding with a more restricted
set of instructions (MIPS16e).

To enforce consistent usage, each of the ISA_* adjectives has (or will
have) the relevant encoding attached to it along the relevant ISA revision
where the instruction is defined.

Each instruction, pattern or alias will then have the correct ISA adjective
attached to it, and the base instruction description classes will have any
predicates relating to ISA encoding or revision removed.

Pseudo instructions will also be guarded for the encoding or ABI that they are
supported in.

Finally, the hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods
of MipsSubtarget will be changed such that only one can be true at any one time.

The result of this is that code generation and assembly will produce the
correct encoding up front, while code generated from pseudo instructions
and other inserted sequences of instructions will be able to rely on the mapping
tables to produce the correct encoding. This should fix numerous bugs where
the result 'happens' to be correct but has edge cases where microMIPS and MIPS
have subtle differences (e.g. microMIPSR6 using 'j', 'jal' instructions.)

This patch starts the process by changing most of the ISA adjectives to make
use of the EncodingPredicate member of PredicateControl. Follow on patches
will annotate instructions with their correct ISA adjective and eliminate
the usage of "let Predicates = [..]", "let AdditionalPredicates = [..]" and
"isCodeGenOnly = 1" in the cases where it was used to control instruction
availability.

Contributions from Nitesh Jain.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D41434

llvm-svn: 326322
 2018-02-28 13:02:44 +00:00
Aleksandar Beserminji a734d409c6 [mips] Remove duplicated R6 EVA instructions 
This patch removes duplicated EVA instructions in R6.

Differential Revision: https://reviews.llvm.org/D41769

llvm-svn: 322007
 2018-01-08 16:50:33 +00:00
Aleksandar Beserminji d6dada17ff [mips] Removal of microMIPS64R6 
All files and parts of files related to microMIPS4R6 are removed.
When target is microMIPS4R6, errors are printed.

This is LLVM part of patch.

Differential Revision: https://reviews.llvm.org/D35625

llvm-svn: 320350
 2017-12-11 11:21:40 +00:00
Simon Dardis 169df4e24b [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version 
Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encoded for
microMIPS32r6, so this patch provides the correct encoding.

Secondly, correct the encoding of the 'rs' and 'rt' operands which have
an instruction specific encoding for the registers those operands accept.

Finally, correct the decoding of the 'dst_regs' operand which was extracting
the relevant field from the instruction, but was actually extracting the
field from the alreadly extracted field.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39495

llvm-svn: 317475
 2017-11-06 12:59:53 +00:00
Zlatko Buljan cba9f80ba8 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
 2016-07-11 07:41:56 +00:00
Hrvoje Varga c962c4936e [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions 
Differential Revision: http://reviews.llvm.org/D11798

llvm-svn: 272259
 2016-06-09 12:57:23 +00:00
Zlatko Buljan e663e34e79 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions 
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
 2016-05-19 07:31:28 +00:00
Zoran Jovanovic 84e4d59e47 [mips][microMIPS] Implement BEQZC and BNEZC instructions 
Differential Revision: http://reviews.llvm.org/D15417

llvm-svn: 269755
 2016-05-17 11:10:15 +00:00
Hrvoje Varga cf6a78192b Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions" 
This reverts commit r269176 as it caused test-suite failure.

llvm-svn: 269287
 2016-05-12 12:46:06 +00:00
Hrvoje Varga 52c9bed858 [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions 
Differential Revision: http://reviews.llvm.org/D19713

llvm-svn: 269176
 2016-05-11 12:12:24 +00:00
Zlatko Buljan ba553a6e0a [mips][microMIPS] Implement LWP and SWP instructions 
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
 2016-05-09 08:07:28 +00:00
Zoran Jovanovic f6344ff295 [mips][microMIPS] Revert commit r266861. 
Commit r266861 was the reason for failing tests in LLVM test suite.

llvm-svn: 267166
 2016-04-22 16:53:15 +00:00
Zlatko Buljan ae720dbbb6 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions 
Differential Revision: http://reviews.llvm.org/D18687

llvm-svn: 267114
 2016-04-22 06:44:34 +00:00
Zoran Jovanovic fdbd0a37c1 [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions 
Differential Revision: http://reviews.llvm.org/D14206

llvm-svn: 266873
 2016-04-20 14:07:46 +00:00
Hrvoje Varga 117625aaf3 [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions 
Differential Revision: http://reviews.llvm.org/D18640

llvm-svn: 266861
 2016-04-20 06:34:48 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Zoran Jovanovic a68b67d1ed [mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated. 
Author: milena.vujosevic.janicic
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D17373

llvm-svn: 262725
 2016-03-04 17:34:31 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions 
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
 2015-12-21 13:08:58 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions 
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
 2015-10-28 11:04:29 +00:00
Hrvoje Varga 3c88fbd367 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions 
Differential Revision: http://reviews.llvm.org/D11633

llvm-svn: 250511
 2015-10-16 12:24:58 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Zoran Jovanovic 5a8dffc618 [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions 
Differential Revision: http://reviews.llvm.org/D11219

llvm-svn: 249317
 2015-10-05 14:00:09 +00:00
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions 
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
 2015-10-01 12:49:27 +00:00
Zoran Jovanovic 7beb737b46 [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 
Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
 2015-09-15 10:05:10 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
 2015-09-09 13:55:45 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions 
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
 2015-09-08 15:02:50 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions 
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
 2015-09-08 10:18:38 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
 2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions 
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
 2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions 
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
 2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
 2015-09-05 09:25:30 +00:00
Zoran Jovanovic a6593ff613 [mips][microMIPS] Implement SW and SWE instructions 
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
 2015-08-18 12:53:08 +00:00
Zoran Jovanovic 2a47d08afd [mips][microMIPS] Implement SLL and NOP instructions 
http://reviews.llvm.org/D10474

llvm-svn: 241150
 2015-07-01 09:54:51 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions 
http://reviews.llvm.org/D10090

llvm-svn: 240531
 2015-06-24 10:32:16 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions 
http://reviews.llvm.org/D10091

llvm-svn: 239522
 2015-06-11 10:22:46 +00:00
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions 
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
 2015-05-27 15:39:47 +00:00
Jozef Kolek 888830adfe [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions 
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031

llvm-svn: 238325
 2015-05-27 14:19:22 +00:00
Jozef Kolek cc0c0fc926 [mips][microMIPSr6] Implement LSA instruction 
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919

llvm-svn: 237634
 2015-05-18 23:12:10 +00:00
Jozef Kolek cbb227b48d [mips][microMIPSr6] Implement ALIGN and AUI instructions 
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782

llvm-svn: 237563
 2015-05-18 11:44:30 +00:00
Jozef Kolek 6fec325d10 [mips][microMIPSr6] Implement CLO and CLZ instructions 
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553

llvm-svn: 237257
 2015-05-13 14:18:11 +00:00
Jozef Kolek 38bb81db85 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions 
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497

llvm-svn: 237158
 2015-05-12 17:39:32 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions 
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
 2015-05-08 14:25:11 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions 
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
 2015-05-08 13:52:04 +00:00