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Author SHA1 Message Date
Amjad Aboud 4f97751798 [X86] Generate VZEROUPPER for Skylake-avx512. 
VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be.

Differential Revision: https://reviews.llvm.org/D29874

llvm-svn: 296859
 2017-03-03 09:03:24 +00:00
Craig Topper 63e2cd6caa [AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial. 
Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions.

This also picks up cases where the masked move was created due to a masked load intrinsic.

Differential Revision: https://reviews.llvm.org/D28454

llvm-svn: 292005
 2017-01-14 07:50:52 +00:00
Elena Demikhovsky 59f6f8c05d [X86 Codegen Test] Divided masked_memop into several files. NFC. 
The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files.

llvm-svn: 281892
 2016-09-19 08:58:43 +00:00