Commit Graph

406104 Commits

Author SHA1 Message Date
Hsiangkai Wang 9a88566537 [RISCV] Fix a bug in RISCVFrameLowering.
When we have out-going arguments passing through stack and we do not
reserve the stack space in the prologue. Use BP to access stack objects
after adjusting the stack pointer before function calls.

callseq_start  ->  sp = sp - reserved_space
//
// Use FP to access fixed stack objects.
// Use BP to access non-fixed stack objects.
//
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision: https://reviews.llvm.org/D114246
2021-11-30 10:39:35 +08:00
Hsiangkai Wang 4ae2222e14 [RISCV] Add a test case to show the bug in RISCVFrameLowering.
If the number of arguments is too large to use register passing, it
needs to occupy stack space to pass the arguments to the callee. There
are two scenarios. One is to reserve the space in prologue and the other
is to reserve the space before the function calls. When we need to
reserve the stack space before function calls, the stack pointer is
adjusted. Under the scenario, we should not use stack pointer to access
the stack objects. It looks like,

callseq_start  ->  sp = sp - reserved_space
//
// We should not use SP to access stack objects in this area.
//
call @foo
callseq_end    ->  sp = sp + reserved_space

Differential Revision: https://reviews.llvm.org/D114245
2021-11-30 10:39:34 +08:00
Mircea Trofin fde937748b [NFC] Header comment in X86RegisterBanks.td referred to Aarch64
Differential Revision: https://reviews.llvm.org/D114763
2021-11-29 17:59:47 -08:00
Vitaly Buka 25a7e4b9f7 [sanitizer] Add Leb128 encoding/decoding
Reviewed By: dvyukov, kstoimenov

Differential Revision: https://reviews.llvm.org/D114464
2021-11-29 17:12:34 -08:00
Luís Ferreira 2e5c47eda1
Revert "[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h"
This reverts commit 6f99e1aa58.
2021-11-30 00:52:53 +00:00
David Blaikie bd4c6a476f Add missing header 2021-11-29 16:29:37 -08:00
Aart Bik 7d4da4e1ab [mlir][sparse] generalize sparse tensor output implementation
Moves sparse tensor output support forward by generalizing from injective
insertions only to include reductions. This revision accepts the case with all
parallel outer and all reduction inner loops, since that can be handled with
an injective insertion still. Next revision will allow the inner parallel loop
to move inward (but that will require "access pattern expansion" aka "workspace").

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D114399
2021-11-29 16:15:53 -08:00
Matthias Braun 87ba99c263 X86: Fold masked-merge when and-not is not available
Differential Revision: https://reviews.llvm.org/D112754
2021-11-29 16:09:01 -08:00
Matthias Braun 53dfa52546 Tests for D112754
Differential Revision: https://reviews.llvm.org/D113151
2021-11-29 16:09:01 -08:00
Luís Ferreira b779f02a1c [Demangle] Add support for D anonymous symbols
Anonymous symbols are represented by 0 in the mangled symbol. We should skip
    them in order to represent the demangled name correctly, otherwise demangled
    names like `demangle..anon` can happen.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D114307
2021-11-29 16:05:48 -08:00
David Blaikie 6e08abdc25 [Demangle] Add support for multiple identifiers in D qualified names
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D114305
2021-11-29 16:05:33 -08:00
David Blaikie e63c799a76 [Demangle] Add support for D simple single qualified names
This patch adds support for simple single qualified names that includes
    internal mangled names and normal symbol names.

Differential Revision: https://reviews.llvm.org/D111415
2021-11-29 16:05:32 -08:00
Mircea Trofin e8b8304d76 [NFC][Regalloc] Split canEvictInterference into hint and general
There are 2 eviction queries. One is made by tryAssign, when it attempts to
free an interference occupying the hint of the candidate. The other is
during 'regular' interference resolution, where we scan over all
physical registers and try to see if we can evict live ranges in favor
of the candidate. We currently use the same logic in both cases, just
that the former never passes the cost to any subsequent query.
Technically, the 2 decisions could be implemented with different
policies.

This patch splits the 2.

RFC: https://lists.llvm.org/pipermail/llvm-dev/2021-November/153639.html

Differential Revision: https://reviews.llvm.org/D114019
2021-11-29 16:04:03 -08:00
Luís Ferreira 6f99e1aa58
[lldb][NFC] Format lldb/include/lldb/Symbol/Type.h
Reviewed By: teemperor, JDevlieghere

Differential Revision: https://reviews.llvm.org/D113604

Signed-off-by: Luís Ferreira <contact@lsferreira.net>
2021-11-29 23:55:58 +00:00
Jon Chesterfield 3ab150f6e4 [openmp][devicertl] Add a missing loader_uninitialized attribute 2021-11-29 23:54:37 +00:00
Salman Javed c7aa358798 [clang-tidy] Fix pr48613: "llvm-header-guard uses a reserved identifier"
Fixes https://bugs.llvm.org/show_bug.cgi?id=48613.

llvm-header-guard is suggesting header guards with leading underscores
if the header file path begins with a '/' or similar special character.
Only reserved identifiers should begin with an underscore.

Differential Revision: https://reviews.llvm.org/D114149
2021-11-30 12:43:35 +13:00
Jeremy Morse 0eee844539 [DebugInfo][InstrRef] Terminate overlapping variable fragments
If we have a variable where its fragments are split into overlapping
segments:

    DBG_VALUE $ax, $noreg, !123, !DIExpression(DW_OP_LLVM_fragment_0, 16)
    ...
    DBG_VALUE $eax, $noreg, !123, !DIExpression(DW_OP_LLVM_fragment_0, 32)

we should only propagate the most recently assigned fragment out of a
block. LiveDebugValues only deals with live-in variable locations, as
overlaps within blocks is DbgEntityHistoryCalculators domain.

InstrRefBasedLDV has kept the accumulateFragmentMap method from
VarLocBasedLDV, we just need it to recognise DBG_INSTR_REFs. Once it's
produced a mapping of variable / fragments to the overlapped variable /
fragments, VLocTracker uses it to identify when a debug instruction needs
to terminate the other parts it overlaps with. The test is updated for
some standard "InstrRef picks different registers" variation, and the
order of some unrelated DBG_VALUEs changes.

Differential Revision: https://reviews.llvm.org/D114603
2021-11-29 23:37:20 +00:00
Fabian Wolff 45ecfed6c6 [CVP] Remove ashr of -1 or 0
Fixes PR#52190. There is already a check for converting ashr instructions with non-negative left-hand sides into lshr; this patch adds an optimization to remove ashr altogether if the left-hand side is known to be in the range [-1, 1).

Differential Revision: https://reviews.llvm.org/D113835
2021-11-29 15:32:09 -08:00
Philip Reames 8906a0fe64 [SCEVExpander] Drop poison generating flags when reusing instructions
The basic problem we have is that we're trying to reuse an instruction which is mapped to some SCEV. Since we can have multiple such instructions (potentially with different flags), this is analogous to our need to drop flags when performing CSE. A trivial implementation would simply drop flags on any instruction we decided to reuse, and that would be correct.

This patch is almost that trivial patch except that we preserve flags on the reused instruction when existing users would imply UB on overflow already. Adding new users can, at most, refine this program to one which doesn't execute UB which is valid.

In practice, this fixes two conceptual problems with the previous code: 1) a binop could have been canonicalized into a form with different opcode or operands, or 2) the inbounds GEP case which was simply unhandled.

On the test changes, most are pretty straight forward. We loose some flags (in some cases, they'd have been dropped on the next CSE pass anyways). The one that took me the longest to understand was the ashr-expansion test. What's happening there is that we're considering reuse of the mul, previously we disallowed it entirely, now we allow it with no flags. The surrounding diffs are all effects of generating the same mul with a different operand order, and then doing simple DCE.

The loss of the inbounds is unfortunate, but even there, we can recover most of those once we actually treat branch-on-poison as immediate UB.

Differential Revision: https://reviews.llvm.org/D112734
2021-11-29 15:23:34 -08:00
Jeremy Morse fc9dae420c [DebugInfo][InstrRef][NFC] "Final" x86 test cleanup
These are some final test changes for using instruction referencing on X86:
 * Most of these tests just have the flag switched so that they run with
   instr-ref, and just work: these tests were fixed by earlier patches.
 * There are some spurious differences in textual outputs,
 * A few have different temporary labels in the output because more
   MCSymbols are printed to the output.

Differential Revision: https://reviews.llvm.org/D114588
2021-11-29 22:56:09 +00:00
Philip Reames f50207c015 [unroll] Use early return in shouldPartialUnroll [nfc] 2021-11-29 14:37:18 -08:00
Philip Reames a655e0f991 [unroll] Reduce scope of UnrollFactor variable in computeUnrollCount [NFC]
Suggested in review of D114453, done as a separate change to get all uses at once.
2021-11-29 14:33:14 -08:00
Jeremy Morse a20987adf4 [DebugInfo][InstrRef] Add indirection from dbg.declare in SelectionDAG
Usually dbg.declares get translated into either entries in an MF
side-table, or a DBG_VALUE on entry to the function with IsIndirect set
(including in instruction referencing mode). Much rarer is a dbg.declare
attached to a non-argument value, such as in the test added in this patch
where there's a variable-length-array. Such dbg.declares become SDDbgValue
nodes with InIndirect=true.

As it happens, we weren't correctly emitting DBG_INSTR_REFs with the
additional indirection. This patch adds the extra indirection, encoded as
adding an additional DW_OP_deref to the expression.

Differential Revision: https://reviews.llvm.org/D114440
2021-11-29 22:24:19 +00:00
Philip Reames 829b62adf5 [unroll] Split full exact and full bound unroll costing [NFC]
This change should be NFC. It's posted for review mostly to make sure others are happy with the names I'm introducing for "exact full unroll" and "bounded full unroll". The motivation here is that our cost model for bounded unrolling is too aggressive - it gives benefits for exits we aren't going to prune - but I also just think the new version of the code is a lot easier to follow.

Differential Revision: https://reviews.llvm.org/D114453
2021-11-29 14:18:15 -08:00
Fangrui Song 1ce51a5f35 [ELF] --cref: If -Map is specified, print to the map file
PR48282: This behavior matches GNU ld and gold.

Reviewed By: markj

Differential Revision: https://reviews.llvm.org/D114663
2021-11-29 14:14:53 -08:00
Sanjay Patel 99f8b795cc [InstCombine] try to fold 'or' into 'mul' operand
or (mul X, Y), X --> mul X, (add Y, 1) (when the multiply has no common bits with X)

We already have this fold if the pattern ends in 'add', but we can miss it if the
'add' becomes 'or' via another no-common-bits transform.

This is part of fixing:
http://llvm.org/PR49055
...but it won't make a difference on that example yet.

https://alive2.llvm.org/ce/z/Vrmoeb

Differential Revision: https://reviews.llvm.org/D114729
2021-11-29 17:03:08 -05:00
Jeremy Morse 9cf31b8d39 [DebugInfo][InstrRef] Preserve properties of restored variables
InstrRefBasedLDV observes when variable locations are clobbered, scans what
values are available in the machine, and re-issues a DBG_VALUE for the
variable if it can find another location. Unfortunately, I hadn't joined up
the Indirectness flag, so if it did this to an Indirect Value, the
indirectness would be dropped.

Fix this, and add a test that if we clobber a variable value (on the stack
in this case), then the recovered variable location keeps the Indirect
flag.

Differential Revision: https://reviews.llvm.org/D114378
2021-11-29 21:57:24 +00:00
David Green 410d276400 [DAG] Add tests for fpsti.sat for various architectures. NFC 2021-11-29 21:57:13 +00:00
Matt Arsenault 935abeaace OpenMP: Correctly query location for amdgpu-arch
This was trying to figure out the build path for amdgpu-arch, and
making assumptions about where it is which were not working on my
system. Whether a standalone build or not, we should have a proper
imported target to get the location from.
2021-11-29 16:31:32 -05:00
Adrian Prantl 4f215bfa6e Update unit test API usage (NFC) 2021-11-29 13:14:35 -08:00
Jeremy Morse 32815bc907 [DebugInfo][InstrRef][NFC] Test changes: DBG_VALUE to DBG_INSTR_REF
This patch contains a bunch of replacements of:

    DBG_VALUE $somereg

with,

    SOMEINST debug-instr-number1
    DBG_INSTR_REF 1, 0, ...

It's mostly SelectionDAG tests that are making sure that the variable
location assignment is placed in the correct position in the instructions.

To avoid a loss in test coverage of SelectionDAG, which is used by a lot
of different backends, all these tests now have two modes and sets of RUN
lines, one for DBG_VALUE mode, the other for instruction referencing.

Differential Revision: https://reviews.llvm.org/D114258
2021-11-29 20:53:48 +00:00
Matt Arsenault 25eb7fa01d Revert "OpenMP: Start calling setTargetAttributes for generated kernels"
This reverts commit 6c27d389c8.

This is failing on the buildbots
2021-11-29 15:47:10 -05:00
Aart Bik 52668355f4 [mlir][sparse] some leftover cleanup from migration to bufferization dialect
Reviewed By: pifon2a

Differential Revision: https://reviews.llvm.org/D114730
2021-11-29 12:46:01 -08:00
Nikita Popov eee035235e [LICM] Regenerate test checks (NFC) 2021-11-29 21:28:33 +01:00
Sanjay Patel 142044a0b5 [InstCombine] add tests for or with mul operand; NFC 2021-11-29 14:57:44 -05:00
Stanislav Mekhanoshin 5c6b9e1622 [InstCombine] (~(a | b) & c) | ~(c | (a ^ b)) -> ~((a | b) & (c | (b ^ a)))
```
----------------------------------------
define i3 @src(i3 %a, i3 %b, i3 %c) {
%0:
  %or1 = or i3 %b, %c
  %not1 = xor i3 %or1, 7
  %and1 = and i3 %a, %not1
  %xor1 = xor i3 %b, %c
  %or2 = or i3 %xor1, %a
  %not2 = xor i3 %or2, 7
  %or3 = or i3 %and1, %not2
  ret i3 %or3
}
=>
define i3 @tgt(i3 %a, i3 %b, i3 %c) {
%0:
  %obc = or i3 %b, %c
  %xbc = xor i3 %b, %c
  %o = or i3 %a, %xbc
  %and = and i3 %obc, %o
  %r = xor i3 %and, 7
  ret i3 %r
}
Transformation seems to be correct!
```

Differential Revision: https://reviews.llvm.org/D112955
2021-11-29 11:20:34 -08:00
Steven Wan 3c32c56884 [NFC][clang]Increase the number of driver diagnostics
We're close to hitting the limited number of driver diagnostics, increase `DIAG_SIZE_DRIVER` to accommodate more.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D114615
2021-11-29 14:12:03 -05:00
Anshil Gandhi df0560ca00 [HIP] Add atomic load, atomic store and atomic cmpxchng_weak builtin support in HIP-clang
Introduce `__hip_atomic_load`, `__hip_atomic_store` and `__hip_atomic_compare_exchange_weak`
builtins in HIP.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D114553
2021-11-29 12:07:13 -07:00
Zequan Wu fe270ab061 [LLDB][NativePDB] fix find-functions.cpp failure on windows bots (2) 2021-11-29 11:06:06 -08:00
Matt Arsenault 6c27d389c8 OpenMP: Start calling setTargetAttributes for generated kernels
This wasn't setting any of the attributes the target would expect to
emit for kernels.
2021-11-29 13:43:34 -05:00
Louis Dionne a8278a747d [libc++] Fix incorrect REQUIRES on a locale-dependent test
The test doesn't depend specifically on the en_US.UTF-8 locale, instead
it depends on whether localization support exists, period.

Differential Revision: https://reviews.llvm.org/D114708
2021-11-29 13:42:57 -05:00
Steven Wan 23dc886226 [NFC][AIX]Disable unsupported hip test on AIX
AIX doesn't support GPU. There is no point testing HIP on it.

Reviewed By: Jake-Egan

Differential Revision: https://reviews.llvm.org/D114484
2021-11-29 13:26:26 -05:00
Zequan Wu 34d02fada2 [LLDB][NativePDB] fix find-functions.cpp failure on windows bots 2021-11-29 10:05:09 -08:00
Benjamin Kramer 8d474f1d15 [mlir] Handle an edge case when folding reshapes with multiple trailing 1 dimensions
We would exit early and miss this case.

Differential Revision: https://reviews.llvm.org/D114711
2021-11-29 18:31:43 +01:00
Kazu Hirata f240e528ce [llvm] Use range-based for loops (NFC) 2021-11-29 09:04:44 -08:00
Mehrnoosh Heidarpour c572eb1ad9 [InstCombine] Fold (~A | B) ^ A --> ~(A & B)
https://alive2.llvm.org/ce/z/gLrYPk

Fixes:
https://llvm.org/PR52518

Reviewed by: spatel

Differential revision: https://reviews.llvm.org/D114339
2021-11-29 11:29:21 -05:00
Nikita Popov 77dd579827 [SCEV] Remove incorrect assert
Fix assertion failure reported on D113349 by removing the assert.
While the produced expression should be equivalent, it may not
be strictly the same, e.g. due to lazy nowrap flag updates. Similar
to what the main createSCEV() code does, simply retain the old
value map entry if one already exists.
2021-11-29 17:09:12 +01:00
Matt Morehouse 2022e2fcd0 [HWASan] Disable LTO test on aarch64.
It fails for non-Android aarch64 bots as well.
2021-11-29 08:08:17 -08:00
Valentin Clement 1cc3b135aa
[fir] Get rid of the global option in FIRBuilder
Replace the global option `nameLengthHashSize` with a constexpr
with the same name. The option was not used in fir-dev so switching
to a constexpr is fine.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D114630
2021-11-29 17:08:09 +01:00
Roman Lebedev 7e73c2a66a
[X86][Costmodel] `getInterleavedMemoryOpCostAVX512()`: masked load can not be folded into a shuffle
The mask on the shuffle is for the output, not the input.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D114697
2021-11-29 18:37:07 +03:00