Commit Graph

2025 Commits

Author SHA1 Message Date
Owen Anderson 8335e8fa63 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
2010-11-30 22:45:47 +00:00
Owen Anderson 299382e8cb Add encoding support for Thumb2 PLD and PLI instructions.
llvm-svn: 120449
2010-11-30 19:19:31 +00:00
Jim Grosbach 8b16618685 The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,
no extra encoding information), so we no longer need to special case them
here.

llvm-svn: 120444
2010-11-30 19:08:32 +00:00
Jim Grosbach f01da1a7df Tidy up.
llvm-svn: 120443
2010-11-30 19:00:13 +00:00
Jim Grosbach 89a4795b52 Delete a few no longer needed references to pseudos.
llvm-svn: 120441
2010-11-30 18:56:13 +00:00
Bob Wilson 318ce7cb3f Fix the encoding of VLD4-dup alignment.
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
2010-11-30 00:00:42 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
2010-11-29 22:37:40 +00:00
Jim Grosbach 81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.

llvm-svn: 120320
2010-11-29 21:28:32 +00:00
Michael J. Spencer ab425d8360 I swear I did a make clean and make before committing all this...
llvm-svn: 120304
2010-11-29 18:47:54 +00:00
Michael J. Spencer 447762da85 Merge System into Support.
llvm-svn: 120298
2010-11-29 18:16:10 +00:00
Bob Wilson b91ae1ac52 Fix copy-and-paste error in exception message.
llvm-svn: 120033
2010-11-23 19:38:34 +00:00
Jason W Kim 5a97bd873e Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.

llvm-svn: 119760
2010-11-18 23:37:15 +00:00
Bill Wendling 4a08e563d7 Give the exclamation point a name instead of a number.
llvm-svn: 119759
2010-11-18 23:36:54 +00:00
Bob Wilson 4e22a38759 Change the 'x' type modifier for Neon intrinsics to force a signed integer.
This makes it symmetric with the 'u' modifier that forces an unsigned type.
This is needed for unsigned vector shifts, where the shift amount still needs
to be signed.  PR8482 (Radar 8603521).

llvm-svn: 119742
2010-11-18 21:43:22 +00:00
Evan Cheng 7f8ab6ee8b Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Bill Wendling 9898ac97fd Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
2010-11-17 04:32:08 +00:00
Bob Wilson 712f07de0e Use new neon_vector_type and neon_polyvector_type attributes for Neon vectors.
llvm-svn: 119406
2010-11-16 23:57:06 +00:00
Bob Wilson 789e015ce7 Change Neon polynomial types to be signed to match GCC.
llvm-svn: 119405
2010-11-16 23:57:03 +00:00
Bob Wilson 0045702afe Refactor to new GetNumElements function.
No functional change.

llvm-svn: 119404
2010-11-16 23:57:01 +00:00
Bob Wilson dfac58bed1 Tidy up some things in <arm_neon.h>.
Stop defining types with "__neon_" prefixes and then using typedefs without
the prefix; there's no reason to do that anymore.  Remove types that combine
multiple Neon vectors and treat them as a single long vector; they are not
used.

llvm-svn: 119369
2010-11-16 19:39:14 +00:00
Bob Wilson 2880185194 Reapply "Stop using struct wrappers for Neon vector types in <arm_neon.h>."
I've temporarily disabled the failing clang test.

llvm-svn: 119367
2010-11-16 19:16:06 +00:00
Bob Wilson 4d9c9a646b Revert "Stop using struct wrappers for Neon vector types in <arm_neon.h>."
It's breaking buildbots.

llvm-svn: 119363
2010-11-16 18:43:07 +00:00
Bob Wilson d6b6755414 Stop using struct wrappers for Neon vector types in <arm_neon.h>.
Thanks to Nate Begeman for an earlier version of this patch.

llvm-svn: 119358
2010-11-16 18:17:03 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Chris Lattner 578c765fc8 pull the code to get the operand value out of the loop.
llvm-svn: 119130
2010-11-15 07:09:28 +00:00
Chris Lattner c19d510363 split the giant encoder loop into two new helper functions.
llvm-svn: 119129
2010-11-15 06:59:17 +00:00
Chris Lattner 42c4ac4841 reduce nesting and minor cleanups, no functionality change.
llvm-svn: 119128
2010-11-15 06:42:13 +00:00
Chris Lattner 63274cbc5d add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
2010-11-15 05:19:05 +00:00
Jim Grosbach c33f28bf90 ARM fixup encoding for direct call instructions (BL).
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
Owen Anderson c88ce8329c Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
Not yet used.

llvm-svn: 118759
2010-11-11 01:19:24 +00:00
Dan Gohman f899c87343 Rename AccessesArguments and AccessesArgumentsReadonly, and rewrite
their comments.

llvm-svn: 118696
2010-11-10 18:30:00 +00:00
Dan Gohman 88d5f7fd95 Translate IntrReadArgMem to AccessesArgumentsReadonly.
llvm-svn: 118622
2010-11-09 20:07:20 +00:00
Chris Lattner d6746d5b46 pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt.
llvm-svn: 118359
2010-11-06 22:06:03 +00:00
Chris Lattner 4869d346e3 add (and document) the ability for alias results to have
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352
2010-11-06 19:57:21 +00:00
Chris Lattner b6f8e8248d generalize alias support to allow the result of an alias to
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350
2010-11-06 19:25:43 +00:00
Chris Lattner db6f90c61c fix a bug where we had an implicit assumption that the
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334
2010-11-06 08:20:59 +00:00
Chris Lattner 8188fb264f fix some bugs in the alias support, unblocking changing of "clr" aliases
from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330
2010-11-06 07:31:43 +00:00
Chris Lattner fecdad6237 Reimplement BuildResultOperands to be in terms of the result instruction's
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329
2010-11-06 07:14:44 +00:00
Chris Lattner b625dd2d87 implement more checking to reject things like:
(someinst GR16:$foo, GR32:$foo)

Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.

llvm-svn: 118328
2010-11-06 07:06:09 +00:00
Chris Lattner 7603052d49 decode and validate instruction alias result definitions.
llvm-svn: 118327
2010-11-06 06:54:38 +00:00
Chris Lattner 23064cb4e5 simplify
llvm-svn: 118326
2010-11-06 06:45:08 +00:00
Chris Lattner 9f093815fa fix another fixme, replacing a string with a semantic pointer.
llvm-svn: 118325
2010-11-06 06:43:11 +00:00
Chris Lattner 8ffd129950 disolve a hack, having CodeGenInstAlias decode the alias in the .td
file instead of the asmmatcher.

llvm-svn: 118324
2010-11-06 06:39:47 +00:00
Duncan Sands 71049f78ed In the calling convention logic, ValVT is always a legal type,
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
2010-11-04 10:49:57 +00:00
Chris Lattner 4efe13d8d4 partition operand processing between aliases and instructions.
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future.   This removes some
uses of TheOperandList.

llvm-svn: 118232
2010-11-04 02:11:18 +00:00
Chris Lattner ccde463250 pull name slicing out of BuildInstructionOperandReference so
it doesn't do any lexical stuff anymore.

llvm-svn: 118230
2010-11-04 01:58:23 +00:00
Chris Lattner 897a140e2a cleanups.
llvm-svn: 118228
2010-11-04 01:55:23 +00:00
Chris Lattner 7108dad130 replace SrcOpNum with SrcOpName, eliminating a numering dependency
on the incoming operand list.  This also makes the code simpler.

llvm-svn: 118225
2010-11-04 01:42:59 +00:00
Chris Lattner 4779e3e94a strength reduce some code, resolving a fixme.
llvm-svn: 118219
2010-11-04 00:57:06 +00:00
Chris Lattner 743081d097 take a big step to making aliases more general and less of a hack:
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.

llvm-svn: 118217
2010-11-04 00:43:46 +00:00