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56 Commits

Author SHA1 Message Date
Nate Begeman bc3ec1d37b Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ 
PowerPC/and-imm.ll

llvm-svn: 26136
 2006-02-12 09:09:52 +00:00
Chris Lattner 1240574609 PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Chris Lattner 268d3584fc ahem :) 
llvm-svn: 25239
 2006-01-12 02:05:36 +00:00
Nate Begeman 1b8121b227 Add bswap, rotl, and rotr nodes 
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222
 2006-01-11 21:21:00 +00:00
Nate Begeman 477933cfbd Remove a comment that no longer applies. 
llvm-svn: 25167
 2006-01-10 00:15:59 +00:00
Chris Lattner bfb2de9030 add ret void support back 
llvm-svn: 25164
 2006-01-09 23:20:37 +00:00
Evan Cheng 7785e5b3a4 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.

llvm-svn: 25155
 2006-01-09 18:28:21 +00:00
Jim Laskey 762e9ec06c Added initial support for DEBUG_LABEL allowing debug specific labels to be 
inserted in the code.

llvm-svn: 25104
 2006-01-05 01:25:28 +00:00
Jim Laskey 0da76a676a Add unique id to debug location for debug label use (work in progress.) 
llvm-svn: 25096
 2006-01-04 15:04:11 +00:00
Nate Begeman 336dba6fb1 Add support for generating v4i32 altivec code 
llvm-svn: 25046
 2005-12-30 00:12:56 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng 82285c55aa Flip the meaning of FPContractions to reflect Requires<[]> change. 
llvm-svn: 24884
 2005-12-20 20:08:53 +00:00
Nate Begeman b11b8e44fa Pattern-match return. Includes gross hack! 
llvm-svn: 24874
 2005-12-20 00:26:01 +00:00
Nate Begeman 8e6a8af205 Convert load/store over to being pattern matched 
llvm-svn: 24871
 2005-12-19 23:25:09 +00:00
Jim Laskey 7c462768ed Added source file/line correspondence for dwarf (PowerPC only at this point.) 
llvm-svn: 24748
 2005-12-16 22:45:29 +00:00
Nate Begeman 672578bd94 Add a second vector type to the VRRC register class, and fix some patterns 
so that tablegen can infer all types.

llvm-svn: 24746
 2005-12-16 09:19:13 +00:00
Nate Begeman e37cb604c1 Use the new predicate support that Evan Cheng added to remove some code 
from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719
 2005-12-14 22:54:33 +00:00
Evan Cheng 3db275d996 Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. 
llvm-svn: 24716
 2005-12-14 22:07:12 +00:00
Nate Begeman 40f081d8e0 Add support for fmul node of type v4f32. 
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr

llvm-svn: 24701
 2005-12-14 00:34:09 +00:00
Nate Begeman 69caef2b78 Prepare support for AltiVec multiply, divide, and sqrt. 
llvm-svn: 24700
 2005-12-13 22:55:22 +00:00
Chris Lattner 090eed0483 Remove type casts that are no longer needed 
llvm-svn: 24661
 2005-12-11 07:45:47 +00:00
Nate Begeman 4e56db674c Add support for TargetConstantPool nodes to the dag isel emitter, and use 
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.

llvm-svn: 24657
 2005-12-10 02:36:00 +00:00
Nate Begeman ade6f9a255 Add support patterns to many load and store instructions which will 
hopefully use patterns in the near future.

llvm-svn: 24651
 2005-12-09 23:54:18 +00:00
Chris Lattner fea33f7e64 Use new PPC-specific nodes to represent shifts which require the 6-bit 
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.

llvm-svn: 24615
 2005-12-06 02:10:38 +00:00
Chris Lattner f3322af5c6 Add some explicit type casts so that tblgen knows the type of the shift 
amount, which is not necessarily the same as the type being shifted.

llvm-svn: 24594
 2005-12-05 02:34:05 +00:00
Chris Lattner f979794717 Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen 
improvements.

llvm-svn: 24591
 2005-12-04 19:01:59 +00:00
Chris Lattner fd857daa0d Finish moving uncond br over to .td file, remove from .cpp file. 
llvm-svn: 24590
 2005-12-04 18:48:01 +00:00
Chris Lattner d9d18aff6a Define BR in the .td file now that Evan made tblgen smarter. 
llvm-svn: 24589
 2005-12-04 18:42:54 +00:00
Nate Begeman 048b26387b Represent the encoding of the SPR instructions as they actually are, so 
that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521
 2005-11-29 22:42:50 +00:00
Nate Begeman c138118cdb Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516
 2005-11-29 08:04:45 +00:00
Nate Begeman 11fd6b22b1 Small tweaks noticed while on the plane. 
llvm-svn: 24492
 2005-11-26 22:39:34 +00:00
Nate Begeman 8492fd30ab Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489
 2005-11-23 05:29:52 +00:00
Chris Lattner bd9efdb64c disentangle call operands from branch operands a bit 
llvm-svn: 24400
 2005-11-17 19:16:08 +00:00
Chris Lattner 4b11fa284d Generate LA and ADDIS when possible. 
llvm-svn: 24395
 2005-11-17 17:52:01 +00:00
Chris Lattner 595088aa0f Add an initial hack at legalizing GlobalAddress into the appropriate nodes 
on Darwin to remove smarts from the isel.  This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file.  However, we can currently emit stuff like
this:  :)

        li r2, lo16(L_x$non_lazy_ptr)
        lis r3, ha16(L_x$non_lazy_ptr)
        lwzx r2, r3, r2

The obvious improvements will follow.

llvm-svn: 24390
 2005-11-17 07:30:41 +00:00
Chris Lattner 63ed749ce0 LI could theoretically be used for the lo-part of a global address, just like 
lis can be used for the high part.

llvm-svn: 24388
 2005-11-17 07:04:43 +00:00
Nate Begeman a171f6b20c Patch to clean up function call pseudos and support the BLA instruction, 
which branches to an absolute address.  This is required to support objc
direct dispatch.

llvm-svn: 24370
 2005-11-16 00:48:01 +00:00
Chris Lattner 5d6cb604de add support for branch on ordered/unordered. 
llvm-svn: 24067
 2005-10-28 20:32:44 +00:00
Chris Lattner 81ff73ec46 autogen undef 
llvm-svn: 23991
 2005-10-25 21:03:41 +00:00
Chris Lattner b439dad538 Allow pseudos to have patterns, no functionality change 
llvm-svn: 23988
 2005-10-25 20:58:43 +00:00
Chris Lattner 261009a4df Autogen fsel 
llvm-svn: 23987
 2005-10-25 20:55:47 +00:00
Chris Lattner cd7f101c9a Autogen a few new ppc-specific nodes 
llvm-svn: 23985
 2005-10-25 20:41:46 +00:00
Chris Lattner e296949fbe Instead of aborting if not a case we can handle specially, break out and 
let the generic code handle it.  This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.

also, reindent this code

llvm-svn: 23874
 2005-10-21 21:17:10 +00:00
Nate Begeman fd0d55ec69 Match rotate. This does actually match the rotates in an rc5 cipher, but I 
haven't seen it fire on our testsuite.

llvm-svn: 23863
 2005-10-21 06:36:18 +00:00
Nate Begeman 60bbe2d1e5 Add some more patterns for i64 on ppc 
llvm-svn: 23842
 2005-10-20 07:51:08 +00:00
Jim Laskey 74ab9960f2 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Nate Begeman 9f3c26c4ea Write patterns for the various shl and srl patterns that don't involve 
doing something clever.

llvm-svn: 23824
 2005-10-19 18:42:01 +00:00
Chris Lattner c16b0c387f now that tblgen is smarter, use integers directly. This should help Andrew too 
llvm-svn: 23818
 2005-10-19 04:32:04 +00:00
Chris Lattner 5b6f4dc623 Convert these cases to patterns 
llvm-svn: 23811
 2005-10-19 01:38:02 +00:00