Commit Graph

278026 Commits

Author SHA1 Message Date
Mark Searles 9ebdbb433a [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output."
Patch caused a buildbot failure; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15733/steps/build_Lld/logs/stdio :
lib/Target/AMDGPU/SIInsertWaitcnts.cpp:396:11: error: private field 'InstCnt' is not used [-Werror,-Wunused-private-field]
  int32_t InstCnt = 0;
          ^
1 error generated.
"
This reverts commit 71627f79010aafe74fdcba901bba28dd7caa0869.

llvm-svn: 320086
2017-12-07 21:14:41 +00:00
Alex Lorenz 690f0e2f4e [libclang] Record code-completion invocations to a temporary file when
requested by client

This is a follow up to r319702 which records parsing invocations.

These files are not emitted by default, and the client has to specify the
invocation emission path first.

rdar://35322543

llvm-svn: 320085
2017-12-07 20:37:50 +00:00
Mark Searles a84d23489a [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output.
-amdgpu-waitcnt-forcezero={1|0}  Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-amdgpu-waitcnt-forceexp=<n>  Force emit a s_waitcnt expcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcevm=<n>   Force emit a s_waitcnt vmcnt(0) before the first <n> instrs

Differential Revision: https://reviews.llvm.org/D40091

llvm-svn: 320084
2017-12-07 20:36:39 +00:00
Mark Searles d29f24acfb [AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
Differential Revision: https://reviews.llvm.org/D40098

llvm-svn: 320083
2017-12-07 20:34:25 +00:00
George Rokos 145c54721b [OpenMP] NVPTX: Set default/minimum compute capability to sm_35
The current implementation of the nvptx runtime (to be upstreamed shortly) uses the atomicMax operation on 64-bit integers.
This is only supported in compute capabilities 3.5 and later. I've changed the clang default to sm_35.

Differential Revision: https://reviews.llvm.org/D40977

llvm-svn: 320082
2017-12-07 20:27:31 +00:00
Craig Topper dfc79c7c33 [X86] Fix InsertBitToMaskVector to only issue KSHIFTS of native size so that upper bits are properly zeroed.
There's no v2i1 or v4i1 kshift, and v8i1 is only supported with AVXDQ. Isel has fake patterns to extend these types to native shifts, but makes no guarantees about the value of any bits shifted in when shifting right.

This patch promotes the vector to a type that supports a native shift first and only allows inserting into the msb of a native sized shift.

I've constructed this in a way that doesn't do the promotion if we're going to fallback to using a xmm/ymm/zmm shuffle. I think I have a plan to remove the shuffle fall back entirely. In which case we this can be simplified, but I wanted to fix the correctness issue first.

llvm-svn: 320081
2017-12-07 20:10:04 +00:00
Craig Topper 7b8fa5f782 [X86] Fix typo in variable name. NFC
llvm-svn: 320080
2017-12-07 20:10:01 +00:00
Craig Topper b67e5da89b [X86] Make a couple helper lowering methods static.
llvm-svn: 320079
2017-12-07 20:09:55 +00:00
Alexey Bataev 8cf35e4683 [OPENMP] Do not capture private variables in the target regions.
Private variables are completely redefined in the outlined regions, so
we don't need to capture them. Patch adds this behavior to the
target-based regions.

llvm-svn: 320078
2017-12-07 19:49:28 +00:00
Jim Ingham 6c96486962 These tests don't depend on debug info format.
Mark them as such.

llvm-svn: 320077
2017-12-07 19:44:09 +00:00
Adrian Prantl a0de3a8d0a Revert "Temporarily pin tests to DWARF v2 until a more recent version of LLDB"
This reverts commit 319790.

We worked around the bug in LLVM instead.

llvm-svn: 320076
2017-12-07 19:40:31 +00:00
Kostya Serebryany 79990bd606 update hwasan docs
Summary:
* use more readable name
* document the hwasan attribute

Reviewers: eugenis

Reviewed By: eugenis

Subscribers: llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D40938

llvm-svn: 320075
2017-12-07 19:21:30 +00:00
Matt Morehouse 468d4da4e8 [clangd-fuzzer] Update contruction of LSPServer.
The constructor for ClangdLSPServer changed in r318412 and r318925,
breaking the clangd-fuzzer build.

llvm-svn: 320074
2017-12-07 19:04:27 +00:00
Alex Lorenz 6cdef0efb7 [driver] Set the 'simulator' environment for Darwin when compiling for
iOS/tvOS/watchOS simulator

rdar://35135215

Differential Revision: https://reviews.llvm.org/D40682

llvm-svn: 320073
2017-12-07 19:04:10 +00:00
Rafael Espindola d182aaa69d Further simplify .gnu.hash writing. NFC.
llvm-svn: 320072
2017-12-07 18:59:29 +00:00
Vedant Kumar 9df6e0a5ea Disable warnings related to anonymous types in the ObjC plugin
This part of lldb make use of anonymous structs and unions. The usage is
idiomatic and doesn't deserve a warning. Logic in the NSDictionary and NSSet
plugins use anonymous structs in a manner consistent with the relevant Apple
frameworks.

Differential Revision: https://reviews.llvm.org/D40757

llvm-svn: 320071
2017-12-07 18:57:09 +00:00
Rafael Espindola f9f2abe7bd Simplify .gnu.hash writing. NFC.
llvm-svn: 320070
2017-12-07 18:51:19 +00:00
Rafael Espindola 50ca10bb58 Avoid using a temporary std::vector.
With this memory usage when linking clang goes from 174.62MB to
172.77MB.

llvm-svn: 320069
2017-12-07 18:46:03 +00:00
Sanjay Patel 6cfc136870 [InstCombine] add tests for abs using bit hackery; NFC
llvm-svn: 320068
2017-12-07 18:13:33 +00:00
Davide Italiano e2564051be [SBBreakpointOptionCommon] Give this class an explicit destructor.
llvm-svn: 320067
2017-12-07 18:06:06 +00:00
Davide Italiano c218ee58ac [SBBreakpoint] Outline some functions to prevent to be exported.
They're hidden, so all they cause is a linker warning.

ld: warning: cannot export hidden symbol
lldb::SBBreakpointNameImpl::operator==(lldb::SBBreakpointNameImpl const&) from
tools/lldb/source/API/CMakeFiles/liblldb.dir/SBBreakpointName.cpp.o

llvm-svn: 320066
2017-12-07 18:06:06 +00:00
Simon Pilgrim 6d9ac1b1eb [X86] Replace tabs with spaces. NFCI.
llvm-svn: 320065
2017-12-07 17:55:19 +00:00
Simon Pilgrim 386b23f1fa [X86] Tag BMI/BMI2/TBM instructions scheduler classes
Put these under UNARY/BINOP ALU itinerary classes for now - seems to be a good average value

llvm-svn: 320064
2017-12-07 17:37:39 +00:00
Krzysztof Parzyszek 039d4d9286 [Hexagon] Generate HVX code for basic arithmetic operations
Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.

llvm-svn: 320063
2017-12-07 17:37:28 +00:00
Simon Pilgrim d2e93e76b8 [X86][TBM] Add TBM scheduling tests
llvm-svn: 320062
2017-12-07 17:23:00 +00:00
Francis Visoiu Mistrih e6fc3ce470 [CodeGen] Fix index when printing tied machine operands
llvm-svn: 320061
2017-12-07 17:12:30 +00:00
Davide Italiano e1407c2c13 [Target] Remove commented out code. Found by inspection. NFCI.
llvm-svn: 320060
2017-12-07 17:05:56 +00:00
Craig Topper 5db260fca4 [X86] Rename function in recently added test case to not be 'main' returning 'void'. NFC
llvm-svn: 320059
2017-12-07 17:02:49 +00:00
Alexander Richardson 0ce9effaa1 Fix the test from r320056 on Windows
llvm-svn: 320058
2017-12-07 16:41:43 +00:00
Davide Italiano f6e180d523 [DebugInfo] Move this test to X86/ now that it specifies a triple.
Should bring back the arm/arm64 bots. Reported by Yvan Roux.

llvm-svn: 320057
2017-12-07 16:10:39 +00:00
Alexander Richardson 280252c6d1 [ELF][mips] Print the full file path for files with incompatible ISA
Summary:
I also changed the message to print both the ISA and the the architecture
name for incompatible files. Previously it would be quite hard to find the
actual path of the incompatible object files in projects that have many
object files with the same name in different directories.

Reviewers: atanasyan, ruiu

Reviewed By: atanasyan

Subscribers: emaste, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D40958

llvm-svn: 320056
2017-12-07 16:08:59 +00:00
Simon Pilgrim 2983b46973 [X86] Tag SALC instructions scheduler class
Treat these the same as LAHF/SAHF (although its not a x86_64 instruction)

llvm-svn: 320055
2017-12-07 16:07:06 +00:00
Simon Pilgrim ffce0d8fbc [X86] Add LAHF/SAHF scheduling test
llvm-svn: 320054
2017-12-07 16:04:20 +00:00
Simon Pilgrim a13271bcba [X86][VMX] Tag VMX instructions scheduler classes
Tagged all as system instructions

llvm-svn: 320053
2017-12-07 15:57:32 +00:00
Simon Pilgrim a383f84233 [X86] Add SALC scheduling test
llvm-svn: 320052
2017-12-07 15:46:58 +00:00
Simon Pilgrim f1d599adb2 [X86] Tag LZCNT/TZCNT instructions scheduler classes
Tagged as IMUL instructions for a reasonable approximation (ALU tends to be a lot faster) - POPCNT is currently tagged as FAdd which I think should be replaced with IMUL as well

llvm-svn: 320051
2017-12-07 15:24:14 +00:00
Sanjay Patel 9012391af1 [DAGCombiner] eliminate shuffle of insert element
I noticed this pattern in D38316 / D38388. We failed to combine a shuffle that is either 
repeating a scalar insertion at the same position in a vector or translated to a different 
element index.

Like the earlier patch, this could be an instcombine too, but since we opted to make this 
a DAG transform earlier, I've made this one a DAG patch too.

We do not need any legality checking because the new insert is identical to the existing 
insert except that it may have a different constant insertion operand.

The constant insertion test in test/CodeGen/X86/vector-shuffle-combining.ll was the 
motivation for D38756.

Differential Revision: https://reviews.llvm.org/D40209

llvm-svn: 320050
2017-12-07 15:17:58 +00:00
Igor Laevsky 4a4f2e8c67 [InstCombine] Don't crash on out of bounds index in the insertelement
Differential Revision: https://reviews.llvm.org/D40390

llvm-svn: 320049
2017-12-07 15:00:52 +00:00
Simon Pilgrim ff5212091a [X86][FMA] Regenerate fma schedule tests
llvm-svn: 320048
2017-12-07 14:51:47 +00:00
Simon Pilgrim 6b7cd86ca7 [X86][SVM] Tag SVM instructions scheduler classes
Tagged all as system instructions

llvm-svn: 320047
2017-12-07 14:35:17 +00:00
Francis Visoiu Mistrih 567611ef23 [CodeGen] Use more getMFIfAvailable
llvm-svn: 320046
2017-12-07 14:32:15 +00:00
Simon Pilgrim 60411d9a8c [X86] Tag RDRAND/RDSEED instruction scheduler classes
llvm-svn: 320045
2017-12-07 14:18:48 +00:00
Simon Pilgrim bd5f7455a2 [X86][X87] X87 math binop pseudo instructions don't need scheduling info
llvm-svn: 320044
2017-12-07 14:07:18 +00:00
Simon Pilgrim ca63dcce7f [X86][SSE42] SSE42 string pseudo instructions don't need scheduling info
llvm-svn: 320043
2017-12-07 13:52:07 +00:00
Simon Pilgrim 9a2898ed22 [X86] Regenerate RDTSC codegen tests
llvm-svn: 320042
2017-12-07 13:50:29 +00:00
Dan Gohman cdaa87dd2e [WebAssemby] Support main functions with alternate signatures.
WebAssembly requires caller and callee signatures to match, so the usual
C runtime trick of calling main and having it just work regardless of
whether main is defined as '()' or '(int argc, char *argv[])' doesn't
work. Extend the FixFunctionBitcasts pass to rewrite main to use the
latter form.

llvm-svn: 320041
2017-12-07 13:49:27 +00:00
Simon Pilgrim 439679c085 [X86][RDSEED] Add rdseed scheduling tests
llvm-svn: 320040
2017-12-07 13:47:17 +00:00
Simon Pilgrim eb87fe62ec [X86][RDRAND] Add rdrand scheduling tests
llvm-svn: 320039
2017-12-07 13:46:47 +00:00
Alex Bradbury f8f4b90544 [RISCV] MC layer support for the jump/branch instructions of the RVC extension
Differential Revision: https://reviews.llvm.org/D40002
    
Patch by Shiva Chen.

llvm-svn: 320038
2017-12-07 13:19:57 +00:00
Alex Bradbury 9f6aec4b7a [RISCV] MC layer support for load/store instructions of the C (compressed) extension
Differential Revision: https://reviews.llvm.org/D40001
    
Patch by Shiva Chen.

llvm-svn: 320037
2017-12-07 12:50:32 +00:00