Commit Graph

119945 Commits

Author SHA1 Message Date
Sanjay Patel c0ff8bd92e don't repeat function names in comments; NFC
llvm-svn: 243751
2015-07-31 15:10:44 +00:00
Bruno Cardoso Lopes dfc1d96ef8 [CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBefore
This patch is a follow up from r240560 and is a step further into
mitigating the compile time performance issues in CaptureTracker.

By providing the CaptureTracker with a "cached ordered basic block"
instead of computing it every time, MemDepAnalysis can use this cache
throughout its calls to AA->callCapturesBefore, avoiding to recompute it
for every scanned instruction. In the same testcase used in r240560,
compile time is reduced from 2min to 30s.

This also fixes PR22348.

rdar://problem/19230319
Differential Revision: http://reviews.llvm.org/D11364

llvm-svn: 243750
2015-07-31 14:31:35 +00:00
Daniel Sanders e82f2947fd [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when hoisting def's upwards.
Summary:
This prevents vreg260 and D7 from being merged in:
  %vreg260<def> = LDC1 ...
  JAL <ga:@sin>, <regmask ... list not containing D7 ...>
  %D7<def> = COPY %vreg260; ...
Doing so is not valid because the JAL clobbers the D7.

This fixes the almabench regression in the LLVM 3.7.0 release branch.

Reviewers: MatzeB

Subscribers: MatzeB, qcolombet, hans, llvm-commits

Differential Revision: http://reviews.llvm.org/D11649

llvm-svn: 243745
2015-07-31 12:58:55 +00:00
Jingyue Wu 4be014aebe Refactor: Simplify boolean conditional return statements in lib/Target/NVPTX
Summary: Use clang-tidy to simplify boolean conditional return statements

Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D9983

llvm-svn: 243734
2015-07-31 05:09:47 +00:00
Matt Arsenault e1ce344b5a AMDGPU: Fix v16i32 to v16i8 truncstore
llvm-svn: 243731
2015-07-31 04:12:04 +00:00
Kostya Serebryany fb7d8d9d06 [libFuzzer] trace switch statements and apply mutations based on the expected case values
llvm-svn: 243726
2015-07-31 01:33:06 +00:00
Tom Stellard e182e74c53 ELFYAML: Enable parsing of EM_AMDGPU
Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11263

llvm-svn: 243724
2015-07-31 01:15:15 +00:00
Matt Arsenault ba01337942 AMDGPU/SI: Set DwarfRegNum
This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

llvm-svn: 243723
2015-07-31 01:12:10 +00:00
Matt Arsenault a7bc7db53c TableGen: Support folding casts from bits to int
This is to fix an incorrect error when trying to initialize
DwarfNumbers with a !cast<int> of a bits initializer.
getValuesAsListOfInts("DwarfNumbers") would not see an IntInit
and instead the cast, so would give up.

It seems likely that this could be generalized to attempt
the convertInitializerTo for any type. I'm not really sure
why the existing code seems to special case the string cast cases
when convertInitializerTo seems like it should generally handle this
sort of thing.

llvm-svn: 243722
2015-07-31 01:12:06 +00:00
Tom Stellard cb98abe5b7 docs: Add information about helper scripts to HowToReleaseLLVM page
Differential Revision: http://reviews.llvm.org/D10081

llvm-svn: 243720
2015-07-31 01:02:35 +00:00
Tom Stellard 82325598c3 AMDGPU/SI: Remove unused pattern for f32 constant loads
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11603

llvm-svn: 243719
2015-07-31 01:02:32 +00:00
Sumanth Gundapaneni 532a13691c [ARM] Lower modulo operation to generate __aeabi_divmod on Android
For a modulo (reminder) operation,
clang -target armv7-none-linux-gnueabi generates "__modsi3"
clang -target armv7-none-eabi generates "__aeabi_idivmod"
clang -target armv7-linux-androideabi generates "__modsi3"
Android bionic libc doesn't provide a __modsi3, instead it provides a
"__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate
the correct call when ever there is a modulo operation.

Differential Revision: http://reviews.llvm.org/D11661

llvm-svn: 243717
2015-07-31 00:45:12 +00:00
Alex Lorenz 60bf599607 MIR Parser: Report an error when a constant pool item is redefined.
llvm-svn: 243696
2015-07-30 22:00:17 +00:00
Alex Lorenz a06c0c6401 MIR Parser: Report an error when a virtual register is redefined.
llvm-svn: 243695
2015-07-30 21:54:10 +00:00
Sanjay Patel 1166f2ff9f fix memcpy/memset/memmove lowering when optimizing for size
Fixing MinSize attribute handling was discussed in D11363. 
This is a prerequisite patch to doing that.

The handling of OptSize when lowering mem* functions was broken
on Darwin because it wants to ignore -Os for these cases, but the
existing logic also made it ignore -Oz (MinSize).

The Linux change demonstrates a widespread problem. The backend
doesn't usually recognize the MinSize attribute by itself; it
assumes that if the MinSize attribute exists, then the OptSize 
attribute must also exist. 

Fixing this more generally will be a follow-on patch or two.

Differential Revision: http://reviews.llvm.org/D11568

llvm-svn: 243693
2015-07-30 21:41:50 +00:00
Kostya Serebryany c9dc96bfc6 [libFuzzer] fix the strncmp interceptor -- it should respect short strings.
llvm-svn: 243691
2015-07-30 21:22:22 +00:00
Eric Christopher 10f5d60d37 Fix TableGen code generation for ReadNone attribute.
Patch by Pete Abred!

llvm-svn: 243689
2015-07-30 21:16:34 +00:00
Sanjay Patel a93cf60a77 enable fast-math-flag propagation to DAG nodes
This uncovered latent bugs previously:
http://reviews.llvm.org/D10403

...but it's time to try again because internal tests aren't finding more.

If time passes and no other bugs are reported, we can remove this cl::opt.

llvm-svn: 243687
2015-07-30 21:06:55 +00:00
Adhemerval Zanella bfe1eaf0fe Enable dfsan for aarch64
This patch enable DFSan memory transformation for aarch64 (39-bit VMA).

llvm-svn: 243684
2015-07-30 20:49:35 +00:00
Mehdi Amini d937c54944 Add a TargetMachine hook that verifies DataLayout compatibility
Summary: Also provide the associated assertion when CodeGen starts.

Reviewers: echristo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11654

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 243682
2015-07-30 20:33:18 +00:00
Wei Mi d6f7252e2e [SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.
The patch changes the SLPVectorizer::vectorizeStores to choose the immediate
succeeding or preceding candidate for a store instruction when it has multiple
consecutive candidates. In this way it has better chance to find more slp
vectorization opportunities.

Differential Revision: http://reviews.llvm.org/D10445

llvm-svn: 243666
2015-07-30 17:40:39 +00:00
Mehdi Amini 443024b919 Fix lli with OrcLazyJIT: the default DataLayout was used.
Set the correct one using the TargetMachine instead.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 243664
2015-07-30 17:29:33 +00:00
Matt Arsenault 7a0c3a92c0 AMDGPU: Set SubRegIndex size and offset
I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

llvm-svn: 243661
2015-07-30 17:03:11 +00:00
Matt Arsenault b39e858356 AMDGPU: Fix unreachable when emitting binary debug info
Copy implementation of applyFixup from AArch64 with AArch64 bits
ripped out.

Tests will be included with a later commit. Several other
problems must be fixed before binary debug info emission
will work.

llvm-svn: 243660
2015-07-30 17:03:08 +00:00
Alex Lorenz 618b283cd9 MIR Serialization: Serialize the machine basic block's successor weights.
Reviewers: Duncan P. N. Exon Smith
llvm-svn: 243659
2015-07-30 16:54:38 +00:00
David Majnemer d323888e54 [COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristics
llvm-svn: 243658
2015-07-30 16:47:56 +00:00
Tom Stellard 4229aa942d AMDGPU/SI: Simplify moveSMRDToVALU()
Summary:
Replace the switch on instruction opcode with a switch on register size.
This way we don't need to update the switch statement when we add new
SMRD variants.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11601

llvm-svn: 243652
2015-07-30 16:20:42 +00:00
Tom Stellard 9d74076065 AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo
Summary:
This function is never called.  isReallyTriviallyReMaterializable() is
the function that should be implemented instead.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11620

llvm-svn: 243651
2015-07-30 16:20:40 +00:00
Vasileios Kalintiris 3d9d81fbb1 [mips] Fix out-of-date debug information in test file.
Update the debug info in the check-lines because the change in r243638
introduced a constant initialization before the prologue's end as part
of a register spill.

llvm-svn: 243640
2015-07-30 13:13:09 +00:00
NAKAMURA Takumi 1c84ff5f60 MCJITTests/MCJITCAPITest.cpp: Try to appease i686-win32.
llvm-svn: 243639
2015-07-30 13:06:53 +00:00
Vasileios Kalintiris 2041b1dd0b [mips][FastISel] Remove hidden mips-fast-isel option.
Summary:
This hidden option would disable code generation through FastISel by
default. It was removed from the available options and from the
Fast-ISel tests that required it in order to run the tests.

Reviewers: dsanders

Subscribers: qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11610

llvm-svn: 243638
2015-07-30 12:39:33 +00:00
Vasileios Kalintiris 77fb0a3dcf [mips][FastISel] Apply only zero-extension to constants prior to their materialization.
Summary:
Previously, we would sign-extend non-boolean negative constants and
zero-extend otherwise. This was problematic for PHI instructions with
negative values that had a type with bitwidth less than that of the
register used for materialization.

More specifically, ComputePHILiveOutRegInfo() assumes the constants
present in a PHI node are zero extended in their container and
afterwards deduces the known bits.

For example, previously we would materialize an i16 -4 with the
following instruction:

  addiu $r, $zero, -4

The register would end-up with the 32-bit 2's complement representation
of -4. However, ComputePHILiveOutRegInfo() would generate a constant
with the upper 16-bits set to zero. The SelectionDAG builder would use
that information to generate an AssertZero node that would remove any
subsequent trunc & zero_extend nodes.

In theory, we should modify ComputePHILiveOutRegInfo() to consult
target-specific hooks about the way they prefer to materialize the
given constants. However, git-blame reports that this specific code
has not been touched since 2011 and it seems to be working well for every
target so far.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11592

llvm-svn: 243636
2015-07-30 11:51:44 +00:00
Daniel Sanders 3cc4a250a6 [test-release.sh] Add -no-libunwind to disable it on targets that don't support it.
Summary:
Mips doesn't implement unw_getcontext() or libunwind::Registers_*::jumpto() yet
so we must disable libunwind for this release.

Reviewers: hans

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11563

llvm-svn: 243633
2015-07-30 10:14:57 +00:00
Michael Kuperstein cdb076b8d4 [X86] Recognize "flags" as an identifier, not a register in Intel-syntax inline asm
Patch by: marina.yatsina@intel.com
Differential Revision: http://reviews.llvm.org/D11512

llvm-svn: 243630
2015-07-30 10:10:25 +00:00
Matt Arsenault f1ffbe7bb3 Add amdopencl environment to triple
This is used by the AMD x86 OpenCL implementation
to change some ABI details on Windows and Linux.

llvm-svn: 243627
2015-07-30 08:16:51 +00:00
Adam Nemet 252d529b6c [LoopVer] Add missing std::move
The reason I was passing this vector by value in the constructor so that
I wouldn't have to copy when initializing the corresponding member but
then I forgot the std::move.

The use-case is LoopDistribution which filters the checks then
std::moves it to LoopVersioning's constructor.  With this interface we
can avoid any copies.

llvm-svn: 243616
2015-07-30 04:21:13 +00:00
Adam Nemet c75ad69ca5 [LDist] Filter the checks locally rather than in LAA, NFC
Before, we were passing the pointer partitions to LAA.  Now, we get all
the checks from LAA and filter out the checks within partitions in
LoopDistribution.

This effectively concludes the steps to move filtering memchecks from
LAA into its clients.  There is still some cleanup left to remove the
unused interfaces in LAA that still take PtrPartition.

(Moving this functionality to LoopDistribution also requires
needsChecking on pointers to be made public.)

llvm-svn: 243613
2015-07-30 03:29:16 +00:00
Kostya Serebryany b74ba421fc [libFuzzer] implement strncmp hook for data-flow-guided fuzzing (w/ and w/o dfsan), add a test
llvm-svn: 243611
2015-07-30 02:33:45 +00:00
Lang Hames 38008a5e36 [MCJIT] Fix a memory leak in a unit test that was introduced in r243589.
llvm-svn: 243609
2015-07-30 02:05:37 +00:00
Kostya Serebryany 0e776a2250 [libFuzzer] implement memcmp hook for data-flow-guided fuzzing (w/o dfsan), extend the memcmp fuzzer test
llvm-svn: 243603
2015-07-30 01:34:58 +00:00
Pete Cooper 95c14f59a8 Prefix make_reverse_iterator with llvm namespace.
This was fallout from r243581.  Turns out C++14 has make_reverse_iterator.

Thanks to Filipe and David for the quick fix suggestion.

llvm-svn: 243598
2015-07-30 00:40:42 +00:00
Sanjay Patel 5bfbb36a09 push fast-math check for machine-combiner reassociations into instruction-type check; NFC
This makes it simpler to add instruction types that don't depend on fast-math.

llvm-svn: 243596
2015-07-30 00:04:21 +00:00
Matthias Braun 6605ff8efe IR: Implement Value::mergeUseLists() iteratively
This avoids stack overflows when the the compiler does not perform tail call
elimination. Apparently this happens for MSVC with the /Ob2 switch which
may be used by external code including this header.

Reported by and based on a patch from Jean-Francois Riendeau.

Related to rdar://21900756

llvm-svn: 243590
2015-07-29 23:22:48 +00:00
Lang Hames 3393cfdef8 [MCJIT] Fix PR20656 by teaching MCJIT to honor ExecutionEngine's global mapping.
This is important for users of the C API who can't supply custom symbol
resolvers yet.

llvm-svn: 243589
2015-07-29 23:12:33 +00:00
Nick Lewycky c3890d2969 Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.)
Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h.

llvm-svn: 243585
2015-07-29 22:32:47 +00:00
Frederic Riss 4dedb1cdf8 [dsymutil] Re-add command line option -v this time printing the version.
llvm-svn: 243584
2015-07-29 22:29:50 +00:00
Frederic Riss 3137ae9e7f [dsymutil] Use option categories.
Prevent all the unrelated LLVM options to appear in the -help output
by introducing a tool specific option category. As a drive-by improve
the wording of the help message.

llvm-svn: 243583
2015-07-29 22:29:46 +00:00
Frederic Riss 11ab2b8858 [dsymutil] Rename -v option to -verbose
The dsymutil-classic -v option dumps the tool version rather than
putting it in verbose mode. Rename -v to -verbose and update the
tests that use it (in the process removing it from a few tests that
didn't require it anymore since the -dump-debug-map option was
introduced).
A followup commit will reintroduce the -v option that dumps the
version.

llvm-svn: 243582
2015-07-29 22:29:34 +00:00
Pete Cooper f3159f3c12 Reapply "Add reverse(ContainerTy) range adapter."
This reverts commit r243567, which ultimately reapplies r243563.

The fix here was to use std::enable_if for overload resolution.  Thanks to David
Blaikie for lots of help on this, and for the extra tests!

Original commit message follows:

For cases where we needed a foreach loop in reverse over a container,
we had to do something like

 for (const GlobalValue *GV : make_range(TypeInfos.rbegin(),
                                         TypeInfos.rend())) {

This provides a convenience method which shortens this to

 for (const GlobalValue *GV : reverse(TypeInfos)) {

There are 2 versions of this, with a preference to the rbegin() version.

The first uses rbegin() and rend() to construct an iterator_range.

The second constructs an iterator_range from the begin() and end() methods
wrapped in std::reverse_iterator's.

Reviewed by David Blaikie.

llvm-svn: 243581
2015-07-29 22:19:09 +00:00
Eric Christopher d566fb12a1 Rename hasCompatibleFunctionAttributes->areInlineCompatible based
on suggestions. Currently the function is only used for inline purposes
and this is more descriptive for the use.

llvm-svn: 243578
2015-07-29 22:09:48 +00:00