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5 Commits

Author SHA1 Message Date
Luis Marques 3d0fbafd0b [RISCV] Switch to the Machine Scheduler 
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106
 2019-09-17 11:15:35 +00:00
Luis Marques 2d550d19b3 Revert Patch from Phabricator 
This reverts r372092 (git commit e38695a025)

llvm-svn: 372104
 2019-09-17 10:52:09 +00:00
Luis Marques e38695a025 Patch from Phabricator 
llvm-svn: 372092
 2019-09-17 09:43:08 +00:00
Alex Bradbury 5c41ecedf8 [RISCV] Implement isLegalAddImmediate 
This causes a trivial improvement in the recently added lsr-legaladdimm.ll 
test case.

llvm-svn: 330937
 2018-04-26 13:00:37 +00:00
Alex Bradbury c2f78f80da [RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll 
Add a test case which will show a codegen difference upon the implementation 
of a target-specific isLegalAddImmediate.

llvm-svn: 330936
 2018-04-26 12:57:29 +00:00