Akira Hatanaka
314b43b781
MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
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llvm-svn: 164756
2012-09-27 04:08:42 +00:00
Akira Hatanaka
b664ae67ce
MIPS DSP: CMPU.EQ.QB instruction sub-class.
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llvm-svn: 164755
2012-09-27 03:58:34 +00:00
Akira Hatanaka
d09642beb3
MIPS DSP: ADDU.QB instruction sub-class.
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llvm-svn: 164754
2012-09-27 03:13:59 +00:00
Akira Hatanaka
e4bd054f98
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
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llvm-svn: 164751
2012-09-27 02:15:57 +00:00
Akira Hatanaka
9061a46443
MIPS DSP: all the remaining instructions which read or write accumulators.
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llvm-svn: 164750
2012-09-27 02:11:20 +00:00
Akira Hatanaka
1babeaa44c
MIPS DSP: add support for extract-word instructions.
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llvm-svn: 164749
2012-09-27 02:05:42 +00:00
Akira Hatanaka
ecabd1a5d2
MIPS DSP: add functions which decode DSP and accumulator registers.
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llvm-svn: 164748
2012-09-27 02:01:10 +00:00
Akira Hatanaka
42a352485b
MIPS DSP: add code necessary for pseudo instruction lowering.
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llvm-svn: 164747
2012-09-27 01:59:07 +00:00
Akira Hatanaka
de8231eada
MIPS DSP: add bitcast patterns between vectors and int.
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No test cases. These patterns will get tested along with dsp intrinsics.
llvm-svn: 164746
2012-09-27 01:56:38 +00:00
Akira Hatanaka
5eeac4f813
MIPS DSP: add vector load/store patterns.
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llvm-svn: 164744
2012-09-27 01:50:59 +00:00
Bill Wendling
863bab689a
Remove the `hasFnAttr' method from Function.
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The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.
llvm-svn: 164725
2012-09-26 21:48:26 +00:00
Jim Grosbach
c03a0c241e
X86_32: Large Symbol+Offset relocations.
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If the offset is more than 24-bits, it won't fit in a scattered
relocation offset field, so we fall back to using a non-scattered
relocation.
rdar://12358909
llvm-svn: 164724
2012-09-26 21:27:45 +00:00
Akira Hatanaka
7fc726539f
Add case clauses for returning dsp accumulator encoding values in function
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getMipsRegisterNumbering.
llvm-svn: 164720
2012-09-26 19:27:24 +00:00
Akira Hatanaka
e3f79e5505
Add DSP accumulator registers and register class. Remove hi/lo registers.
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llvm-svn: 164719
2012-09-26 19:25:21 +00:00
Akira Hatanaka
8a69b892da
Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.
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llvm-svn: 164718
2012-09-26 19:18:19 +00:00
James Molloy
9e98ef1c59
Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.
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llvm-svn: 164685
2012-09-26 09:48:32 +00:00
Michael Liao
2b425e1e24
Add SARX/SHRX/SHLX code generation support
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llvm-svn: 164675
2012-09-26 08:26:25 +00:00
Michael Liao
2de86af22d
Add RORX code generation support
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llvm-svn: 164674
2012-09-26 08:24:51 +00:00
Michael Liao
f9f7b5518a
Add MULX code generation support
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llvm-svn: 164673
2012-09-26 08:22:37 +00:00
Craig Topper
0a928fa32e
Remove hasNoAVX method. Can just invert hasAVX instead.
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llvm-svn: 164664
2012-09-26 06:29:37 +00:00
Michael Liao
425c0dbc81
Add 'lock' prefix output support in assembly printer
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- Instead of embedding 'lock' into each mnemonic of atomic
instructions except 'xchg', we teach X86 assembly printer to output 'lock'
prefix similar to or consistent with code emitter.
llvm-svn: 164659
2012-09-26 05:13:44 +00:00
Akira Hatanaka
a9d01f1b99
Initialize boolean variables in MipsSubtarget's constructor.
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llvm-svn: 164642
2012-09-25 23:07:11 +00:00
Reed Kotler
7b10400709
blank line for test commit
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llvm-svn: 164640
2012-09-25 22:34:20 +00:00
Sebastian Pop
edb31faf92
TargetLowering interface to set/get minimum block entries for jump tables.
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Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.
getMinimumJumpTableEntries() defaults to 4.
setMinimumJumpTableEntries() allows target configuration.
This patch changes the default for the Hexagon architecture to 5
as it improves performance on some benchmarks.
llvm-svn: 164628
2012-09-25 20:35:36 +00:00
Michael Liao
de51caf2a0
Add missing i64 max/min/umax/umin on 32-bit target
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- Turn on atomic6432.ll and add specific test case as well
llvm-svn: 164616
2012-09-25 18:08:13 +00:00
Jim Grosbach
df8ed71839
ARM: Darwin BL/BLX relocations to out-of-range symbols.
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When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.
rdar://12359919
llvm-svn: 164615
2012-09-25 18:07:17 +00:00
Bob Wilson
165f0a24c6
Consistently specify the assembly variant to MatchInstructionImpl.
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llvm-svn: 164611
2012-09-25 17:19:29 +00:00
Evan Cheng
446ff28df1
Fix an illegal tailcall opt where the callee returns a double via xmm while caller returns x86_fp80 via st0. rdar://12229511
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llvm-svn: 164588
2012-09-25 05:32:34 +00:00
Jim Grosbach
e974a6afaf
ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.
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rdar://9795790
llvm-svn: 164577
2012-09-25 00:08:13 +00:00
Jim Grosbach
361ca34270
Mark jump tables in code sections with DataRegion directives.
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Even out-of-line jump tables can be in the code section, so mark them
as data-regions for those targets which support the directives.
rdar://12362871&12362974
llvm-svn: 164571
2012-09-24 23:06:27 +00:00
Chad Rosier
c4734c8950
Rather then have a wrapper function, have tblgen instantiate the implementation.
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Also remove an unused argument.
llvm-svn: 164567
2012-09-24 22:57:55 +00:00
Roman Divacky
ca10389bfe
Specify MachinePointerInfo as refering to the argument value and offset of the
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store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.
llvm-svn: 164553
2012-09-24 20:47:19 +00:00
Chad Rosier
3cb355d11f
Rather then have a wrapper function, have tblgen instantiate the implementation.
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llvm-svn: 164548
2012-09-24 19:32:29 +00:00
NAKAMURA Takumi
23b5b171eb
ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]
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llvm-svn: 164459
2012-09-22 13:12:28 +00:00
NAKAMURA Takumi
0ac2f2a077
Whitespace.
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llvm-svn: 164458
2012-09-22 13:12:22 +00:00
Tim Northover
2fdbdc5870
Fix edge cases of ARM shift operands in arith instructions.
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As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.
Patch by Chris Lidbury.
llvm-svn: 164456
2012-09-22 11:18:19 +00:00
Tim Northover
0c97e76492
Fix the handling of edge cases in ARM shifted operands.
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This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
llvm-svn: 164455
2012-09-22 11:18:12 +00:00
Michael Liao
2718b20030
Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'
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llvm-svn: 164453
2012-09-22 05:41:15 +00:00
Michael Liao
2456b3ae8c
Fix typo in r164357
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llvm-svn: 164452
2012-09-22 03:39:42 +00:00
Akira Hatanaka
ecfb828341
MIPS DSP: Add immediate leaves.
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llvm-svn: 164435
2012-09-22 00:07:12 +00:00
Akira Hatanaka
329df55de1
MIPS DSP: Add predicates and instruction template.
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llvm-svn: 164434
2012-09-22 00:06:06 +00:00
Akira Hatanaka
fabb8cf421
Add MIPS DSP register classes. Set actions of DSP vector operations and override
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TargetLowering's callback functions.
llvm-svn: 164431
2012-09-21 23:58:31 +00:00
Akira Hatanaka
233ac53a3f
SelectionDAG node enums for MIPS DSP nodes.
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llvm-svn: 164430
2012-09-21 23:52:47 +00:00
Akira Hatanaka
f03b6c34f3
Add MIPS accumulator and DSP control registers.
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llvm-svn: 164429
2012-09-21 23:48:37 +00:00
Akira Hatanaka
65ce931f9a
Add flags and feature bits for mips dsp.
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llvm-svn: 164428
2012-09-21 23:41:49 +00:00
Chad Rosier
17ede627f0
[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.
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llvm-svn: 164420
2012-09-21 22:21:26 +00:00
Chad Rosier
3d325cf3f1
Add comment.
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llvm-svn: 164415
2012-09-21 21:08:46 +00:00
Chad Rosier
143d0f7371
Add comment.
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llvm-svn: 164414
2012-09-21 20:51:43 +00:00
Chad Rosier
8bf01fc663
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
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non-aligned i32 loads/stores.
rdar://12304911
llvm-svn: 164381
2012-09-21 16:58:35 +00:00
Michael Liao
7325a9d08e
Fix a typo in r164357
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llvm-svn: 164372
2012-09-21 16:03:03 +00:00