Commit Graph

159 Commits

Author SHA1 Message Date
Craig Topper 1d32658877 Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
Chad Rosier 248c29966c Fix 80-column violation.
llvm-svn: 151599
2012-02-28 00:23:01 +00:00
Jakob Stoklund Olesen fd7d1b47ba Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."
This caused miscompilations on out-of-tree targets, and possibly i386 as
well.

I'll find some other way of hoisting %rip-relative loads from loops
containing calls.

llvm-svn: 150816
2012-02-17 16:40:44 +00:00
Jakob Stoklund Olesen fd338e9777 Allow Post-RA LICM to hoist reserved register reads.
When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

llvm-svn: 150288
2012-02-11 00:44:19 +00:00
Jakob Stoklund Olesen c8046c02c2 Don't read PreRegAlloc before it is initialized.
llvm-svn: 150286
2012-02-11 00:40:36 +00:00
Andrew Trick 1fa5bcbe2a Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100
2012-02-08 21:23:13 +00:00
Andrew Trick c40815de62 Move pass configuration out of pass constructors: MachineLICM.
llvm-svn: 150099
2012-02-08 21:23:03 +00:00
Andrew Trick 5209c739cd whitespace
llvm-svn: 150098
2012-02-08 21:23:00 +00:00
Jakob Stoklund Olesen 5e1ac45b93 Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

llvm-svn: 149646
2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen 20948fab69 Fix PR11829. PostRA LICM was too aggressive.
This fixes a typo in r148589.

llvm-svn: 148724
2012-01-23 21:01:15 +00:00
Jakob Stoklund Olesen 9082353e3b Simplify debug output.
llvm-svn: 148723
2012-01-23 21:01:11 +00:00
Jakob Stoklund Olesen 6b17ef58a1 Support register masks in MachineLICM.
Only PostRA LICM is affected.

llvm-svn: 148589
2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen 86ae07f049 Extract method for detecting constant unallocatable physregs.
It is safe to move uses of such registers.

llvm-svn: 148259
2012-01-16 22:34:08 +00:00
Evan Cheng da46832e42 80 col violation.
llvm-svn: 147884
2012-01-10 22:27:32 +00:00
Pete Cooper 1c3b1efa58 Hoisted some loop invariant smallvector lookups out of a MachineLICM loop
llvm-svn: 147127
2011-12-22 02:13:25 +00:00
Pete Cooper 1eed5b51e8 Changed MachineLICM to use a worklist list MachineCSE instead of recursion.
Fixes <rdar://problem/10584116>

llvm-svn: 147125
2011-12-22 02:05:40 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Owen Anderson ca2f78a95b Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
llvm-svn: 144747
2011-11-16 01:02:57 +00:00
Evan Cheng 7313337c85 Disable LICM speculation in high register pressure situation again now that Devang has fixed other issues.
llvm-svn: 143003
2011-10-26 01:26:57 +00:00
Devang Patel 1d8ab465bf As Evan suggested, loads from constant pool are safe to speculate.
llvm-svn: 142593
2011-10-20 17:42:23 +00:00
Devang Patel 830c776a94 Add a comment.
llvm-svn: 142592
2011-10-20 17:31:18 +00:00
Evan Cheng aa563df759 Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289
llvm-svn: 142234
2011-10-17 19:50:12 +00:00
Devang Patel 69a4565e65 It is safe to speculate load from GOT. This fixes performance regression caused by r141689.
Radar 10281206.

llvm-svn: 142202
2011-10-17 17:35:01 +00:00
Nick Lewycky 404feb9973 Tabs to spaces.
llvm-svn: 141844
2011-10-13 01:09:50 +00:00
Evan Cheng b35afcaa56 Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions.
llvm-svn: 141813
2011-10-12 21:33:49 +00:00
Bill Wendling 918cea2c27 Expand the check for a landing pad so that it looks at the basic block's
containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.

llvm-svn: 141767
2011-10-12 02:58:01 +00:00
Evan Cheng af1389546e Fix r141744.
1. The speculation check may not have been performed if the BB hasn't had a load
   LICM candidate.
2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the
   instruction even if it's in high register pressure situation.

llvm-svn: 141747
2011-10-12 00:09:14 +00:00
Evan Cheng f192ca0761 Refine r141689 with a tri-state variable.
Also teach MachineLICM to avoid "speculation" when register pressure is high.

llvm-svn: 141744
2011-10-11 23:48:44 +00:00
Bill Wendling 579ff6c39c N.B. This is with the new EH scheme:
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.

I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.

llvm-svn: 141726
2011-10-11 22:42:31 +00:00
Devang Patel 453d401a51 Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141689
2011-10-11 18:09:58 +00:00
Devang Patel 478d5bc0d0 Revert r141569 and r141576.
llvm-svn: 141594
2011-10-10 23:18:02 +00:00
Devang Patel 2689f95875 If loop header is also loop exiting block then it may not be safe to hoist instructions.
llvm-svn: 141576
2011-10-10 20:32:03 +00:00
Devang Patel e554d5995b Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
2011-10-10 19:09:20 +00:00
Evan Cheng 90da66bb69 Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690
llvm-svn: 138934
2011-09-01 01:45:00 +00:00
Evan Cheng 8264e272a9 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Evan Cheng 8d71a75777 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
llvm-svn: 133944
2011-06-27 21:26:13 +00:00
Evan Cheng ef42bea704 Look pass copies when determining whether hoisting would end up inserting more copies. rdar://9266679
llvm-svn: 129297
2011-04-11 21:09:18 +00:00
Cameron Zwarich df61694417 Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
llvm-svn: 127175
2011-03-07 21:56:36 +00:00
Evan Cheng b8b0ad80a8 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
2011-01-20 08:34:58 +00:00
Jakob Stoklund Olesen 2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Dan Gohman 4162e3e213 Add a FIXME comment.
llvm-svn: 118803
2010-11-11 18:08:43 +00:00
Jakob Stoklund Olesen 5c86d22e67 MachineLICM should not claim to be preserving the CFG when it can split critical
edges on demand.

llvm-svn: 117982
2010-11-01 23:59:55 +00:00
Evan Cheng e96b8d7ab6 Use instruction itinerary to determine what instructions are 'cheap'.
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
Evan Cheng 87066f0677 More accurate estimate / tracking of register pressure.
- Initial register pressure in the loop should be all the live defs into the
  loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
  to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.

llvm-svn: 116956
2010-10-20 22:03:58 +00:00
Dan Gohman a94cc6dfe8 Make CodeGen TBAA-aware.
llvm-svn: 116890
2010-10-20 00:31:05 +00:00
Evan Cheng 63c7608c34 Re-enable register pressure aware machine licm with fixes. Hoist() may have
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
2010-10-19 18:58:51 +00:00
Owen Anderson 6c18d1aac0 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
2010-10-19 17:21:58 +00:00
Daniel Dunbar 418204e523 Revert r116781 "- Add a hook for target to determine whether an instruction def
is", which breaks some nightly tests.

llvm-svn: 116816
2010-10-19 17:14:24 +00:00