Commit Graph

53294 Commits

Author SHA1 Message Date
Andrew Trick 02a80da331 misched interface: Expose the MachineScheduler pass.
Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...

llvm-svn: 152278
2012-03-08 01:41:12 +00:00
Jim Grosbach 11e8c0d6b5 ARM don't use MCRelaxAll, as it's not safe on ARM.
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.

rdar://11006355

llvm-svn: 152268
2012-03-08 00:07:52 +00:00
Sean Callanan ca92a3da7c Improved support in RuntimeDyldMachO for generating
code that will be relocated into another memory space.
Now when relocations are resolved, the address of
the relocation in the host memory (where the JIT is)
is passed separately from the address that the
relocation will be at in the target memory (where
the code will run).

llvm-svn: 152264
2012-03-07 23:05:25 +00:00
Andrew Trick 69b4204c18 Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.
llvm-svn: 152262
2012-03-07 23:01:09 +00:00
Andrew Trick 9a0c583954 misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.

llvm-svn: 152261
2012-03-07 23:01:06 +00:00
Andrew Trick d743f71e82 misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.
llvm-svn: 152260
2012-03-07 23:01:02 +00:00
Andrew Trick 9b9dea5d07 misched prep: Comment the ScheduleDAGInstrs interface.
llvm-svn: 152259
2012-03-07 23:00:59 +00:00
Andrew Trick 926d4736ed misched prep: Cleanup ScheduleDAGInstrs interface.
ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.

llvm-svn: 152258
2012-03-07 23:00:57 +00:00
Andrew Trick 67561b3ef2 misched prep: remove extra "protected"
llvm-svn: 152257
2012-03-07 23:00:54 +00:00
Andrew Trick a316faabec misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

llvm-svn: 152256
2012-03-07 23:00:52 +00:00
Andrew Trick 52226d409b misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.

llvm-svn: 152255
2012-03-07 23:00:49 +00:00
Benjamin Kramer 22842f89e4 Copy the right amount of elements.
llvm-svn: 152254
2012-03-07 22:48:42 +00:00
Benjamin Kramer 6e8d4b8eb4 SmallPtrSet: Copy all the elements when swapping, not just numelements.
This fixes a build failure in webkit. Copying all elements shouldn't be
necessary, I'll look out for a better fix soon.

llvm-svn: 152252
2012-03-07 22:33:21 +00:00
Chad Rosier 377f1f2d39 [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point
condition flags to CPSR.  This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.

llvm-svn: 152243
2012-03-07 20:59:26 +00:00
Jakob Stoklund Olesen aa0f752fc8 Fix infinite loop in nested multiclasses.
Patch by Michael Liao!

llvm-svn: 152232
2012-03-07 16:39:35 +00:00
Chandler Carruth 636ee38a88 Try to clarify this comment some.
llvm-svn: 152221
2012-03-07 10:13:40 +00:00
Chandler Carruth 962152ca7a Remove another outbreak of customized (and completely broken) hashing.
This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.

Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...

llvm-svn: 152218
2012-03-07 09:39:46 +00:00
Bill Wendling 7c5dcb6ccf Where the BranchFolding pass removes a branch then adds another better branch,
the DebugLoc information can be maintained throughout by grabbing the DebugLoc
before the RemoveBranch and then passing the result to the InsertBranch.
Patch by Andrew Stanford-Jason!

llvm-svn: 152212
2012-03-07 08:49:42 +00:00
Andrew Trick 1a1b54a2da Fix cmake
llvm-svn: 152210
2012-03-07 05:46:04 +00:00
Andrew Trick f9fa8afdaa comment
llvm-svn: 152209
2012-03-07 05:21:54 +00:00
Andrew Trick 60cf03e772 misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

llvm-svn: 152208
2012-03-07 05:21:52 +00:00
Andrew Trick 42756e2eb4 ScheduleDAGInstrs comments
llvm-svn: 152207
2012-03-07 05:21:47 +00:00
Andrew Trick e932bb77b5 misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.

llvm-svn: 152206
2012-03-07 05:21:44 +00:00
Andrew Trick edee68ce1b misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152205
2012-03-07 05:21:40 +00:00
Andrew Trick 46a58664f7 misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152204
2012-03-07 05:21:36 +00:00
Andrew Trick 7c6c41a56a whitespace
llvm-svn: 152203
2012-03-07 05:21:32 +00:00
Chandler Carruth d4ba3eb480 Switch this code to use hash_combine_range rather than incremental calls
to hash_combine. One of the interfaces could already do this, and the
other can just use a small buffer. This is a much more efficient way to
use the hash_combine interface, although I don't have any particular
benchmark where this code was hot, so I can't measure much of an impact.
It at least doesn't slow anything down.

llvm-svn: 152200
2012-03-07 03:22:32 +00:00
Chandler Carruth cee7a12d40 Cache the sized-ness of struct types, once we reach the steady state of
"is sized". This prevents every query to isSized() from recursing over
every sub-type of a struct type. This could get *very* slow for
extremely deep nesting of structs, as in 177.mesa.

This change is a 45% speedup for 'opt -O2' of 177.mesa.linked.bc, and
likely a significant speedup for other cases as well. It even impacts
-O0 cases because so many part of the code try to check whether a type
is sized.

Thanks for the review from Nick Lewycky and Benjamin Kramer on IRC.

llvm-svn: 152197
2012-03-07 02:33:09 +00:00
Nick Lewycky 1d57ee341a No functionality change. Type::isSized() can be expensive, so avoid calling it
until after other inexpensive tests.

llvm-svn: 152195
2012-03-07 02:27:53 +00:00
Jim Grosbach eadd8ee49c ARM pre-v6 assembly parsing for umull/smull.
llvm-svn: 152188
2012-03-07 01:09:17 +00:00
Jim Grosbach 8db462042c ARM pre-v6 alias for 'nop' to 'mov r0, r0'
llvm-svn: 152185
2012-03-07 00:52:41 +00:00
Jim Grosbach eed9992b26 Tidy up. Remove dead code that slipped into previous commit.
llvm-svn: 152184
2012-03-07 00:52:39 +00:00
Andrew Trick edbb3b2231 Added -view-background to avoid waiting for each GraphViz invocation.
GV and XDOT paths are untested but should work the same.

llvm-svn: 152179
2012-03-07 00:18:27 +00:00
Andrew Trick a5f19560fb Added -view-misched=dags options.
llvm-svn: 152178
2012-03-07 00:18:25 +00:00
Andrew Trick 1b2324d0e8 Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.

llvm-svn: 152177
2012-03-07 00:18:22 +00:00
Andrew Trick 320c7030db Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics.
llvm-svn: 152176
2012-03-07 00:18:18 +00:00
Andrew Trick 5297d8df99 whitespace
llvm-svn: 152175
2012-03-07 00:18:15 +00:00
Andrew Trick 0c84efe8dd Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
llvm-svn: 152174
2012-03-07 00:18:12 +00:00
Andrew Trick 3222c0985b misched comments
llvm-svn: 152173
2012-03-07 00:18:08 +00:00
Andrew Trick 3b6eb1e5ea misched: Use the StartBlock/FinishBlock hooks
llvm-svn: 152172
2012-03-07 00:18:05 +00:00
Eric Christopher 54cf8ff45e Add the DW_AT_APPLE_runtime_class attribute to forward declarations
as well as completely defined classes.

This fixes rdar://10956070

llvm-svn: 152171
2012-03-07 00:15:19 +00:00
Evan Cheng 80893ce5f5 Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
llvm-svn: 152162
2012-03-06 23:33:32 +00:00
Jim Grosbach ed428bc1ce ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.

llvm-svn: 152157
2012-03-06 23:10:38 +00:00
Jakob Stoklund Olesen 936656ba2f Hoist common code out of if statement.
llvm-svn: 152153
2012-03-06 22:27:13 +00:00
Jim Grosbach 13a292cc74 ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
2012-03-06 22:01:44 +00:00
Benjamin Kramer e1c34e9f43 SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap.
This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.

llvm-svn: 152143
2012-03-06 20:40:02 +00:00
Eli Friedman de850676e0 Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.
llvm-svn: 152136
2012-03-06 19:58:46 +00:00
Jim Grosbach 63ee881cd6 Tidy up. Kill some dead code.
llvm-svn: 152131
2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen 579e701fd9 Allow the same types in DPair as in QPR.
llvm-svn: 152129
2012-03-06 18:44:11 +00:00
Kevin Enderby 520eb3ba8a Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
llvm-svn: 152127
2012-03-06 18:33:12 +00:00