1a72add615
Compute feature bits at time of MCSubtargetInfo initialization.
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llvm-svn: 134606
2011-07-07 07:07:08 +00:00
c9c090d7a5
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
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llvm-svn: 134281
2011-07-01 22:36:09 +00:00
0d639a28aa
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
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llvm-svn: 134259
2011-07-01 21:01:15 +00:00
54b68e3432
- Added MCSubtargetInfo to capture subtarget features and scheduling
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itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
llvm-svn: 134257
2011-07-01 20:45:01 +00:00
703a0fbf39
Hide the call to InitMCInstrInfo into tblgen generated ctor.
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llvm-svn: 134244
2011-07-01 17:57:27 +00:00
fe6e405e8c
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
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be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
llvm-svn: 134127
2011-06-30 01:53:36 +00:00
16cde8ad36
Make sure we use the correct register class here since we'll need to
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care about spill values.
llvm-svn: 134122
2011-06-30 01:05:46 +00:00
03e756b93b
Remove todo.
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llvm-svn: 134094
2011-06-29 21:05:54 +00:00
e449141788
Add a TODO for the Alpha port inline asm constraints.
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llvm-svn: 134089
2011-06-29 19:41:27 +00:00
372a5c2a98
Move Alpha from getRegClassForInlineAsmConstraint to
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getRegForInlineAsmConstraint.
Part of rdar://9643582
llvm-svn: 134088
2011-06-29 19:40:01 +00:00
8264e272a9
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
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llvm-svn: 134049
2011-06-29 01:14:12 +00:00
194c3dc01f
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
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llvm-svn: 134030
2011-06-28 21:14:33 +00:00
0beca53a29
Hide more details in tablegen generated MCRegisterInfo ctor function.
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llvm-svn: 134027
2011-06-28 20:44:22 +00:00
1e210d08d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
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llvm-svn: 134024
2011-06-28 20:07:07 +00:00
d9997acd14
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
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into XXXGenRegisterInfo.inc.
llvm-svn: 133922
2011-06-27 18:32:37 +00:00
247533179a
Starting to refactor Target to separate out code that's needed to fully describe
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target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
llvm-svn: 133782
2011-06-24 01:44:41 +00:00
99f35eab45
Use set operations instead of plain lists to enumerate register classes.
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This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
llvm-svn: 133105
2011-06-15 23:28:14 +00:00
5750ca7089
Remove custom allocation order boilerplate that is no longer needed.
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The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
llvm-svn: 132781
2011-06-09 16:56:59 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
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No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
08600bcf65
Use the dwarf->llvm mapping to print register names in the cfi
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directives.
Fixes PR9826.
llvm-svn: 132317
2011-05-30 20:20:15 +00:00
8b2e426555
Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.
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llvm-svn: 131587
2011-05-18 21:54:32 +00:00
2518f8376d
Make the logic for determining function alignment more explicit. No functionality change.
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llvm-svn: 131012
2011-05-06 20:34:06 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
b2c80da4ae
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
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llvm-svn: 126518
2011-02-25 21:41:48 +00:00
ba1186c23e
Use explicit add_subdirectory's for LLVM target sublibraries instead
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of testing for its presence at cmake time.
This way the build automatically regenerates the makefiles when a svn
update brings in a new sublibrary.
llvm-svn: 126068
2011-02-20 02:55:27 +00:00
81c4306005
Swap VT and DebugLoc operands of getExtLoad() for consistency with
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other getNode() methods. Radar 9002173.
llvm-svn: 125665
2011-02-16 16:23:55 +00:00
4bc5e38960
Teach frame lowering to ignore debug values after the terminators.
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llvm-svn: 123399
2011-01-13 21:28:52 +00:00
441ae5b88c
Update CMake stuff
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llvm-svn: 123171
2011-01-10 12:39:23 +00:00
2f93128109
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
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llvm-svn: 123170
2011-01-10 12:39:04 +00:00
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
3e5fbd74ed
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
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something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
2010-12-21 02:38:05 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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llvm-svn: 119990
2010-11-23 03:31:01 +00:00
0eecf5d201
Move hasFP() and few related hooks to TargetFrameInfo.
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llvm-svn: 119740
2010-11-18 21:19:35 +00:00
51d2e9ca29
Attempt to unbreak cmake-based builds
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llvm-svn: 119098
2010-11-15 00:48:12 +00:00
f7183edb59
First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place
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llvm-svn: 119097
2010-11-15 00:06:54 +00:00
66031ed839
move all the target's asmprinters into the main target. The piece
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that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.
llvm-svn: 119056
2010-11-14 18:43:56 +00:00
dab307c6f4
fix cmake
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llvm-svn: 119053
2010-11-14 18:27:11 +00:00
9007c368c6
remove JIT support from the Alpha backend. The JIT will be moving to MC,
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and the Alpha backend isn't MCized yet. Approved by Andrew.
llvm-svn: 119051
2010-11-14 18:24:41 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
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llvm-svn: 117667
2010-10-29 17:29:13 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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llvm-svn: 116018
2010-10-08 00:21:28 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
b4b12535e8
Removed a bunch of unnecessary target_link_libraries.
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llvm-svn: 114999
2010-09-28 22:39:14 +00:00
676c61db0e
update a bunch of code to use the MachinePointerInfo version of getStore.
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llvm-svn: 114461
2010-09-21 18:41:36 +00:00
6963c1f789
eliminate an old SelectionDAG::getTruncStore method, propagating
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MachinePointerInfo around more.
llvm-svn: 114452
2010-09-21 17:42:31 +00:00
3d178ed4d4
propagate MachinePointerInfo through various uses of the old
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SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
2010-09-21 17:04:51 +00:00
7727d05dbb
convert the targets off the non-MachinePointerInfo of getLoad.
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llvm-svn: 114410
2010-09-21 06:44:06 +00:00
018f965a77
AlphaSchedule.td: 7bit-ize.
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llvm-svn: 114173
2010-09-17 09:56:43 +00:00
65b48b5dfc
zap dead code.
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llvm-svn: 113073
2010-09-04 18:12:00 +00:00
6a77066913
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
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to try to re-use scavenged frame index reference registers. rdar://8277890
llvm-svn: 112241
2010-08-26 23:32:16 +00:00
2edfdd289f
remove some dead code.
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llvm-svn: 111345
2010-08-18 02:42:11 +00:00
Evan Cheng