Commit Graph

14 Commits

Author SHA1 Message Date
David Blaikie b3bde2ea50 Fix a bunch more layering of CodeGen headers that are in Target
All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

llvm-svn: 318490
2017-11-17 01:07:10 +00:00
Dylan McKay f9e291a2f6 [AVR] Implement getCmpLibcallReturnType().
This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code.
By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit.

Patch By Thomas Backman.

llvm-svn: 314070
2017-09-24 01:07:26 +00:00
Jonas Paulsson 024e319489 [SystemZ, LoopStrengthReduce]
This patch makes LSR generate better code for SystemZ in the cases of memory
intrinsics, Load->Store pairs or comparison of immediate with memory.

In order to achieve this, the following common code changes were made:

 * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if
 LSR should do instruction-based addressing evaluations by calling
 isLegalAddressingMode() with the Instruction pointers.
 * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy
 as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address,
 not just loads or stores.

SystemZ changes:

 * isLSRCostLess() implemented with Insns first, and without ImmCost.
 * New function supportedAddressingMode() that is a helper for TTI methods
 looking at Instructions passed via pointers.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D35262
https://reviews.llvm.org/D35049

llvm-svn: 308729
2017-07-21 11:59:37 +00:00
Dylan McKay 59e7fe3da8 [AVR] Implement non-constant bit rotations
This lets us do bit rotations of variable amount.

llvm-svn: 301794
2017-05-01 09:48:55 +00:00
Dylan McKay 8fa6d8db9c [AVR] Implement TargetLoweing::getRegisterByName
This allows the use of the 'read_register' intrinsics used by clang's
named register globals features.

llvm-svn: 291375
2017-01-07 23:39:47 +00:00
Dylan McKay a1a944e3cb [AVR] Use references rather than pointers in AVRISelLowering
llvm-svn: 283636
2016-10-08 01:06:21 +00:00
Dylan McKay 12109e7314 Allow a maximum of 64 bits to be returned in registers
The rest spills to the stack

Authored by Jake Goulding

llvm-svn: 283635
2016-10-08 01:05:09 +00:00
Dylan McKay c1ff65cf62 [AVR] Expand MULHS for all types
Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.

Authored by Jake Goulding

llvm-svn: 283634
2016-10-08 01:01:49 +00:00
Dylan McKay 7e91886a3f Revert "[AVR] Add instruction selection lowering code"
I accidentally comitted it.

llvm-svn: 282712
2016-09-29 12:49:18 +00:00
Dylan McKay b79c01a423 [AVR] Add instruction selection lowering code
Summary: This adds AVRISelLowering.cpp

Reviewers: kparzysz, arsenm

Subscribers: wdng, beanz, mgorny

Differential Revision: https://reviews.llvm.org/D25034

llvm-svn: 282711
2016-09-29 12:44:38 +00:00
Duncan P. N. Exon Smith e4f5e4f4d1 CodeGen: Use MachineInstr& in TargetLowering, NFC
This is a mechanical change to make TargetLowering API take MachineInstr&
(instead of MachineInstr*), since the argument is expected to be a valid
MachineInstr.  In one case, changed a parameter from MachineInstr* to
MachineBasicBlock::iterator, since it was used as an insertion point.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

llvm-svn: 274287
2016-06-30 22:52:52 +00:00
Benjamin Kramer bdc4956bac Pass DebugLoc and SDLoc by const ref.
This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.

llvm-svn: 272512
2016-06-12 15:39:02 +00:00
Dylan McKay f830f4baa5 [AVR] Remove the 'AVRConfig.h' header
It defined the LLVM_AVR_GCC_COMPAT constant, which would enable/disable
certain GCC-specific behaviours.

There is no point conditionally turning it on/off, as it will always be
turned on, and we have to maintain both code paths anyway.

llvm-svn: 269904
2016-05-18 11:20:48 +00:00
Dylan McKay 6d8078f993 [AVR] Add a majority of the backend code
Summary: This adds the majority of the AVR backend.

Reviewers: hfinkel, dsanders, vkalintiris, arsenm

Subscribers: dylanmckay

Differential Revision: http://reviews.llvm.org/D17906

llvm-svn: 268722
2016-05-06 10:12:31 +00:00