Commit Graph

16 Commits

Author SHA1 Message Date
Chandler Carruth 2946cd7010 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
2019-01-19 08:50:56 +00:00
Krzysztof Parzyszek e3ef6e0706 [Hexagon] Memoize instruction positions in BitTracker
llvm-svn: 324250
2018-02-05 17:12:07 +00:00
Benjamin Kramer 45aa89eb7f BitTracker.h needs a full definition of MachineInstr, so include the defining file.
Patch by Dean Sturtevant!

Differential Revision: https://reviews.llvm.org/D42907

llvm-svn: 324245
2018-02-05 15:56:24 +00:00
Krzysztof Parzyszek 058d3cec15 [Hexagon] Remove recursion in visitUsesOf, replace with use queue
This is primarily to reduce stack usage, but ordering the use queue
according to the position in the code (earlier instructions visited
before later ones) reduces the number of unnecessary bottoms due to
visiting instructions out of order, e.g.
  %reg1 = copy %reg0
  %reg2 = copy %reg0
  %reg3 = and %reg1, %reg2
Here, reg3 should be known to be same as reg0-2, but if reg3 is
evaluated after reg1 is updated, but before reg2 is updated, the two
inputs to the and will appear different, causing reg3 to become
bottom.

llvm-svn: 320866
2017-12-15 21:34:05 +00:00
Krzysztof Parzyszek 7e604deca9 [Hexagon] Better determination of register classes in bit tracker
Add two callbacks to MachineEvaluator, so that specific implementations
can specify more details about register classes:
- composeWithSubRegIndex(RC,Idx), to provide the register class for a
  register from RC used in conjunction with a subregister index Idx.
- getPhysRegBitWidth(Reg), to provide the size in bits of the given
  physical register.

llvm-svn: 314136
2017-09-25 19:12:55 +00:00
Eugene Zelenko e4fc6ee790 [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309230
2017-07-26 23:20:35 +00:00
Krzysztof Parzyszek 5bfaf56ee5 [Hexagon] Cache reached blocks in bit tracker instead of scanning list
llvm-svn: 300701
2017-04-19 15:08:31 +00:00
Krzysztof Parzyszek 998e49e5c8 [Hexagon] Allow setting register in BitVal without storing into map
In the bit tracker, references to other bit values in which the register
is 0 are prohibited. This means that generating self-referential register
cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order
to get a self-referential cell, it had to be stored into a map and then
reloaded from it. To avoid this step, add a function that will set the
register to a given value without going through the map.

llvm-svn: 296025
2017-02-23 22:08:50 +00:00
Eugene Zelenko b2ca1b3f37 [Hexagon, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 290925
2017-01-04 02:02:05 +00:00
Krzysztof Parzyszek 623afbdbd7 [Hexagon-ish] Add function to print cell map contents in bit tracker
llvm-svn: 277622
2016-08-03 18:13:32 +00:00
Krzysztof Parzyszek 6eba5b8c37 [Hexagon] Rerun bit tracker on new instructions in RIE
Consider this case:
  vreg1 = A2_zxth vreg0   (1)
  ...
  vreg2 = A2_zxth vreg1   (2)

Redundant instruction elimination could delete the instruction (1)
because the user (2) only cares about the low 16 bits. Then it could
delete (2) because the input is already zero-extended. The problem
is that the properties allowing each individual instruction to be
deleted depend on the existence of the other instruction, so either
one can be deleted, but not both.
The existing check for this situation in RIE was insufficient. The
fix is to update all dependent cells when an instruction is removed
(replaced via COPY) in RIE.

llvm-svn: 276792
2016-07-26 19:08:45 +00:00
Duncan P. N. Exon Smith 98226e3d93 Hexagon: Avoid implicit iterator conversions, NFC
Avoid implicit iterator conversions from MachineInstrBundleIterator to
MachineInstr* in the Hexagon backend, mostly by preferring MachineInstr&
over MachineInstr* and switching to range-based for loops.

There's a long tail of API cleanup here, but I'm planning to leave the
rest to the Hexagon maintainers.  HexagonInstrInfo defines many of its
own predicates, and most of them still take MachineInstr*.  Some of
those actually check for nullptr, so I didn't feel comfortable changing
them to MachineInstr& en masse.

llvm-svn: 275142
2016-07-12 01:55:32 +00:00
David Blaikie 78633802c2 -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11
Remove some unnecessary explicit special members in Hexagon that, once
removed, allow the other implicit special members to be used without
depending on deprecated features.

llvm-svn: 243825
2015-08-01 05:31:27 +00:00
Benjamin Kramer 9a5d788948 [Hexagon] Use composition instead of inheritance from STL types
The standard containers are not designed to be inherited from, as
illustrated by the MSVC hacks for NodeOrdering. No functional change
intended.

llvm-svn: 242616
2015-07-18 17:43:23 +00:00
Benjamin Kramer d8861517bf [Hexagon] Move BitTracker into the llvm namespace and remove redundant qualifications
No functional change intended.

llvm-svn: 242062
2015-07-13 20:38:16 +00:00
Krzysztof Parzyszek e53b31a593 [Hexagon] Implement bit-tracking facility with specifics for Hexagon
This includes code that is intended to be target-independent as well
as the Hexagon-specific details. This is just the framework without
any users.

llvm-svn: 241595
2015-07-07 15:16:42 +00:00