Commit Graph

160950 Commits

Author SHA1 Message Date
Alexey Bataev 625ce229b1 [SLP] Additional tests for stores vectorization, NFC.
llvm-svn: 326740
2018-03-05 20:20:12 +00:00
Daniel Sanders a09751e779 Re-commit: Make STATISTIC() values available programmatically
Summary:
It can be useful for tools to be able to retrieve the values of variables
declared via STATISTIC() directly without having to emit them and parse
them back. Use cases include:
* Needing to report specific statistics to a test harness
* Wanting to post-process statistics. For example, to produce a percentage of
  functions that were fully selected by GlobalISel

Make this possible by adding llvm::GetStatistics() which returns an
iterator_range that can be used to inspect the statistics that have been
touched during execution. When statistics are disabled (NDEBUG and not
LLVM_ENABLE_STATISTICS) this method will return an empty range.

This patch doesn't address the effect of multiple compilations within the same
process. In such situations, the statistics will be cumulative for all
compilations up to the GetStatistics() call.

Reviewers: qcolombet, rtereshin, aditya_nandakumar, bogner

Reviewed By: rtereshin, bogner

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D43901

This re-commit fixes a missing include of <vector> which it seems clang didn't
mind but G++ and MSVC objected to. It seems that, clang was ok with std::vector
only being forward declared at the point of use since it was fully defined
eventually but G++/MSVC both rejected it at the point of use.

llvm-svn: 326738
2018-03-05 19:38:16 +00:00
Dmitry Mikulin 430c7ff732 On Windows we need to be able to process response files with Windows-style
path names.

Differential Revision: https://reviews.llvm.org/D43988

llvm-svn: 326737
2018-03-05 19:34:33 +00:00
Nemanja Ivanovic 6cc31ca814 [PowerPC] Do not emit record-form rotates when record-form andi suffices
Up until Power9, the performance profile for rlwinm., rldicl. and andi. looked
more or less equivalent. However with Power9, the rotates are still 2-way
cracked whereas the and-immediate is not.

This patch just ensures that we don't emit record-form rotates when an andi.
is adequate.

As first pointed out by Carrot in https://bugs.llvm.org/show_bug.cgi?id=30833
(this patch is a fix for that PR).

Differential Revision: https://reviews.llvm.org/D43977

llvm-svn: 326736
2018-03-05 19:27:16 +00:00
Sanjay Patel 77ae82b84a [x86] auto-generate full checks for fabs tests
Also, change the x86-64 test to optimized and remove the 
unnecessary platform specification from the RUN lines..

llvm-svn: 326735
2018-03-05 19:11:20 +00:00
Dmitry Mikulin 0faf7c8de2 On Windows expansion of regex file name patterns is the responsibility of each
tool. Fix ar to do that.

Differential Revision: https://reviews.llvm.org/D43987

llvm-svn: 326734
2018-03-05 18:54:56 +00:00
Eric Liu 47f42c2167 Fix an unused variable warning introduced by rr326703. NFC
llvm-svn: 326732
2018-03-05 18:36:39 +00:00
Aaron Smith 5ab08cfd23 [llvm-pdbdump] Dump restrict type qualifier
Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: majnemer

Differential Revision: https://reviews.llvm.org/D43639

llvm-svn: 326731
2018-03-05 18:29:43 +00:00
Daniel Neilson bdda115e19 [InstCombine] Don't blow up in foldICmpWithCastAndCast on vector icmp instructions.
Summary:
Presently, InstCombiner::foldICmpWithCastAndCast() implicitly assumes that it is
only invoked with icmp instructions of integer type. If that assumption is broken,
and it is called with an icmp of vector type, then it fails (asserts/crashes).

This patch addresses the deficiency. It allows it to simplify
icmp (ptrtoint x), (ptrtoint/c) of vector type into a compare of the inputs,
much as is done when the type is integer.

Reviewers: apilipenko, fedor.sergeev, mkazantsev, anna

Reviewed By: anna

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44063

llvm-svn: 326730
2018-03-05 18:05:51 +00:00
Craig Topper 8452faceae [InstCombine] Add constant vector support to getMinimumFPType for visitFPTrunc.
This patch teaches getMinimumFPType to support shrinking a vector of ConstantFPs. This should improve our ability to combine vector fptrunc with fp binops.

Differential Revision: https://reviews.llvm.org/D43774

llvm-svn: 326729
2018-03-05 18:04:12 +00:00
Daniel Sanders 7612f85df5 Revert r326723: Make STATISTIC() values available programmatically
Despite building cleanly on my machine in three separate configs, it's failing on pretty much all bots due to missing includes among other things. Investigating.

llvm-svn: 326726
2018-03-05 17:52:43 +00:00
Evandro Menezes f29e35afff [AArch64] Harden test case
NFC

llvm-svn: 326724
2018-03-05 17:42:18 +00:00
Daniel Sanders edcf110b23 Make STATISTIC() values available programmatically
Summary:
It can be useful for tools to be able to retrieve the values of variables
declared via STATISTIC() directly without having to emit them and parse
them back. Use cases include:
* Needing to report specific statistics to a test harness
* Wanting to post-process statistics. For example, to produce a percentage of
  functions that were fully selected by GlobalISel

Make this possible by adding llvm::GetStatistics() which returns an
iterator_range that can be used to inspect the statistics that have been
touched during execution. When statistics are disabled (NDEBUG and not
LLVM_ENABLE_STATISTICS) this method will return an empty range.

This patch doesn't address the effect of multiple compilations within the same
process. In such situations, the statistics will be cumulative for all
compilations up to the GetStatistics() call.

Reviewers: qcolombet, rtereshin, aditya_nandakumar, bogner

Reviewed By: rtereshin, bogner

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D43901

llvm-svn: 326723
2018-03-05 17:41:45 +00:00
Sebastian Pop ac0bfb5938 fix PR36582
The error occurs when reading i16 elements (as in the testcase) from a v8i8
with a pattern of <0,2,4,6>. As all the data in the vector is accessed, the
operation is not a VUZP. The patch stops the pattern recognition of VUZP when
EXTRACT_VECTOR_ELT has a different element type than BUILD_VECTOR.

llvm-svn: 326722
2018-03-05 17:35:49 +00:00
Florian Hahn 0b7c6422fb [IPSCCP] Add getCompare which returns either true, false, undef or null.
getCompare returns true, false or undef constants if the comparison can
be evaluated, or nullptr if it cannot. This is in line with what
ConstantExpr::getCompare returns. It also allows us to use
ConstantExpr::getCompare for comparing constants.

Reviewers: davide, mssimpso, dberlin, anna

Reviewed By: davide

Differential Revision: https://reviews.llvm.org/D43761

llvm-svn: 326720
2018-03-05 17:33:50 +00:00
Evandro Menezes cd855f70c5 [AArch64] Improve code generation of constant vectors
Use the whole gammut of constant immediates available to set up a vector.
Instead of using, for example, `mov w0, #0xffff; dup v0.4s, w0`, which
transfers between register files, use the more efficient `movi v0.4s, #-1`
instead.  Not limited to just a few values, but any immediate value that can
be encoded by all the variants of `FMOV`, `MOVI`, `MVNI`, thus eliminating
the need to there be patterns to optimize special cases.

Differential revision: https://reviews.llvm.org/D42133

llvm-svn: 326718
2018-03-05 17:02:47 +00:00
Jonas Paulsson bc32f7db85 [MachineScheduler] Dump SUnits before calling SchedImpl->initialize()
This is a NFC simple patch that changes the DEBUG dumping in the
MachineScheduler so that the dumping of the built SUnits is done before the
SchedImpl->initialize() is called.

This is better on SystemZ, since it has a strategy that does some dumping at
the start of the region, and it is not possible to easily read it if it is
output above a long list of SU.

Review: Javed Absar
https://reviews.llvm.org/D44089

llvm-svn: 326716
2018-03-05 16:31:49 +00:00
Matt Arsenault e31ab94e97 AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACT
llvm-svn: 326715
2018-03-05 16:25:18 +00:00
Matt Arsenault 71272e6d4e AMDGPU/GlobalISel: Make some G_EXTRACTs legal
As far as I can tell legalization of weird sizes for the
output type isn't implemented.

llvm-svn: 326714
2018-03-05 16:25:15 +00:00
Matt Arsenault 4cc0b85276 AMDGPU: Fix build warning about override
llvm-svn: 326713
2018-03-05 16:25:10 +00:00
Sanjay Patel 53ffabdfcb [CVP] fix formatting; NFC
llvm-svn: 326711
2018-03-05 16:08:34 +00:00
Tim Northover 24c296de77 Fuzzer: remove temporary files after we're done with them.
These were just copies of the relevant fuzzer binary with (presumably)
meaningful suffixes, but accounted for more than 10% of my build
directory (> 8GB). Hard drive space is cheap, but not that cheap.

llvm-svn: 326710
2018-03-05 15:49:00 +00:00
Nicolai Haehnle 7d697857cd TableGen: Resolve all template args simultaneously in ResolveMulticlassDefARgs
Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Change-Id: I679e86988b309d19f25e6cca8b0b14ea150198a6

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43654

llvm-svn: 326708
2018-03-05 15:21:19 +00:00
Nicolai Haehnle 1faf8689d7 TableGen: Resolve all template args simultaneously in AddSubMultiClass
Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Change-Id: Ia4dcc6d42dd8b65e6079d318c6a202f36f320fee

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43653

llvm-svn: 326707
2018-03-05 15:21:15 +00:00
Nicolai Haehnle b0cf9e93a6 TableGen: Resolve all template args simultaneously in AddSubClass
Summary:
Use the new resolver interface more explicitly, and avoid traversing
all the initializers multiple times.

Add a test case for a pattern that was broken by an earlier version
of this change.

An additional change is that we now remove *all* template arguments
after resolving them.

Change-Id: I86c828c8cc84c18b052dfe0f64c0d5cbf3c4e13c

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43652

llvm-svn: 326706
2018-03-05 15:21:11 +00:00
Nicolai Haehnle 8ebf7e4dfa TableGen: Reimplement !foreach using the resolving mechanism
Summary:
This changes the syntax of !foreach so that the first "parameter" is
a new syntactic variable: !foreach(x, lst, expr) will define the
variable x within the scope of expr, and evaluation of the !foreach
will substitute elements of the given list (or dag) for x in expr.

Aside from leading to a nicer syntax, this allows more complex
expressions where x is deeply nested, or even constant expressions
in which x does not occur at all.

!foreach is currently not actually used anywhere in trunk, but I
plan to use it in the AMDGPU backend. If out-of-tree targets are
using it, they can adjust to the new syntax very easily.

Change-Id: Ib966694d8ab6542279d6bc358b6f4d767945a805

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits, tpr

Differential Revision: https://reviews.llvm.org/D43651

llvm-svn: 326705
2018-03-05 15:21:04 +00:00
Nicolai Haehnle 0b0eaf7ee2 TableGen: Introduce an abstract variable resolver interface
Summary:
The intention is to allow us to more easily restructure how resolving is
done, e.g. resolving multiple variables simultaneously, or using the
resolving mechanism to implement !foreach.

Change-Id: I4b976b54a32e240ad4f562f7eb86a4d663a20ea8

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43564

llvm-svn: 326704
2018-03-05 15:20:51 +00:00
Alexander Timofeev 2e5eeceeb7 Pass Divergence Analysis data to Selection DAG to drive divergence
dependent instruction selection.

Differential revision: https://reviews.llvm.org/D35267

llvm-svn: 326703
2018-03-05 15:12:21 +00:00
Stefan Pintilie d45db612c6 [Power9] Add more missing instructions to the Power 9 scheduler
Adding more instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.

llvm-svn: 326701
2018-03-05 14:34:59 +00:00
Nicolai Haehnle 3c80e4c514 TableGen: Allow NAME in template arguments in defm in multiclass
Summary:
NAME has already worked for def in a multiclass, since the (protoype)
record including its NAME variable is created before parsing the
superclasses. Since defm's do not have an associated single record,
support for NAME has to be implemented differently here.

Original test cases provided by Artem Belevich (tra)

Change-Id: I933b74f328c0ff202e7dc23a35b78f3505760cc9

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43656

llvm-svn: 326700
2018-03-05 14:01:38 +00:00
Nicolai Haehnle 0409b28af1 TableGen: Use DefInit::getDef() instead of the type's getRecord()
The former simply makes more sense: we want to access the data here in
the backend, not information about the type.

More importantly, removing users of RecordRecTy::getRecord() allows us
more freedom to refactor the frontend.

Change-Id: Iee8905fd22cdb9b11c42ca03246c03d8fe4dd77f
llvm-svn: 326699
2018-03-05 14:01:30 +00:00
Xin Tong 8345c0e3a5 [MergeICmp] We can discard initial blocks that do other work
Summary:
 We can discard initial blocks that do other work
We do not need to limit ourselves to just the first block in the chain.

Reviewers: courbet, davide

Reviewed By: courbet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44029

llvm-svn: 326698
2018-03-05 13:54:47 +00:00
Nicholas Wilson b3748f71df [WebAssembly] Add validation to reloc section
We now check relocations offsets are within range, and the relocation
index is valid.

Also updated tests which contained invalid Wasm files that were
previously not checked.

Differential Revision: https://reviews.llvm.org/D43684

llvm-svn: 326697
2018-03-05 13:32:38 +00:00
Oliver Stannard f20222a83c [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers
These instructions require that the two S registers are adjacent (but not the R
registers), because only the first register is included in the encoding, but we
were not checking this in the assembler.

Differential revision: https://reviews.llvm.org/D44084

llvm-svn: 326696
2018-03-05 13:27:26 +00:00
Nicholas Wilson c22bfb6b4b [WebAssembly] Reorder reloc sections to come between symtab and name
This is required in order to enable relocs to be validated
as they are read in.

Also update tests with new section ordering.

Differential Revision: https://reviews.llvm.org/D43940

llvm-svn: 326694
2018-03-05 12:59:03 +00:00
Nicholas Wilson 6705c00f4d [WebAssembly] Fix tests with invalid yaml (required CODE section missing)
Differential Revision: https://reviews.llvm.org/D44023

llvm-svn: 326692
2018-03-05 12:28:01 +00:00
Nicholas Wilson 959e737118 [WebAssembly] Attach a name to globals similarly to function naming
This allows LLD to print the name for an InputGlobal when encountering
an error.

Differential Revision: https://reviews.llvm.org/D44033

llvm-svn: 326691
2018-03-05 12:16:32 +00:00
Thomas Preud'homme c699eaa311 Fix location of comment in EmitPopInst
Comment about folding return in LDM was not moved along with the
corresponding code in r242714. This commit fixes that.

llvm-svn: 326690
2018-03-05 11:49:00 +00:00
Yuka Takahashi 41789e46a6 [Bash-autocompletion] Pass all flags in shell command-line to Clang
Previously, we passed "#" to --autocomplete to indicate to enable cc1
flags. For example, when -cc1 or -Xclang was passed to bash, bash
executed `clang --autocomplete=#-<flag they want to complete>`.

However, this was not a good implementation because it depends -Xclang
and -cc1 parsing to shell. So I changed this to pass all flags shell
has, so that Clang can handle them internally.

I had to change many testcases because API spec changed quite a lot.

Reviewers: teemperor, v.g.vassilev

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D39342

llvm-svn: 326684
2018-03-05 08:54:20 +00:00
Clement Courbet 34be1b0288 [MergeICmps][NFC] Improve logging.
llvm-svn: 326683
2018-03-05 08:21:47 +00:00
Craig Topper f546b2c06f [X86] Replace usages of X86Subtarget::hasFp256 with hasAVX. Remove hasFP256.
Almost none of these usages were FP specific. And we had no clear guideliness on when to use hasAVX vs hasFP256.

I might also remove hasInt256 too since its an alias for hasAVX2.

llvm-svn: 326682
2018-03-05 00:13:35 +00:00
Craig Topper f2aae62228 [X86] Add a DAG combine to turn stores of vXi1 constants into scalar stores.
llvm-svn: 326679
2018-03-04 19:33:15 +00:00
Craig Topper 1209eb7d66 [X86] Add a 32-bit mode command line to avx512-mask-op.ll. Add tests for storing v2i1 and v4i1 constants.
llvm-svn: 326678
2018-03-04 19:33:13 +00:00
Craig Topper 4196dd12a2 [DAGCombiner] Add a peekThroughBitcast to MergeStoresOfConstantsOrVecElts to fix a crash if we are storing a bitcast of a constant.
Loading a constant into a k-register in AVX512 requires a bitcast from a scalar constant. In the test case here we have a k-register store that gets split into multiple parts of KNL. MergeConsecutiveStores sees each of these pieces as a consecutive store and looks through the bitcast to find the underly scalar constant. But when we went to create the combined store we didn't look through the same bitcast.

llvm-svn: 326677
2018-03-04 18:51:46 +00:00
Simon Pilgrim 8197b04b9b [X86][X87] Add X87 folded integer arithmetic tests
Add tests for FIADD/FISUB/FISUBR/FIMUL/FIDIV/FIDIVR

Shows we have more FILD stack usage than necessary (arg load, spill, reload to x87)

llvm-svn: 326674
2018-03-04 15:00:19 +00:00
Simon Pilgrim 3a76bc29d7 [X86][MMX] Remove completed _mm_cvtsi32_si64 todo
rL322525 - mmx zero constant support
rL322553 - mmx i32 zero extended value
rL326497 - mmx i64 general constant handling

Not all constants are folded, we generate some on the GPRs (similar to SSE build vector) where appropriate

llvm-svn: 326673
2018-03-04 14:57:26 +00:00
Craig Topper 12c35e1940 [X86] Fix unused variable in release builds.
llvm-svn: 326672
2018-03-04 02:14:16 +00:00
Craig Topper a476026f70 [X86] Combine (store (v1i1 (scalar_to_vector (i8 X)))) -> (store (i8 X)).
llvm-svn: 326670
2018-03-04 01:48:02 +00:00
Craig Topper be31585be8 [X86] Lower v1i1/v2i1/v4i1/v8i1 load/stores to i8 load/store during op legalization if AVX512DQ is not supported.
We were previously doing this with isel patterns. Moving it to op legalization gives us chance to see the required bitcast earlier. And it lets us remove some isel patterns.

llvm-svn: 326669
2018-03-04 01:48:00 +00:00
Fedor Indutny 364b9c2adb [CallSiteSplitting] fix use after-free
Iterating through predecessors of `TailBB` while removing their
terminators leads to use after-free, because the predecessor list is
changing on each removal.

llvm-svn: 326668
2018-03-03 22:34:38 +00:00