4 Commits

Author	SHA1	Message	Date
Silviu Baranga	755ec0e027	[AArch64] Turn on by default interleaved access vectorization ... Summary: This change turns on by default interleaved access vectorization for AArch64. We also clean up some tests which were spedifically enabling this behaviour. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12149 llvm-svn: 246542	2015-09-01 11:26:46 +00:00
Silviu Baranga	de38070587	The tests added in r243270 require asserts to be enabled ... llvm-svn: 243274	2015-07-27 15:22:49 +00:00
Silviu Baranga	65bdb6788b	Fix the tests added in r243270. Use 2>&1 instead of |& ... llvm-svn: 243273	2015-07-27 15:08:55 +00:00
Silviu Baranga	7581d22512	[ARM/AArch64] Fix cost model for interleaved accesses ... Summary: Fix the cost of interleaved accesses for ARM/AArch64. We were calling getTypeAllocSize and using it to check the number of bits, when we should have called getTypeAllocSizeInBits instead. This would pottentially cause the vectorizer to generate loads/stores and shuffles which cannot be matched with an interleaved access instruction. No performance changes are expected for now since matching/generating interleaved accesses is still disabled by default. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11524 llvm-svn: 243270	2015-07-27 14:39:34 +00:00