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Author SHA1 Message Date
Igor Breger 7b46b4e798 AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. 
Differential Revision: http://reviews.llvm.org/D15713

llvm-svn: 256324
 2015-12-23 08:06:50 +00:00
James Y Knight 7c905063c5 Make utils/update_llc_test_checks.py note that the assertions are 
autogenerated.

Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.

llvm-svn: 253917
 2015-11-23 21:33:58 +00:00
Simon Pilgrim b38c09d7ff [X86][AVX512] Added 512-bit vector shift tests. 
Only works for avx512f (dq) targets so far - need to add avx512bw tests once char/short shifts are supported.

llvm-svn: 246943
 2015-09-06 13:36:32 +00:00