cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
...
llvm-svn: 86628
2009-11-10 00:15:47 +00:00
a951526510
Remove an unneeded #include.
...
llvm-svn: 86601
2009-11-09 22:28:30 +00:00
f04c4cdb27
Fix for 64-bit builds.
...
llvm-svn: 86600
2009-11-09 22:28:21 +00:00
2745d19287
Print "..." instead of all the uninteresting register clobbers on call
...
instructions. This makes CodeGen dumps significantly less noisy.
Example before:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>
Same example after:
BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
llvm-svn: 86583
2009-11-09 19:38:45 +00:00
d2f9c044c0
Fix dependencies added to model memory aliasing for post-RA scheduling. The dependencies were overly conservative for memory access that are known not to alias.
...
llvm-svn: 86580
2009-11-09 19:22:17 +00:00
6f67f8902a
Constify MachineFunctionAnalysis' TargetMachine reference.
...
llvm-svn: 86564
2009-11-09 18:18:49 +00:00
ad7c6124e7
Hide a couple of options.
...
llvm-svn: 86522
2009-11-09 06:49:37 +00:00
ce29331e10
80 col.
...
llvm-svn: 86521
2009-11-09 06:49:22 +00:00
09eeeaf08b
Moved some ManagedStatics out of the SlotIndexes header.
...
llvm-svn: 86446
2009-11-08 08:49:59 +00:00
f93bb39b03
Add 8 bit libcalls and make use of them for msp430
...
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
8e1d7222a7
Fix PR5421 by APInt'izing switch lowering.
...
llvm-svn: 86354
2009-11-07 07:50:34 +00:00
bc247dce4d
Update some globals to use ManagedStatic.
...
llvm-svn: 86342
2009-11-07 05:50:28 +00:00
fc032ced22
Fix memoizing of CvtRndSatSDNode
...
llvm-svn: 86340
2009-11-07 04:46:25 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
07119737aa
Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
...
llvm-svn: 86324
2009-11-07 02:11:54 +00:00
4141d8ee92
Fix inverted conflict test in -early-coalesce.
...
A non-identity copy cannot be coalesced when the phi join destination register
is live at the copy site.
Also verify the condition that the PHI join source register is only used in
the PHI join. Otherwise the coalescing is invalid.
llvm-svn: 86322
2009-11-07 01:58:40 +00:00
b29e155c53
Fix comment typos.
...
llvm-svn: 86295
2009-11-06 22:38:38 +00:00
0080ee2d91
Use WriteAsOperand to print GlobalAddress MachineOperands. This
...
prints them with the leading '@'.
llvm-svn: 86261
2009-11-06 18:03:10 +00:00
cc11371b77
Do not bother to emit debug info for nameless global variable.
...
llvm-svn: 86259
2009-11-06 17:58:12 +00:00
06ce6506d2
Do not try to emit debug info entry for dead global variable.
...
llvm-svn: 86212
2009-11-06 01:30:04 +00:00
ee8afcc59d
Factor out the printing of the leading tab into printInlineAsm.
...
llvm-svn: 86199
2009-11-06 00:04:54 +00:00
d53b5cfe3f
Fix the label name generation for address-taken labels to avoid potential
...
problems with name collisions.
llvm-svn: 86189
2009-11-05 23:14:35 +00:00
933c541270
Added support for renumbering existing index list elements. Removed some junk from the initial numbering code in runOnMachineFunction.
...
llvm-svn: 86184
2009-11-05 22:20:57 +00:00
bed7cb6c1d
Fix bug in aggressive antidep breaking; liveness was not updated correctly for regions that do not have antidep candidates.
...
llvm-svn: 86172
2009-11-05 21:06:09 +00:00
43bdc260d6
Avoid printing a redundant space in SDNode->dump().
...
llvm-svn: 86151
2009-11-05 18:49:11 +00:00
542649463b
Replace std::map.at() with std::map[].
...
llvm-svn: 86102
2009-11-05 01:45:50 +00:00
7d8878add2
Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.
...
llvm-svn: 86098
2009-11-05 01:19:35 +00:00
66549b2818
Now that code placement optimization pass is run for JIT, make sure it's before pre-emit passes.
...
llvm-svn: 86092
2009-11-05 01:16:59 +00:00
921152fe9d
Code refactoring.
...
llvm-svn: 86085
2009-11-05 00:51:13 +00:00
28ba4f27d1
Correctly add chain dependencies around calls and unknown-side-effect instructions.
...
llvm-svn: 86080
2009-11-05 00:16:44 +00:00
f05d57283e
While calculating original type size for a derived type, handle type variants encoded as DIDerivedType appropriately.
...
This improves bitfield support.
llvm-svn: 86073
2009-11-04 23:48:00 +00:00
67f56f08c2
Fix DW_AT_data_member_location for bit-fields. It points to the location of annonymous field that covers respective field.
...
llvm-svn: 86054
2009-11-04 22:06:12 +00:00
289b8a2bd9
Handle empty/tombstone keys for LiveIndex more cleanly. Check for index sanity when constructing index list entries.
...
llvm-svn: 86049
2009-11-04 21:24:15 +00:00
9196f0c0e8
Add some options to disable various code gen optimizations.
...
llvm-svn: 86044
2009-11-04 19:57:50 +00:00
5d3fe2fc77
Array element size does not match array size but array is not a bitfield.
...
llvm-svn: 86043
2009-11-04 19:37:40 +00:00
c7cfc94bcc
Print out an informative comment for KILL instructions.
...
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
llvm-svn: 86041
2009-11-04 19:24:37 +00:00
95bdc5d899
RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
...
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.
llvm-svn: 86022
2009-11-04 08:33:14 +00:00
90790c7781
Fix CMake makefiles
...
llvm-svn: 85994
2009-11-04 01:32:06 +00:00
05fb9637f6
The Indexes Patch.
...
This introduces a new pass, SlotIndexes, which is responsible for numbering
instructions for register allocation (and other clients). SlotIndexes numbering
is designed to match the existing scheme, so this patch should not cause any
changes in the generated code.
For consistency, and to avoid naming confusion, LiveIndex has been renamed
SlotIndex.
The processImplicitDefs method of the LiveIntervals analysis has been moved
into its own pass so that it can be run prior to SlotIndexes. This was
necessary to match the existing numbering scheme.
llvm-svn: 85979
2009-11-03 23:52:08 +00:00
53a31ad3c1
Fix branch folding bug for indirect branches: for a block containing only
...
an unconditional branch (possibly from tail merging), this code is
trying to redirect all of its predecessors to go directly to the branch
target, but that isn't feasible for indirect branches. The other
predecessors (that don't end with indirect branches) could theoretically
still be handled, but that is not easily done right now.
The AnalyzeBranch interface doesn't currently let us distinguish jump table
branches from indirect branches, and this code is currently handling
jump tables. To avoid punting on address-taken blocks, we would have to give
up handling jump tables. That seems like a bad tradeoff.
llvm-svn: 85975
2009-11-03 23:44:31 +00:00
f42b5af549
Re-apply 85799. It turns out my code isn't buggy.
...
llvm-svn: 85947
2009-11-03 21:40:02 +00:00
8501dbbe10
Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.
...
llvm-svn: 85939
2009-11-03 20:57:50 +00:00
a86f919763
<rdar://problem/7352605>. When building schedule graph use mayAlias information to avoid chaining loads/stores of spill slots with non-aliased memory ops.
...
llvm-svn: 85934
2009-11-03 20:15:00 +00:00
ffa7c07352
Ignore unnamed variables.
...
llvm-svn: 85909
2009-11-03 18:30:27 +00:00
6235b19d7b
Fix a funky "declared with greater visibility than the type of its field"
...
warning from gcc by removing VISIBILITY_HIDDEN attributes.
llvm-svn: 85873
2009-11-03 06:29:36 +00:00
a8a58efc03
Revert 85799 for now. It might be breaking llvm-gcc driver.
...
llvm-svn: 85827
2009-11-02 21:49:14 +00:00
00822aabf6
Chain dependencies used to enforce memory order should have latency of 0 (except for true dependency of Store followed by aliased Load... we estimate that case with a single cycle of latency assuming the hardware will bypass)
...
llvm-svn: 85807
2009-11-02 17:06:28 +00:00
2729543984
Initilize the machine LICM CSE map upon the first time an instruction is hoisted to
...
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.
llvm-svn: 85799
2009-11-02 08:09:49 +00:00
ea68c7c9a8
Add PseudoSourceValue::mayAlias. It returns true if the object can ever alias any LLVM IR value.
...
llvm-svn: 85762
2009-11-01 23:50:04 +00:00
ae6bb61594
Fix a missing newline in the dwarf output code.
...
llvm-svn: 85684
2009-10-31 20:59:09 +00:00
34341e69c4
Make -print-machineinstrs more readable.
...
- Be consistent when referring to MachineBasicBlocks: BB#0.
- Be consistent when referring to virtual registers: %reg1024.
- Be consistent when referring to unknown physical registers: %physreg10.
- Be consistent when referring to known physical registers: %RAX
- Be consistent when referring to register 0: %reg0
- Be consistent when printing alignments: align=16
- Print jump table contents.
- Don't print host addresses, in general.
- and various other cleanups.
llvm-svn: 85682
2009-10-31 20:19:03 +00:00
18dc1c5c9e
Factor out more code into addCommonCodeGenPasses. The JIT wasn't
...
previously running CodePlacementOpt. Also print headers before
each dump in -print-machineinstrs mode, so that it's clear which
dump is which.
llvm-svn: 85681
2009-10-31 20:17:39 +00:00
fb7f0e57b6
Remove CodeGenLICM. It's largely obsoleted by MachineLICM's new ability
...
to unfold loop-invariant loads.
llvm-svn: 85657
2009-10-31 14:35:41 +00:00
ba8735d25a
When discarding SrcValue information, discard all of it so that code
...
that uses this information knows to behave conservatively.
llvm-svn: 85654
2009-10-31 14:14:04 +00:00
97abba5b6f
Fix 80-column violation.
...
llvm-svn: 85653
2009-10-31 14:12:53 +00:00
a0ca9e944f
Fix warning with gcc-4.0 and signed/unsigned.
...
llvm-svn: 85648
2009-10-31 09:24:35 +00:00
060ee82dab
Add assertion checks here to turn silent miscompiles into aborts.
...
llvm-svn: 85639
2009-10-30 23:59:06 +00:00
d814e32e57
Don't mark registers dead here when processing nodes with MVT::Flag
...
results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.
llvm-svn: 85638
2009-10-30 23:57:47 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
...
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
94966ca926
Stop the iterator in ValueLiveAt from potentially running off the end of the interval.
...
llvm-svn: 85599
2009-10-30 18:12:09 +00:00
64997909a6
Don't delete blocks which have their address taken.
...
llvm-svn: 85572
2009-10-30 02:13:27 +00:00
e0a8b8fc56
Mention if a block has its address taken in debug output.
...
llvm-svn: 85571
2009-10-30 02:08:26 +00:00
4246f00e0c
Add support for BlockAddress static initializers.
...
llvm-svn: 85562
2009-10-30 01:45:18 +00:00
2f8ccf2bf4
Add a FIXME comment.
...
llvm-svn: 85559
2009-10-30 01:38:20 +00:00
c83dc4b506
Add some comments.
...
llvm-svn: 85558
2009-10-30 01:34:35 +00:00
6c9388011b
Initial target-independent CodeGen support for BlockAddresses.
...
llvm-svn: 85556
2009-10-30 01:27:03 +00:00
faa7660fd0
Between scheduling regions, correctly maintain anti-dep breaking state so that we don't incorrectly rename registers that span these regions.
...
llvm-svn: 85537
2009-10-29 23:30:59 +00:00
05efd893db
Remove some unnecessary spaces in debug output.
...
llvm-svn: 85536
2009-10-29 23:30:06 +00:00
554a75a973
Move some code from being emitted as boilerplate duplicated in every
...
*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.
llvm-svn: 85530
2009-10-29 22:30:23 +00:00
9f1b2d4619
Fix a couple of bugs in aggressive anti-dep breaking.
...
llvm-svn: 85522
2009-10-29 19:17:04 +00:00
94f8f87890
Refactor complicated predicate into a separate function.
...
llvm-svn: 85519
2009-10-29 18:40:06 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
104f57cae8
Refactor the code for unfolding a load into a separate function.
...
llvm-svn: 85515
2009-10-29 17:47:20 +00:00
c44768ae69
Reapply r85338.
...
llvm-svn: 85514
2009-10-29 17:39:46 +00:00
cad78a7634
When the function is doing dynamic stack realignment, the spill slot will be
...
indexed via the stack pointer, even if a frame pointer is present. Update the
heuristic to place it nearest the stack pointer in that case, rather than
nearest the frame pointer.
llvm-svn: 85474
2009-10-29 02:33:47 +00:00
8829fc3a18
When there is a 2-instruction spill sequence, record
...
the second (store) instruction in SpillSlotToUsesMap
consistently. I don't think this matters functionally,
but it's cleaner and Evan wants it this way.
llvm-svn: 85463
2009-10-29 01:15:40 +00:00
3505c94923
Don't put in these EH changes.
...
llvm-svn: 85460
2009-10-29 00:37:35 +00:00
a8eceedb82
Reverting r85338 for now. It's causing a bootstrap failure on PPC darwin9.
...
--- Reverse-merging r85338 into '.':
U lib/CodeGen/SimpleRegisterCoalescing.cpp
U lib/CodeGen/SimpleRegisterCoalescing.h
llvm-svn: 85454
2009-10-29 00:22:16 +00:00
3ab552ec74
Reimplement BranchFolding change to avoid tail merging for a 1 instruction
...
common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.
llvm-svn: 85441
2009-10-28 22:10:20 +00:00
14f162d9dc
When we generate spill code, then decide we don't need
...
to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec). We need to
remove the store in this case. Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here. 7331562.
llvm-svn: 85437
2009-10-28 21:56:18 +00:00
1fd4c577d2
Make sure we return the right sized type here.
...
llvm-svn: 85436
2009-10-28 21:32:16 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
...
I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
e30ed53c05
Make AntiDepReg.h internal.
...
llvm-svn: 85412
2009-10-28 18:29:54 +00:00
14ca753e28
Don't call SDNode::isPredecessorOf when it isn't necessary. If the load's
...
chains have no users, they can't be predecessors of the condition.
llvm-svn: 85394
2009-10-28 15:28:02 +00:00
57780dfdfc
Simplify this code: if the unfolded load can't be hoisted, just delete
...
the new instructions and leave the old one in place.
llvm-svn: 85393
2009-10-28 15:23:36 +00:00
cd139c0373
Rewrite SelectionDAG::isPredecessorOf to be iterative instead of
...
recursive to avoid consuming extraordinary amounts of stack space
when processing tall graphs.
llvm-svn: 85369
2009-10-28 03:44:30 +00:00
1b44f10ff4
Teach MachineLICM to unfold loads from constant memory from
...
otherwise unhoistable instructions in order to allow the loads
to be hoisted.
llvm-svn: 85364
2009-10-28 03:21:57 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
...
llvm-svn: 85361
2009-10-28 01:43:28 +00:00
4b46cbfc23
Mark dead physregdefs dead immediately. This helps MachineSink and
...
MachineLICM and other things which run before LiveVariables is run.
llvm-svn: 85360
2009-10-28 01:13:53 +00:00
75d6a4afd2
Allow constants of different types to share constant pool entries
...
if they have compatible encodings.
llvm-svn: 85359
2009-10-28 01:12:16 +00:00
d04cb6d0fa
rename indbr -> indirectbr to appease the residents of #llvm.
...
llvm-svn: 85351
2009-10-28 00:19:10 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
...
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
cd3939ef0e
Fixed a bug in the coalescer where intervals were occasionally merged despite a real interference. This fixes rdar://problem/7157961.
...
llvm-svn: 85338
2009-10-27 23:16:58 +00:00
a5e078b677
Update the MachineBasicBlock CFG for an indirect branch.
...
llvm-svn: 85325
2009-10-27 22:10:34 +00:00
a4374e66f0
Add CodeGen support for indirect branches.
...
llvm-svn: 85323
2009-10-27 21:56:26 +00:00
cfeaa48642
Do not held on to DenseMap slot accross map insertion. The insertion may cause the map to grow rending the slot invalid.
...
Use this opportunity to use ValueMap instead of DenseMap.
llvm-svn: 85298
2009-10-27 20:47:17 +00:00
26076a8f10
don't use stdio
...
llvm-svn: 85296
2009-10-27 20:42:54 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
...
llvm-svn: 85281
2009-10-27 19:56:55 +00:00
3ed871fe62
add enough support for indirect branch for the feature test to pass
...
(assembler,asmprinter, bc reader+writer) and document it. Codegen
currently aborts on it.
llvm-svn: 85274
2009-10-27 19:13:16 +00:00
0997991252
pseudosourcevalue is also still using getGlobalContext(), so it isn't
...
thread safe either.
llvm-svn: 85253
2009-10-27 17:02:08 +00:00
7a50b280c1
Add objectsize intrinsic and hook it up through codegen. Doesn't
...
do anything than return "I don't know" at the moment.
llvm-svn: 85189
2009-10-27 00:52:25 +00:00
de5ad42aa1
Remove FreeInst.
...
Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.
llvm-svn: 85176
2009-10-26 23:43:48 +00:00
e056d1077e
Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.
...
llvm-svn: 85166
2009-10-26 22:31:16 +00:00
661ea989e9
Define virtual destructor in *.cpp file.
...
llvm-svn: 85146
2009-10-26 19:41:00 +00:00
de11f36ab7
Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
...
llvm-svn: 85145
2009-10-26 19:32:42 +00:00
9aba0d9988
When checking whether a def of an aliased register is dead, ask the
...
machineinstr whether the aliased register is dead, rather than the original
register is dead. This allows it to get the correct answer when examining
an instruction like this:
CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead>
where EAX is dead but a subregister of it is still live. This fixes PR5294.
llvm-svn: 85135
2009-10-26 18:26:18 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
b81cb2a9a8
- Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
...
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
common for targets to operate on registers where the top bits are undef. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
= d0
When the insert_subreg is eliminated by the coalescer, the scavenger used to
complain. The previous fix was to keep to insert_subreg around. But that's
brittle and it's overly conservative when we want to use the scavenger to
allocate registers. It's actually legal and desirable for other instructions
to use the "undef" part of d0. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
s1 =
= s1
= d0
We probably need add a "partial-undef" marker on machine operand so the
machine verifier would not complain.
llvm-svn: 85091
2009-10-26 04:56:07 +00:00
56869f22c4
Move DataTypes.h to include/llvm/System, update all users. This breaks the last
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direct inclusion edge from System to Support.
llvm-svn: 85086
2009-10-26 01:35:46 +00:00
4c799e65d7
Use isIdentityCopy. Fix a bozo bug (flipped condition) in InvalidateRegDef.
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llvm-svn: 85047
2009-10-25 07:51:47 +00:00
5d2245b210
Code clean up.
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llvm-svn: 85046
2009-10-25 07:49:57 +00:00
19348415c4
Do not delete identity insert_subreg even if dest is virtual. Let later passes delete them. This avoids register scavenger complain.
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llvm-svn: 85045
2009-10-25 07:48:51 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
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VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
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Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
5027d359e7
When the scavenger is looking for a good candidate location to restore from a
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spill, it should avoid doing so inside the live range of a virtual register.
llvm-svn: 85026
2009-10-25 00:45:07 +00:00
8f4078ba39
Rename isLoopExit to isLoopExiting, for consistency with the wording
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used elsewhere - an exit block is a block outside the loop branched to
from within the loop. An exiting block is a block inside the loop that
branches out.
llvm-svn: 85019
2009-10-24 23:34:26 +00:00
b4a1347be2
Add some asserts to catch copyRegToReg() fails early
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llvm-svn: 84983
2009-10-24 00:27:00 +00:00
d638bc310a
Identity copies should not contribute to spill weight.
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llvm-svn: 84978
2009-10-23 23:09:19 +00:00
4ef112be62
APInt-ify the gep scaling code, so that it correctly handles the case where
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the scale overflows pointer-sized arithmetic. This fixes PR5281.
llvm-svn: 84954
2009-10-23 17:57:43 +00:00
6aea1a2a5a
Neuter stack protectors by only checking character arrays. This is what GCC
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does.
llvm-svn: 84916
2009-10-23 00:01:05 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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llvm-svn: 84911
2009-10-22 23:19:17 +00:00
4f0b8d7861
Tidying up some code and comments. No functionality change.
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llvm-svn: 84894
2009-10-22 20:48:59 +00:00
8626367e38
Fix null pointer dereference.
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llvm-svn: 84806
2009-10-22 00:15:17 +00:00
ff97acd8f1
Revert the main portion of r31856. It was causing BranchFolding
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to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.
This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.
llvm-svn: 84803
2009-10-22 00:03:58 +00:00
c16c8c707b
The spill restore needs to be resolved to the SP/FP just like the spill
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llvm-svn: 84792
2009-10-21 22:59:56 +00:00
bc30143451
Cleanup of frame index scavenging. Better code flow and more accurately
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handles T2 and ARM use cases.
llvm-svn: 84761
2009-10-21 15:26:21 +00:00
f781bd8947
Need a comma after imp-use.
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llvm-svn: 84749
2009-10-21 07:56:02 +00:00
682a2d154a
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
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llvm-svn: 84727
2009-10-21 01:44:44 +00:00
4388beb884
Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.
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llvm-svn: 84691
2009-10-20 22:50:43 +00:00
a6faf60831
Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)
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transform.
llvm-svn: 84683
2009-10-20 21:37:45 +00:00
16edcd724a
Oops. Backing out 84681 - needs to wait for the indexing patch.
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llvm-svn: 84682
2009-10-20 21:28:22 +00:00
d8938d1ca8
Added some debugging output to pre-alloc splitting.
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llvm-svn: 84681
2009-10-20 21:25:13 +00:00
baf6dd26ea
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
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llvm-svn: 84658
2009-10-20 19:54:44 +00:00
d2ba321930
Better handle instructions that re-def a scratch register
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llvm-svn: 84657
2009-10-20 19:52:35 +00:00
5f2581a37a
Register re-use for scavenged frame indices must check for re-deginition
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of the register in the instruction which kills the scavenged value.
llvm-svn: 84641
2009-10-20 16:33:57 +00:00
c0964a571b
Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks are
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tracked. Instead of trying to manually keep track of these locations
while doing complex modifications, just recompute them when they're needed.
This fixes a bug in which the TopMBB and BotMBB were not correctly updated,
leading to invalid transformations.
llvm-svn: 84598
2009-10-20 04:50:37 +00:00
ccc2e0cbda
Trim unnecessary includes.
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llvm-svn: 84597
2009-10-20 04:23:20 +00:00
d383c2f6ba
Add getTopBlock and getBottomBlock member functions to MachineLoopInfo.
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llvm-svn: 84596
2009-10-20 04:16:37 +00:00
fa4bcaec7c
If the physical register being spilled does not have an interval, spill its sub-registers instead.
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llvm-svn: 84586
2009-10-20 01:31:09 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
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llvm-svn: 84585
2009-10-20 01:26:58 +00:00
5a5a3bc5d4
Adjust the scavenge register spilling to allow the target to choose an
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appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
llvm-svn: 84554
2009-10-19 22:27:30 +00:00
8383c3d7f3
Revert r84295, this unbreaks llvm-gcc bootstrap on x86-64/linux
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llvm-svn: 84516
2009-10-19 18:21:09 +00:00
b0db9917af
Fix a typo in a comment.
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llvm-svn: 84504
2009-10-19 14:56:05 +00:00
20a327b31f
Change a few instance variables to be local variables.
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llvm-svn: 84503
2009-10-19 14:52:05 +00:00
f0236e011e
Spill slots cannot alias.
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llvm-svn: 84432
2009-10-18 19:58:47 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
0b8db2dab7
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
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llvm-svn: 84411
2009-10-18 06:27:36 +00:00
54279632f3
Fix my -Asserts warning fix.
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llvm-svn: 84372
2009-10-17 23:15:04 +00:00
47dfc9ae1b
Suppress -Asserts warning.
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llvm-svn: 84327
2009-10-17 09:33:00 +00:00
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
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llvm-svn: 84326
2009-10-17 09:20:14 +00:00
David Goodwin