6 Commits

Author	SHA1	Message	Date
Krzysztof Parzyszek	64e5d7d3ae	[Hexagon] Reorganize and update instruction patterns ... llvm-svn: 316228	2017-10-20 19:33:12 +00:00
Krzysztof Parzyszek	a72fad980c	[Hexagon] Replace instruction definitions with auto-generated ones ... llvm-svn: 294753	2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek	a7c5f0409c	[Hexagon] Split double registers ... llvm-svn: 250549	2015-10-16 20:38:54 +00:00
Krzysztof Parzyszek	cd97c985c7	[Hexagon] Use A2_tfrsi for constant pool and jump table addresses ... llvm-svn: 235535	2015-04-22 18:25:53 +00:00
David Blaikie	a79ac14fa6	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction ... Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794	2015-02-27 21:17:42 +00:00
Jyotsna Verma	803e506fec	Hexagon: Pass to replace tranfer/copy instructions into combine instruction ... where possible. llvm-svn: 181817	2013-05-14 18:54:06 +00:00