Commit Graph

228846 Commits

Author SHA1 Message Date
Richard Smith 9b296e3fd8 When deducing template parameters from base classes of an argument type, don't
preserve any deduced types from a failed deduction to a subsequent attempt at
deduction. Patch by Erik Pilkington!

llvm-svn: 267444
2016-04-25 19:09:05 +00:00
Francis Ricci 86f37ffa6f test commit
llvm-svn: 267443
2016-04-25 19:02:05 +00:00
Johannes Doerfert d5c369f460 Do not check all GEPs for assumptions
Before, we checked all GEPs in a statement in order to derive
  out-of-bound assumptions. However, this can not only introduce new
  parameters but it is also not clear what we can learn from GEPs that
  are not immediately used in a memory accesses inside the SCoP. As this
  case is very rare, no actual change in the behaviour is expected.

llvm-svn: 267442
2016-04-25 18:55:15 +00:00
Johannes Doerfert c78ce7dc21 Only add user assumptions on known parameters [NFC]
Before, assumptions derived from llvm.assume could reference new
  parameters that were not known to the SCoP before. These were neither
  beneficial to the representation nor to the user that reads the
  emitted remark. Now we project them out and keep only user assumptions
  on known parameters. Nevertheless, the new parameters are still part
  of the SCoPs parameter space as the SCEVAffinator currently adds them
  on demand.

llvm-svn: 267441
2016-04-25 18:51:27 +00:00
Philip Reames 3bb2832900 [LVI] Clarify comments describing the lattice values
There has been much recent confusion about the partition in the lattice between constant and non-constant values.  Hopefully, documenting this will prevent confusion going forward.

llvm-svn: 267440
2016-04-25 18:48:43 +00:00
Philip Reames 6671577eb3 [LVI] Split solveBlockValueConstantRange into two [NFC]
This function handled both unary and binary operators.  Cloning and specializing leads to much easier to follow code with minimal duplicatation.

llvm-svn: 267438
2016-04-25 18:30:31 +00:00
Evgeniy Stepanov d194e51726 [gold] Fix linkInModule and extend common.ll test.
Fix early exit from linkInModule. IRMover::move returns false on
success and true on error.

Add a few more cases of merged common linkage variables with
different sizes and alignments.

llvm-svn: 267437
2016-04-25 18:23:29 +00:00
Chad Rosier bbabc85031 Fix typo from r267432.
llvm-svn: 267436
2016-04-25 18:20:27 +00:00
Krzysztof Parzyszek a4602b5be1 [Hexagon] Use llvm-mc instead of llc in an MC testcase
Remember to svn add the new file.

llvm-svn: 267435
2016-04-25 18:09:36 +00:00
Krzysztof Parzyszek 4ea9bd72df [Hexagon] Use llvm-mc instead of llc in an MC testcase
llvm-svn: 267434
2016-04-25 18:08:33 +00:00
Krzysztof Parzyszek e8e754da74 [Hexagon] Register save/restore functions do not follow regular conventions
Do not mark them as modifying any of the volatile registers by default.

llvm-svn: 267433
2016-04-25 17:49:44 +00:00
Chad Rosier 4c4e3336b8 [ValueTracking] Add an additional test case for r266767 where one operand is a const.
llvm-svn: 267432
2016-04-25 17:41:48 +00:00
Zachary Turner 0a43efea95 Resubmit "Refactor raw pdb dumper into library"
This fixes a number of endianness issues as well as an ODR
violation that hopefully causes everything to be happy.

llvm-svn: 267431
2016-04-25 17:38:08 +00:00
Chad Rosier e2cbd13e56 [ValueTracking] Improve isImpliedCondition when the dominating cond is false.
llvm-svn: 267430
2016-04-25 17:23:36 +00:00
Davide Italiano 8d728fccb8 [gold-plugin] Remove dead assignment. NFC.
llvm-svn: 267429
2016-04-25 17:18:45 +00:00
Davide Italiano 63593f6202 [ELFRelocs] Other architectures do not have *_NUM reloc.
It also seems to be unused. Get rid of it.
Thanks to Rafael for pointing out.

llvm-svn: 267428
2016-04-25 17:13:39 +00:00
Adrian Prantl 2c0b0ab624 dsymutil: Only warn about clang module DWO id mismatches in verbose mode.
Until PR27449 (https://llvm.org/bugs/show_bug.cgi?id=27449) is fixed in
clang this warning is pointless, since ASTFileSignatures will change
randomly when a module is rebuilt.

rdar://problem/25610919

llvm-svn: 267427
2016-04-25 17:04:32 +00:00
Sanjay Patel 43c7af6889 add tests for potential CGP transform (PR27344)
llvm-svn: 267426
2016-04-25 16:56:52 +00:00
Michael Zuckerman fa508e8b6d [Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, KORTEST, KXNOR, KXOR, KUNPACK instruction set.
Differential Revision: http://reviews.llvm.org/D19466

llvm-svn: 267425
2016-04-25 16:42:29 +00:00
Jacques Pienaar 522031bd05 [lanai] Expand findClosestSuitableAluInstr check to consider offset register.
Previously findClosestSuitableAluInstr was only considering the base register when checking the current instruction for suitability. Expand check to consider the offset if the offset is a register.

llvm-svn: 267424
2016-04-25 16:41:21 +00:00
Johannes Doerfert 4e3bb7b98c Refactor Scop parameter handling
The new handling is consistent with the remaining code, e.g., we do
  not create a new parameter id for each lookup call but copy an
  existing one. Additionally, we now use the implicit order defined by
  the Parameters set instead of an explicit one defined in a map.

llvm-svn: 267423
2016-04-25 16:15:13 +00:00
Tamas Berghammer 0237eda929 Fix ARM attribute parsing for Android after rL267291
Differential revision: http://reviews.llvm.org/D19480

llvm-svn: 267422
2016-04-25 15:51:45 +00:00
Todd Fiala 6d547205f0 skip TestBitfields.py on OS X
tracked by:
https://llvm.org/bugs/show_bug.cgi?id=27515

llvm-svn: 267421
2016-04-25 15:48:34 +00:00
Marcin Koscielnicki 1c1af6ef77 [PR27390] [CodeGen] Reject indexed loads in CombinerDAG.
visitAND, when folding and (load) forgets to check which output of
an indexed load is involved, happily folding the updated address
output on the following testcase:

target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

%typ = type { i32, i32 }

define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) {
  %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1
  %1 = load i32, i32* %b, align 4
  %2 = ptrtoint i32* %b to i64
  %3 = and i64 %2, -35184372088833
  %4 = inttoptr i64 %3 to i32*
  %_msld = load i32, i32* %4, align 4
  %zzz = add i32 %1,  %_msld
  ret i32 %zzz
}

Fix this by checking ResNo.

I've found a few more places that currently neglect to check for
indexed load, and tightened them up as well, but I don't have test
cases for them.  In fact, they might not be triggerable at all,
at least with current targets.  Still, better safe than sorry.

Differential Revision: http://reviews.llvm.org/D19202

llvm-svn: 267420
2016-04-25 15:43:44 +00:00
Hrvoje Varga c2dd5d223a [mips][microMIPS] Revert commit r267137
Commit r267137 was the reason for failing tests in LLVM test suite.

llvm-svn: 267419
2016-04-25 15:40:08 +00:00
Zlatko Buljan b43d4bcbd5 [mips][microMIPS] Revert commit r266977
Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...

llvm-svn: 267418
2016-04-25 15:34:57 +00:00
Sanjay Patel 0fc4137065 [x86] auto-generate checks for cmov tests
llvm-svn: 267417
2016-04-25 15:26:57 +00:00
Eric Liu 4cfb88a936 Added Fixer implementation and fix() interface in clang-format for removing redundant code.
Summary:
After applying replacements, redundant code like extra commas or empty namespaces
might be introduced. Fixer can detect and remove any redundant code introduced by replacements.
The current implementation only handles redundant commas.

Reviewers: djasper, klimek

Subscribers: ioeric, mprobst, klimek, cfe-commits

Differential Revision: http://reviews.llvm.org/D18551

llvm-svn: 267416
2016-04-25 15:09:22 +00:00
Etienne Bergeron 06c14ec31e Fix incorrect redundant expression in target AMDGPU.
Summary:
The expression is detected as a redundant expression.
Turn out, this is probably a bug.

```
/home/etienneb/llvm/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:306:26: warning: both side of operator are equivalent [misc-redundant-expression]
  if (isSMRD(*FirstLdSt) && isSMRD(*FirstLdSt)) {
```

Reviewers: rnk, tstellarAMD

Subscribers: arsenm, cfe-commits

Differential Revision: http://reviews.llvm.org/D19460

llvm-svn: 267415
2016-04-25 15:06:33 +00:00
Michael Zuckerman edc82fe3ef [Clang][Builtin][AVX512]Adding intrinsics for vfpclass{sd|ss} vfpclass{pd|ps} instruction set
Differential Revision: http://reviews.llvm.org/D19476

llvm-svn: 267414
2016-04-25 14:48:23 +00:00
Artem Dergachev 70247e69b1 [analyzer] Let TK_PreserveContents span across the whole base region.
If an address of a field is passed through a const pointer,
the whole structure's base region should receive the
TK_PreserveContents trait and avoid invalidation.

Additionally, include a few FIXME tests shown up during testing.

Differential Revision: http://reviews.llvm.org/D19057

llvm-svn: 267413
2016-04-25 14:44:25 +00:00
David Majnemer dd21523653 [WinEH] Update SplitAnalysis::computeLastSplitPoint to cope with multiple EH successors
We didn't have logic to correctly handle CFGs where there was more than
one EH-pad successor (these are novel with WinEH).
There were situations where a register was live in one exceptional
successor but not another but the code as written would only consider
the first exceptional successor it found.

This resulted in split points which were insufficiently early if an
invoke was present.

This fixes PR27501.

N.B.  This removes getLandingPadSuccessor.

llvm-svn: 267412
2016-04-25 14:31:32 +00:00
Silviu Baranga 82d04260b7 [ARM] Add support for the X asm constraint
Summary:
This patch adds support for the X asm constraint.

To do this, we lower the constraint to either a "w" or "r" constraint
depending on the operand type (both constraints are supported on ARM).

Fixes PR26493

Reviewers: t.p.northover, echristo, rengolin

Subscribers: joker.eph, jgreenhalgh, aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D19061

llvm-svn: 267411
2016-04-25 14:29:18 +00:00
Artem Tamazov d6468666b5 [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.
Added hwreg(reg[,offset,width]) syntax.
Default offset = 0, default width = 32.
Possibility to specify 16-bit immediate kept.
Added out-of-range checks.
Disassembling is always to hwreg(...) format.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19329

llvm-svn: 267410
2016-04-25 14:13:51 +00:00
Rafael Espindola 926bff8c3e Add support for R_X86_64_PC64.
llvm-svn: 267409
2016-04-25 14:05:44 +00:00
Johannes Doerfert c3596284c3 Model zext-extend instructions
A zero-extended value can be interpreted as a piecewise defined signed
  value. If the value was non-negative it stays the same, otherwise it
  is the sum of the original value and 2^n where n is the bit-width of
  the original (or operand) type. Examples:
    zext i8 127 to i32 -> { [127] }
    zext i8  -1 to i32 -> { [256 + (-1)] } = { [255] }
    zext i8  %v to i32 -> [v] -> { [v] | v >= 0; [256 + v] | v < 0 }

  However, LLVM/Scalar Evolution uses zero-extend (potentially lead by a
  truncate) to represent some forms of modulo computation. The left-hand side
  of the condition in the code below would result in the SCEV
  "zext i1 <false, +, true>for.body" which is just another description
  of the C expression "i & 1 != 0" or, equivalently, "i % 2 != 0".

    for (i = 0; i < N; i++)
      if (i & 1 != 0 /* == i % 2 */)
        /* do something */

  If we do not make the modulo explicit but only use the mechanism described
  above we will get the very restrictive assumption "N < 3", because for all
  values of N >= 3 the SCEVAddRecExpr operand of the zero-extend would wrap.
  Alternatively, we can make the modulo in the operand explicit in the
  resulting piecewise function and thereby avoid the assumption on N. For the
  example this would result in the following piecewise affine function:
  { [i0] -> [(1)] : 2*floor((-1 + i0)/2) = -1 + i0;
    [i0] -> [(0)] : 2*floor((i0)/2) = i0 }
  To this end we can first determine if the (immediate) operand of the
  zero-extend can wrap and, in case it might, we will use explicit modulo
  semantic to compute the result instead of emitting non-wrapping assumptions.

  Note that operands with large bit-widths are less likely to be negative
  because it would result in a very large access offset or loop bound after the
  zero-extend. To this end one can optimistically assume the operand to be
  positive and avoid the piecewise definition if the bit-width is bigger than
  some threshold (here MaxZextSmallBitWidth).

  We choose to go with a hybrid solution of all modeling techniques described
  above. For small bit-widths (up to MaxZextSmallBitWidth) we will model the
  wrapping explicitly and use a piecewise defined function. However, if the
  bit-width is bigger than MaxZextSmallBitWidth we will employ overflow
  assumptions and assume the "former negative" piece will not exist.

llvm-svn: 267408
2016-04-25 14:01:36 +00:00
Pavel Labath 73151ff298 Skip TestBitfileds on linux
Test added in r267248 exposed a bug in handling of dwarf produced by clang>=3.9, which causes a
crash during expression evaluation. Skip the test until this is sorted out.

llvm-svn: 267407
2016-04-25 14:00:23 +00:00
Anna Thomas 95f68aa7eb Test commit: modified comment. NFC
llvm-svn: 267406
2016-04-25 13:58:05 +00:00
Omair Javaid cbd7f8847e Handle invalid values of PLT entry size generated by linker
Make sure we figure out correct plt entry field in case linker has generated a small value below realistic entry size like 4 bytes or below.

Differential revision: http://reviews.llvm.org/D19252

llvm-svn: 267405
2016-04-25 13:45:39 +00:00
Johannes Doerfert 517d8d2f94 Check only loop control of loops that are part of the region
This also removes a duplicated line of code in the region generator
  that caused a SPEC benchmark to fail with the new SCoPs.

llvm-svn: 267404
2016-04-25 13:37:24 +00:00
Johannes Doerfert a4dd8ef40f Initialize the invalid domain of an access with an empty set
llvm-svn: 267403
2016-04-25 13:36:23 +00:00
Johannes Doerfert e4459a24cc Do not propagate invalid domains over back edges
llvm-svn: 267402
2016-04-25 13:34:50 +00:00
Johannes Doerfert f560b3d2db Introduce a parameter set type [NFC]
llvm-svn: 267401
2016-04-25 13:33:07 +00:00
Johannes Doerfert ec8a217729 Remove unnecessary argument of the SCEVValidator [NFC]
llvm-svn: 267400
2016-04-25 13:32:36 +00:00
Chad Rosier 3d75f8ce9e Typo. NFC.
llvm-svn: 267399
2016-04-25 13:25:14 +00:00
Michael Zuckerman fcf32c2f00 [Clang][AVX512][BUILTIN] Adding intrinsics for VSCATTERPF{1|0}{DPS|QPS|DPD|QPD} instruction set
Differential Revision: http://reviews.llvm.org/D19313

llvm-svn: 267398
2016-04-25 13:01:40 +00:00
Krzysztof Parzyszek e6ee481bdf [Hexagon] Correctly set "Flags" in ELF header
llvm-svn: 267397
2016-04-25 12:49:47 +00:00
Rafael Espindola d79073dc2a Simplify. NFC.
llvm-svn: 267396
2016-04-25 12:32:19 +00:00
Alexey Bataev 7292c29bb5 [OPENMP 4.5] Codegen for 'taskloop' directive.
The taskloop construct specifies that the iterations of one or more associated loops will be executed in parallel using OpenMP tasks. The iterations are distributed across tasks created by the construct and scheduled to be executed.
The next code will be generated for the taskloop directive:
    #pragma omp taskloop num_tasks(N) lastprivate(j)
        for( i=0; i<N*GRAIN*STRIDE-1; i+=STRIDE ) {
          int th = omp_get_thread_num();
          #pragma omp atomic
            counter++;
          #pragma omp atomic
            th_counter[th]++;
          j = i;
    }

Generated code:
task = __kmpc_omp_task_alloc(NULL,gtid,1,sizeof(struct
task),sizeof(struct shar),&task_entry);
psh = task->shareds;
psh->pth_counter = &th_counter;
psh->pcounter = &counter;
psh->pj = &j;
task->lb = 0;
task->ub = N*GRAIN*STRIDE-2;
task->st = STRIDE;
__kmpc_taskloop(
NULL,             // location
gtid,             // gtid
task,             // task structure
1,                // if clause value
&task->lb,        // lower bound
&task->ub,        // upper bound
STRIDE,           // loop increment
0,                // 1 if nogroup specified
2,                // schedule type: 0-none, 1-grainsize, 2-num_tasks
N,                // schedule value (ignored for type 0)
(void*)&__task_dup_entry // tasks duplication routine
);

llvm-svn: 267395
2016-04-25 12:22:29 +00:00
Rafael Espindola a6c4d2f197 Delete needsCopyRelImpl. It is redundant with getRelExpr.
llvm-svn: 267394
2016-04-25 12:05:56 +00:00